On 6/6/19 9:58 AM, Srinivas Kandagatla wrote:
On 06/06/2019 15:28, Pierre-Louis Bossart wrote:
On 6/6/19 6:22 AM, Srinivas Kandagatla wrote:
multi bank switching code takes lock on condition but releases without
any check resulting in below warning.
This patch fixes this.
Question to make
On Sun, May 26, 2019 at 10:07:50AM +0530, Vidya Sagar wrote:
> Add support for Synopsys DesignWare core IP based PCIe host controller
> present in Tegra194 SoC.
>
> Signed-off-by: Vidya Sagar
> ---
> Changes since [v7]:
> * Addressed review comments from Thierry
>
> Changes since [v6]:
> * Remov
This patch series adds a reset-simple compatible string for DesignWare
IPs allowing active high and low resets inputs.
Also adds the corresponding documentation.
Gustavo Pimentel (1):
reset: Add DesignWare IP support to simple reset
Luis Oliveira (1):
dt-bindings: Document the DesignWare IP
On Wed, Jun 05, 2019 at 01:14:04PM -0700, Andy Lutomirski wrote:
>
>
> > On Jun 5, 2019, at 8:17 AM, Jarkko Sakkinen
> > wrote:
> >
> >> On Tue, Jun 04, 2019 at 10:10:22PM +, Xing, Cedric wrote:
> >> A bit off topic here. This mmap()/mprotect() discussion reminds me a
> >> question (guess
From: Gustavo Pimentel
The reset-simple driver can be now used on DesignWare IPs by
default by selecting the following compatible strings:
- snps,dw-high-reset for active high resets inputs
- snps,dw-low-reset for active low resets inputs
Signed-off-by: Gustavo Pimentel
Signed-off-by: Luis Ol
This adds documentation of device tree bindings for the
DesignWare IP reset controller.
Signed-off-by: Gustavo Pimentel
Signed-off-by: Luis Oliveira
---
Changelog
- Add active low configuration example
- Fix compatible string in the active high example
.../devicetree/bindings/reset/snps,dw-res
Standardize dump presentation for va, dma and da dumps by adding
"0x" prefix for virtual address.
Fixes: 276ec9934231("remoteproc: replace "%p" with "%pK"")
Signed-off-by: Arnaud Pouliquen
---
drivers/remoteproc/remoteproc_debugfs.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --
Add csi node for i.MX6UL SoC.
Reviewed-by: Fabio Estevam
Signed-off-by: Sébastien Szymanski
---
Changes for v2:
- only "mclk" clock is required now.
arch/arm/boot/dts/imx6ul.dtsi | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/im
Hi Linus,
please pull some additional fixes and cleanups for the parisc architecture from:
git://git.kernel.org/pub/scm/linux/kernel/git/deller/parisc-linux.git
parisc-5.2-3
Changes include
- Fix crashes when accessing PCI devices on some machines like C240 and J5000.
The crashes were trigg
On Thu, Jun 06, 2019 at 10:20:40AM -0500, Jassi Brar wrote:
> On Thu, Jun 6, 2019 at 7:51 AM Sudeep Holla wrote:
>
> >
> > > BTW, this is not going to be the end of SCMI troubles (I believe
> > > that's what his client is). SCMI will eventually have to be broken up
> > > in layers (protocol and tr
On Thu, Jun 06, 2019 at 10:27:43AM -0400, Jerome Glisse wrote:
> On Thu, Jun 06, 2019 at 11:16:44AM -0300, Jason Gunthorpe wrote:
> > On Mon, May 06, 2019 at 04:29:39PM -0700, rcampb...@nvidia.com wrote:
> > > From: Ralph Campbell
> > >
> > > There are no functional changes, just some coding styl
On 6/6/19 11:32 AM, Waiman Long wrote:
> On 6/6/19 11:21 AM, Alex Kogan wrote:
Also, the paravirt code is under arch/x86, while CNA is generic (not
x86-specific). Do you still want to see CNA-related patching residing
under arch/x86?
We still need a config option (somethin
Hey everyone,
I hope this is not going to start a trash fire.
While working on a new clone version I tried to find out what the
current naming conventions for syscall revisions is. I was told and
seemed to be able to confirm through the syscall list that revisions of
syscalls are for the most par
Hi George,
On 05/06/2019 15:12, George Hung wrote:
> Add support for the Nuvoton NPCM7xx SoC EDAC driver
Could you say something about what the NPCM7xx SoC is, and what errors its
memory
controller can detect?
The commit message is for describing what/why this code was added.
Is this Cadence D
On Thu 06 Jun 08:38 PDT 2019, Arnaud Pouliquen wrote:
> Standardize dump presentation for va, dma and da dumps by adding
> "0x" prefix for virtual address.
>
> Fixes: 276ec9934231("remoteproc: replace "%p" with "%pK"")
>
> Signed-off-by: Arnaud Pouliquen
Applied
Thanks,
Bjorn
> ---
> driver
On Tue, 28 May 2019 18:59:56 +0800
Chun-Hung Wu wrote:
> Hi Matthias:
>
> Thanks for your suggestion, I think device_links is a good way to
> make dependency of module's suspend/resume order.
>
> Hi Jonathan:
>
> Is it ok to keep using late_suspend and early_resume, or do you think
> it's
On Tue, 4 Jun 2019 10:26:56 +1000
"Tobin C. Harding" wrote:
> Currently vfs.rst does not render well into HTML the method descriptions
> for VFS data structures. We can improve the HTML output by putting the
> description string on a new line following the method name.
>
> Suggested-by: Jonath
Hi George,
On 05/06/2019 15:12, George Hung wrote:
> Add device tree documentation for Nuvoton BMC ECC
(Nit: The DT folk prefer patches adding bindings to come first in the series,
before the
driver that uses them).
> diff --git a/Documentation/devicetree/bindings/edac/npcm7xx-sdram-edac.txt
On 6/6/19 8:43 AM, Enrico Weigelt, metux IT consult wrote:
> From: Enrico Weigelt
>
> fix an uninitialized variable:
>
> CC net/ipv4/fib_semantics.o
> net/ipv4/fib_semantics.c: In function 'fib_check_nh_v4_gw':
> net/ipv4/fib_semantics.c:1027:12: warning: 'err' may be used uninitialized i
Hi!
On Thursday 06 June 2019 16:53:09 Jean Delvare wrote:
> Hi Pali,
>
> On Wed, 5 Jun 2019 00:33:03 +0200, Pali Rohár wrote:
> > Dell platform team told us that some (DMI whitelisted) Dell Latitude
> > machines have ST microelectronics accelerometer at I2C address 0x29.
> >
> > Presence of tha
On 6/6/19 12:19 PM, Borut Seljak wrote:
> Remove spin_lock_irqsave in stm32_config_rs485, it cause recursive locking.
> Already locked in uart_set_rs485_config.
>
> fixes: 1bcda09d291081 ("serial: stm32: add support for RS485 hardware control
> mode")
>
> Signed-off-by: Borut Seljak
Hi Borut,
On Thu, Jun 06, 2019 at 12:41:29PM -0300, Jason Gunthorpe wrote:
> On Thu, Jun 06, 2019 at 10:27:43AM -0400, Jerome Glisse wrote:
> > On Thu, Jun 06, 2019 at 11:16:44AM -0300, Jason Gunthorpe wrote:
> > > On Mon, May 06, 2019 at 04:29:39PM -0700, rcampb...@nvidia.com wrote:
> > > > From: Ralph Camp
On Thu, 6 Jun 2019 11:13:52 +
"Ardelean, Alexandru" wrote:
> On Wed, 2019-06-05 at 17:35 -0300, Renato Lui Geh wrote:
> > [External]
> >
> >
> > On 05/26, Jonathan Cameron wrote:
> > > On Fri, 24 May 2019 22:26:30 -0300
> > > Renato Lui Geh wrote:
> > >
> > > > This patch adds a YAML
> On 6 Jun 2019, at 11:34, Peter Zijlstra wrote:
>
>
> The VMCI driver is abusing atomic64_t and atomic_t, there is no actual
> atomic RmW operations around.
>
> Rewrite the code to use a regular u64 with READ_ONCE() and
> WRITE_ONCE() and a cast to 'unsigned long'. This fully preserves
> wha
Document "fsl,imx6ul-csi" entry.
Signed-off-by: Sébastien Szymanski
---
Changes for v2:
- New patch to document new "fsl,imx6ul-csi" entry.
Documentation/devicetree/bindings/media/imx7-csi.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/binding
On Mon, May 06, 2019 at 04:29:39PM -0700, rcampb...@nvidia.com wrote:
> @@ -924,6 +922,7 @@ int hmm_range_register(struct hmm_range *range,
> unsigned page_shift)
> {
> unsigned long mask = ((1UL << page_shift) - 1UL);
> + struct hmm *hmm;
>
> range->valid =
On Thu, Jun 06, 2019 at 02:53:23PM +0200, Pavel Machek wrote:
> Hi!
>
> > [ Upstream commit faf5a744f4f8d76e7c03912b5cd381ac8045f6ec ]
> >
> > clang -Wuninitialized incorrectly sees a variable being used without
> > initialization:
> >
> > drivers/scsi/lpfc/lpfc_nvme.c:2102:37: error: variable '
On Thu, Jun 6, 2019 at 5:25 PM Kirill Tkhai wrote:
>
> On 06.06.2019 18:18, Dmitry Vyukov wrote:
> > On Thu, Jun 6, 2019 at 4:54 PM Kirill Tkhai wrote:
> >>
> >> On 06.06.2019 17:40, Dmitry Vyukov wrote:
> >>> On Thu, Jun 6, 2019 at 3:43 PM Kirill Tkhai wrote:
>
> On 06.06.2019 16:13,
On Thu, Jun 06, 2019 at 11:34:28AM +0200, Peter Zijlstra wrote:
>
> The VMCI driver is abusing atomic64_t and atomic_t, there is no actual
> atomic RmW operations around.
>
> Rewrite the code to use a regular u64 with READ_ONCE() and
> WRITE_ONCE() and a cast to 'unsigned long'. This fully preser
On Thu, Jun 06, 2019 at 03:54:24PM +, Jorgen Hansen wrote:
>
>
> > On 6 Jun 2019, at 11:34, Peter Zijlstra wrote:
> >
> >
> > The VMCI driver is abusing atomic64_t and atomic_t, there is no actual
> > atomic RmW operations around.
> >
> > Rewrite the code to use a regular u64 with READ_ON
Add an entry for the meson video decoder for amlogic SoCs.
Signed-off-by: Maxime Jourdan
---
MAINTAINERS | 8
1 file changed, 8 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index b8fbf41865c2..7cf3ece9f0cb 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -10222,6 +10222,14 @@ S:
Add documentation for the meson vdec dts node.
Signed-off-by: Maxime Jourdan
Reviewed-by: Rob Herring
---
.../bindings/media/amlogic,vdec.txt | 71 +++
1 file changed, 71 insertions(+)
create mode 100644 Documentation/devicetree/bindings/media/amlogic,vdec.txt
diff -
Hi Miquel
The 05/12/2019 14:24, Miquel Raynal wrote:
EXTERNAL MAIL
EXTERNAL MAIL
Hi Piotr,
Sorry for de delay.
Piotr Sroka wrote on Thu, 21 Mar 2019 09:33:58
+:
The 03/05/2019 19:09, Miquel Raynal wrote:
>EXTERNAL MAIL
>
>
>Hi Piotr,
>
>Piotr Sroka wrote on Tue, 19 Feb 2019 16:18:
Amlogic SoCs feature a powerful video decoder unit able to
decode many formats, with a performance of usually up to 4k60.
This is a driver for this IP that is based around the v4l2 m2m framework.
It features decoding for:
- MPEG 1
- MPEG 2
Supported SoCs are: GXBB (S905), GXL (S905X/W/D), GXM (S
Hi everyone,
[V7] The Driver was moved to staging until it can pass future
specification & compliance tools.
[V6] Good news, the firmware situation is resolved. We have received a
redistributable license from Amlogic and the firmwares have been merged
in linux-firmware[5].
[V5] It's been a while
> On May 27, 2019, at 4:57 AM, Kairui Song wrote:
>
> On Sat, May 25, 2019 at 7:23 AM Josh Poimboeuf wrote:
>>
>> On Fri, May 24, 2019 at 10:20:52AM +0800, Kairui Song wrote:
>>> On Fri, May 24, 2019 at 1:27 AM Josh Poimboeuf wrote:
On Fri, May 24, 2019 at 12:41:59AM +0800, Kairu
On Wed, Jun 05, 2019 at 11:18:19PM -0700, Christoph Hellwig wrote:
> On Wed, Jun 05, 2019 at 06:45:36PM -0700, ira.we...@intel.com wrote:
> > From: Ira Weiny
> >
> > In order to support checking for a layout lease on a FS DAX inode these
> > calls need to know if FOLL_LONGTERM was specified.
> >
3745 Comm: irqbalance Tainted:
G W 5.2.0-rc3-next-20190606+ #2
[ 151.065548][ T3745] Hardware name: HPE Apollo
70 /C01_APACHE_MB , BIOS L50_5.13_1.0.9 03/01/2019
[ 151.076064][ T3745] Call trace:
[ 151.079218][ T3745] dump_backtrace+0x0/0x268
[ 151.083574]
The Lenovo Miix 630 is one of three ARM based (specifically Qualcomm
MSM8998) laptops that comes with Windows, and seems to have a dedicated
following of folks intrested to get Linux up and running on it.
This series adds support for the basic functionality this is validated
towork using devicetre
Clang warns:
drivers/vhost/vhost.c:2085:5: warning: macro expansion producing
'defined' has undefined behavior [-Wexpansion-to-defined]
#if VHOST_ARCH_CAN_ACCEL_UACCESS
^
drivers/vhost/vhost.h:98:38: note: expanded from macro
'VHOST_ARCH_CAN_ACCEL_UACCESS'
#define VHOST_ARCH_CAN_
Elan_i2c and hid-quirks work in conjunction to decide which devices each
driver will handle. Document this link in elan_i2c as a reminder that
updates to elan_i2c need to be mirrored to hid-quirks.
Signed-off-by: Jeffrey Hugo
---
drivers/input/mouse/elan_i2c_core.c | 4
1 file changed, 4 i
There needs to be coordination between hid-quirks and the elan_i2c driver
about which devices are handled by what drivers. Currently, both use
whitelists, which results in valid devices being unhandled by default,
when they should not be rejected by hid-quirks. This is quickly becoming
an issue.
This adds the initial DT for the Lenovo Miix 630 laptop. Supported
functionality includes USB (host), microSD-card, keyboard, and trackpad.
Signed-off-by: Jeffrey Hugo
---
arch/arm64/boot/dts/qcom/Makefile | 1 +
.../boot/dts/qcom/msm8998-clamshell.dtsi | 240
On Thu, Jun 06, 2019 at 12:58:55PM +0200, Jan Kara wrote:
> On Wed 05-06-19 18:45:40, ira.we...@intel.com wrote:
> > From: Ira Weiny
> >
> > If pages are actively gup pinned fail the truncate operation.
> >
> > Signed-off-by: Ira Weiny
> > ---
> > fs/ext4/inode.c | 3 +++
> > 1 file changed, 3
During a perf session we try to allocate buffers on the "node" associated
with the CPU the event is bound to. If it's not bound to a CPU, we use
the current CPU node, using smp_processor_id(). However this is unsafe
in a pre-emptible context and could generate the splats as below :
BUG: using smp
We have a few places where we call smp_processor_id() from preemptible
contexts during the perf buffer handling. We do this to figure out the
numa node for the allocation in case the event is not CPU bound. Instead
use NUMA_NO_NODE to avoid a splat.
Changes since v3:
- No function changes. Fix t
During a perf session we try to allocate buffers on the "node" associated
with the CPU the event is bound to. If it is not bound to a CPU, we
use the current CPU node, using smp_processor_id(). However this is unsafe
in a pre-emptible context and could generate the splats as below :
BUG: using sm
During a perf session we try to allocate buffers on the "node" associated
with the CPU the event is bound to. If it is not bound to a CPU, we
use the current CPU node, using smp_processor_id(). However this is unsafe
in a pre-emptible context and could generate the splats as below :
BUG: using sm
During a perf session we try to allocate buffers on the "node" associated
with the CPU the event is bound to. If it is not bound to a CPU, we
use the current CPU node, using smp_processor_id(). However this is unsafe
in a pre-emptible context and could generate the splats as below :
BUG: using sm
>
> i tested your patch against a qca 9984 chipset using SAE and without
> encryption. both did not work. the devices are connecting, but no data
> connection is possible
Hi Sebastian,
I tested Ryder's patch using mt76x2 as mesh peer and it works fine for me.
Could you please provide some more in
Hi Mathieu,
On 03/06/2019 20:01, Mathieu Poirier wrote:
Hi Suzuki,
On Thu, May 30, 2019 at 04:11:17PM +0100, Suzuki K Poulose wrote:
Update the documentation to reflect the new naming scheme with
latest changes.
Reported-by: Leo Yan
Cc: Mathieu Poirier
Cc: Jonathan Corbet
Signed-off-by: Su
On Thu, 6 Jun 2019 10:17:51 +
"Zhang, Tina" wrote:
> > -Original Message-
> > From: intel-gvt-dev [mailto:intel-gvt-dev-boun...@lists.freedesktop.org] On
> > Behalf Of kra...@redhat.com
> > Sent: Wednesday, June 5, 2019 6:10 PM
> > To: Zhang, Tina
> > Cc: Tian, Kevin ; k...@vger.kern
Quoting anson.hu...@nxp.com (2019-06-03 18:59:27)
> From: Anson Huang
>
> This patch adds i.MX8MN clock driver support.
>
> Signed-off-by: Anson Huang
> ---
> Changes since V2:
> - use platform driver model for this clock driver;
Can you also use platform device APIs like platform_*(),
On Thu, Jun 06, 2019 at 05:12:01PM +0200, Vitor Soares wrote:
> This patch series add i3c support for STM LSM6DSO and LSM6DSR sensors.
Why is the I2C list on CC? Is there something relevant I missed?
signature.asc
Description: PGP signature
26.05.2019 7:37, Vidya Sagar пишет:
> Synopsys DesignWare core based PCIe controllers in Tegra 194 SoC interface
> with Universal PHY (UPHY) module through a PIPE2UPHY (P2U) module.
> For each PCIe lane of a controller, there is a P2U unit instantiated at
> hardware level. This driver provides supp
The Keystone 2 66AK2HK/E/L 1G Ethernet Switch Subsystems contains The
Common Platform Time Sync (CPTS) module which is in general compatible with
CPTS module found on "legacy" TI AM3/4/5 SoCs. So, the basic support for
Keystone 2 CPTS is available by default, but not documented.
The Keystone 2 CPTS
Hi
The Keystone 2 66AK2HK/E/L 1G Ethernet Switch Subsystems contains The
Common Platform Time Sync (CPTS) module which is in general compatible with
CPTS module found on TI AM3/4/5 SoCs. So, the basic support for
Keystone 2 CPTS is available by default, but not documented and has never been
enable
Use devm_get_clk_from_child() instead of devm_clk_get() and this way allow
to group CPTS DT properties in sub-node for better code readability and
maintenance. Roll-back to devm_clk_get() if devm_get_clk_from_child()
fails for backward compatibility.
Signed-off-by: Grygorii Strashko
Acked-by: Ric
Allow to place CPTS properties in the child "cpts" DT node. For backward
compatibility - roll-back and read CPTS DT properties from parent node if
"cpts" node is not present.
Signed-off-by: Grygorii Strashko
Acked-by: Richard Cochran
---
drivers/net/ethernet/ti/netcp_ethss.c | 9 +++--
1 fi
Some CPTS instances, which can be found on KeyStone 2 1G Ethernet Switch
Subsystems, can control an external multiplexer that selects one of up to
32 clocks as time sync reference (RFTCLK) clock. This feature can be
configured through CPTS_RFTCLK_SEL register (offset: x08) in CPTS module
and can be
Add set of fixed, external input clocks definitions for TIMI0, TIMI1,
TSREFCLK clocks. Such clocks can be used as reference clocks for some HW
modules (as cpts, for example) by configuring corresponding clock muxes.
For these clocks real frequencies have to be defined in board files.
Signed-off-by
KeyStone 66AK2H/K 1G Ethernet Switch Subsystems, can control an external
multiplexer that selects one of up to 32 clocks for time sync reference
(RFTCLK) clock. This feature can be configured through CPTS_RFTCLK_SEL
register (offset: x08) in CPTS module and modelled as multiplexer clock.
Hence, ad
Add set of fixed, external input clocks definitions for TSIPCLKA, TSIPCLKB
clocks. Such clocks can be used as reference clocks for some HW modules (as
cpts, for example) by configuring corresponding clock muxes. For these
clocks real frequencies have to be defined in board files.
Signed-off-by: Gr
KeyStone 66AK2E 1G Ethernet Switch Subsystems, can control an external
multiplexer that selects one of up to 32 clocks for time sync reference
(RFTCLK) clock. This feature can be configured through CPTS_RFTCLK_SEL
register (offset: x08) in CPTS module and modelled as multiplexer clock.
Hence, add
On 06/06/2019 16:18, Dmitry Osipenko wrote:
...
>>> If I understood everything correctly, the FIFO buffer is shared among
>>> all of the ADMA clients and hence it should be up to the ADMA driver to
>>> manage the quotas of the clients. So if there is only one client that
>>> uses ADMA at a time
KeyStone 66AK2L 1G Ethernet Switch Subsystems, can control an external
multiplexer that selects one of up to 32 clocks for time sync reference
(RFTCLK) clock. This feature can be configured through CPTS_RFTCLK_SEL
register (offset: x08) in CPTS module and modelled as multiplexer clock.
Hence, add
Enable CPTS support which is present in Network Coprocessor Gigabit
Ethernet (GbE) Switch Subsystem.
Signed-off-by: Grygorii Strashko
Acked-by: Richard Cochran
---
arch/arm/configs/keystone_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/keystone_defconfig
b/arch
From: Paul E. McKenney
> Sent: 06 June 2019 10:44
...
> But m68k is !SMP-only, correct? If so, the only issues would be
> interactions with interrupt handlers and the like, and doesn't current
> m68k hardware use exact interrupts? Or is it still possible to interrupt
> an m68k in the middle of an
26.05.2019 7:37, Vidya Sagar пишет:
> Add support for Synopsys DesignWare core IP based PCIe host controller
> present in Tegra194 SoC.
>
> Signed-off-by: Vidya Sagar
> ---
> Changes since [v7]:
> * Addressed review comments from Thierry
>
> Changes since [v6]:
> * Removed code around "nvidia,di
On Mon, May 27, 2019 at 02:59:07PM +, Michael Kelley wrote:
This patch series moves Hyper-V clock/timer code to a separate Hyper-V
clocksource driver. Previously, Hyper-V clock/timer code and data
structures were mixed in with other Hyper-V code in the ISA independent
drivers/hv code as well
On Thu, May 23, 2019 at 7:45 PM Marcos Paulo de Souza
wrote:
>
> Commit c42d3240990814eec1e4b2b93fa0487fc4873aed
> ("md: return -ENODEV if rdev has no mddev assigned") changed rdev_attr_store
> to
> return -ENODEV when rdev->mddev is NULL, now do the same to rdev_attr_show.
nit: checkpatch.pl co
Hi Wolfram,
I think I2C ecosystem is also part interested in I3C due the
compatibility and maybe they can provide some feedback.
If you think differently, sorry I will remove I2C list next time.
Regards,
Vitor Soares
From: Wolfram Sang
Date: Thu, Jun 06, 2019 at 17:25:23
> On Thu, Jun 06, 201
06.06.2019 19:32, Jon Hunter пишет:
>
> On 06/06/2019 16:18, Dmitry Osipenko wrote:
>
> ...
>
If I understood everything correctly, the FIFO buffer is shared among
all of the ADMA clients and hence it should be up to the ADMA driver to
manage the quotas of the clients. So if there
On Thu, May 30, 2019 at 12:14:00AM +, Michael Kelley wrote:
Break out parts of mshyperv.h that are ISA independent into a
separate file in include/asm-generic. This move facilitates
ARM64 code reusing these definitions and avoids code
duplication. No functionality or behavior is changed.
Sig
Need feedback to the following patches which adds support for a DART-6UL Board
Product Page: https://www.variscite.com/product/evaluation-kits/dart-6ul-kits
Oliver Graute (2):
ARM: dts: imx6ul: Add Variscite DART-6UL SoM support
ARM: dts: Add support for i.MX6 UltraLite DART Variscite Customb
On Tue, Jun 4, 2019 at 3:47 PM Gustavo A. R. Silva
wrote:
>
> One of the more common cases of allocation size calculations is finding
> the size of a structure that has a zero-sized array at the end, along
> with memory for some number of elements for that array. For example:
>
> struct foo {
>
This patch adds DeviceTree Bindings for the i.MX6 UltraLite DART NAND/WIFI
Signed-off-by: Oliver Graute
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/imx6ul-var-6ulcustomboard.dts | 209
2 files changed, 210 insertions(+)
create mode 100
This patch adds support for the i.MX6UL variant of the Variscite DART-6UL
SoM Carrier-Board
Signed-off-by: Oliver Graute
---
.../boot/dts/imx6ul-imx6ull-var-dart-common.dtsi | 458 +
1 file changed, 458 insertions(+)
create mode 100644 arch/arm/boot/dts/imx6ul-imx6ull-var-
Checking for 32-bit PAE is quite common around code that fiddles with
the PDPTRs. Add a function to compress all checks into a single
invocation.
Signed-off-by: Paolo Bonzini
---
arch/x86/kvm/vmx/nested.c | 3 +--
arch/x86/kvm/vmx/vmx.c| 4 ++--
arch/x86/kvm/x86.c| 8
arch/
On Thu, Jun 06, 2019 at 09:00:42AM -0700, Nathan Chancellor wrote:
> On Thu, Jun 06, 2019 at 02:53:23PM +0200, Pavel Machek wrote:
> > Hi!
> >
> > > [ Upstream commit faf5a744f4f8d76e7c03912b5cd381ac8045f6ec ]
> > >
> > > clang -Wuninitialized incorrectly sees a variable being used without
> > >
On 06/06/2019 17:44, Dmitry Osipenko wrote:
> 06.06.2019 19:32, Jon Hunter пишет:
>>
>> On 06/06/2019 16:18, Dmitry Osipenko wrote:
>>
>> ...
>>
> If I understood everything correctly, the FIFO buffer is shared among
> all of the ADMA clients and hence it should be up to the ADMA driver t
Neil Armstrong writes:
> Add missing XBGR & ABGR formats variants from the primary plane.
>
> Fixes: bbbe775ec5b5 ("drm: Add support for Amlogic Meson Graphic Controller")
> Signed-off-by: Neil Armstrong
Reviewed-by: Kevin Hilman
Add PXP node for i.MX6UL/L SoC.
Signed-off-by: Sébastien Szymanski
---
arch/arm/boot/dts/imx6ul.dtsi | 9 +
arch/arm/boot/dts/imx6ull.dtsi | 6 ++
2 files changed, 15 insertions(+)
diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi
index f10012de5eb6..a3c005
On Wed, Jun 05, 2019 at 02:57:59PM -0700, Dan Williams wrote:
> Prepare for hot{plug,remove} of sub-ranges of a section by tracking a
> sub-section active bitmask, each bit representing a PMD_SIZE span of the
> architecture's memory hotplug section size.
>
> The implications of a partially populat
On Thu, 2019-06-06 at 11:52 -0400, Jerome Glisse wrote:
> On Thu, Jun 06, 2019 at 12:41:29PM -0300, Jason Gunthorpe wrote:
> > On Thu, Jun 06, 2019 at 10:27:43AM -0400, Jerome Glisse wrote:
> > > On Thu, Jun 06, 2019 at 11:16:44AM -0300, Jason Gunthorpe wrote:
> > > > On Mon, May 06, 2019 at 04:29:
On 6/6/19 11:51 AM, Song Liu wrote:
>
> Applied to my md-next tree.
>
Great. :)
Thanks, Song.
--
Gustavo
Hi Boris,
From: Boris Brezillon
Date: Thu, Jun 06, 2019 at 16:17:55
> On Thu, 6 Jun 2019 17:12:03 +0200
> Vitor Soares wrote:
>
> > This helper return the i3c_device_id structure in order the client
> > have access to the driver data.
> >
> > Signed-off-by: Vitor Soares
> > ---
> > Changes
> For today the st_lsm6dsx driver support LSM6DSO and LSM6DSR sensor only in
> spi and i2c mode.
>
> The LSM6DSO and LSM6DSR are also i3c capable so lets give i3c support to
> them.
>
> Signed-off-by: Vitor Soares
> ---
Hi Vitor,
just a nit inline, but you can add my acked-by for st_lsm6dsx pa
On Wed, Jun 05, 2019 at 02:58:21PM -0700, Dan Williams wrote:
> Allow sub-section sized ranges to be added to the memmap.
> populate_section_memmap() takes an explict pfn range rather than
> assuming a full section, and those parameters are plumbed all the way
> through to vmmemap_populate(). There
On Thu, Jun 06, 2019 at 03:54:24PM +, Jorgen Hansen wrote:
>
>
> > On 6 Jun 2019, at 11:34, Peter Zijlstra wrote:
> >
> >
> > The VMCI driver is abusing atomic64_t and atomic_t, there is no actual
> > atomic RmW operations around.
> >
> > Rewrite the code to use a regular u64 with READ_ON
Quoting Nicolas Saenz Julienne (2019-06-06 07:22:58)
> diff --git a/drivers/clk/bcm/clk-raspberrypi.c
> b/drivers/clk/bcm/clk-raspberrypi.c
> index b1365cf19f3a..052296b5fbe4 100644
> --- a/drivers/clk/bcm/clk-raspberrypi.c
> +++ b/drivers/clk/bcm/clk-raspberrypi.c
> @@ -63,6 +63,8 @@ struct raspb
On Thu, Jun 06, 2019 at 10:36:02AM -0500, Pierre-Louis Bossart wrote:
> On 6/6/19 9:58 AM, Srinivas Kandagatla wrote:
> >
> >
> > On 06/06/2019 15:28, Pierre-Louis Bossart wrote:
> > > On 6/6/19 6:22 AM, Srinivas Kandagatla wrote:
> > > > multi bank switching code takes lock on condition but rele
On 6/5/2019 10:24 PM, Nathan Chancellor wrote:
When building powerpc pseries_defconfig or powernv_defconfig:
drivers/scsi/lpfc/lpfc_nvmet.c:224:1: error: unused function
'lpfc_nvmet_get_ctx_for_xri' [-Werror,-Wunused-function]
drivers/scsi/lpfc/lpfc_nvmet.c:246:1: error: unused function
'lpfc
From: Frieder Schrempf
The 1Gb Macronix chip can have a maximum of 20 bad blocks, while
the 2Gb version has twice as many blocks and therefore the maximum
number of bad blocks is 40.
The 4Gb GigaDevice GD5F4GQ4xA has twice as many blocks as its 2Gb
counterpart and therefore a maximum of 80 bad b
Quoting Nicolas Saenz Julienne (2019-06-06 07:22:56)
> diff --git a/drivers/cpufreq/raspberrypi-cpufreq.c
> b/drivers/cpufreq/raspberrypi-cpufreq.c
> new file mode 100644
> index ..99b59d5a50aa
> --- /dev/null
> +++ b/drivers/cpufreq/raspberrypi-cpufreq.c
[...]
> +
> +/*
> + * Since th
On Wed, Jun 05, 2019 at 10:52:12PM -0700, John Hubbard wrote:
> On 6/5/19 6:45 PM, ira.we...@intel.com wrote:
> > From: Ira Weiny
> >
> > ... V1,000,000 ;-)
> >
> > Pre-requisites:
> > John Hubbard's put_user_pages() patch series.[1]
> > Jan Kara's ext4_break_layouts() fixes[2]
> >
>
On Fri, May 24, 2019 at 03:53:06PM +0100, Dave P Martin wrote:
> On Fri, May 24, 2019 at 02:02:17PM +0100, Mark Rutland wrote:
> > On Fri, May 24, 2019 at 11:25:29AM +0100, Dave Martin wrote:
> > > #endif /* _UAPI__ASM_HWCAP_H */
> > > diff --git a/arch/arm64/include/uapi/asm/mman.h
> > > b/arch/
Am Do., 6. Juni 2019 um 13:20 Uhr schrieb Marcel Holtmann :
>
> Hi Joerg,
>
> >>> In 5.2.0-rcx I see a new error message on startup probably after
> >>> loading the Bluetooth firmware:
> >>> [1.609460] Bluetooth: hci0: unexpected event for opcode 0xfc2f
> >>>
> dmesg | grep Bluetooth
> >>>
From: Boris Brezillon
Date: Thu, Jun 06, 2019 at 15:18:44
> On Thu, 6 Jun 2019 16:00:01 +0200
> Vitor Soares wrote:
>
> > Currently the I3C framework limits SCL frequency to FM speed when
> > dealing with a mixed slow bus, even if all I2C devices are FM+ capable.
> >
> > The core was also not
On Thu, 2019-06-06 at 10:05 -0700, Stephen Boyd wrote:
> Quoting Nicolas Saenz Julienne (2019-06-06 07:22:58)
> > diff --git a/drivers/clk/bcm/clk-raspberrypi.c b/drivers/clk/bcm/clk-
> > raspberrypi.c
> > index b1365cf19f3a..052296b5fbe4 100644
> > --- a/drivers/clk/bcm/clk-raspberrypi.c
> > +++ b
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