On Tue, May 28, 2019 at 05:16:24PM +0200, Daniel Bristot de Oliveira wrote:
> #if defined(CONFIG_PREEMPT) && (defined(CONFIG_DEBUG_PREEMPT) || \
> defined(CONFIG_TRACE_PREEMPT_TOGGLE))
> +
> +DEFINE_PER_CPU(int, __traced_preempt_count) = 0;
> /*
> * If the value pa
The function should return NULL in case no device is found, but it
always returns the last checked mc device from the list even if the
index did not match. This patch fixes this.
I did some analysis why this did not raise any issues for about 3
years and the reason is that edac_mc_find() is mostly
Make code more readable by introducing a mci_for_each_dimm() iterator.
Now, we just get a pointer to a struct dimm_info. Direct array access
using an index is no longer needed to iterate.
Signed-off-by: Robert Richter
---
drivers/edac/edac_mc.c | 18 ++
drivers/edac/edac_mc
Remove needless and boilerplate variable declarations. No functional
changes.
Signed-off-by: Robert Richter
---
drivers/edac/edac_mc.c | 21 +
1 file changed, 9 insertions(+), 12 deletions(-)
diff --git a/drivers/edac/edac_mc.c b/drivers/edac/edac_mc.c
index a6b34ccce3d4..a8
Current arm64 systems that use the ghes driver lack kernel support for
a proper memory error reporting. Following issues are seen:
* Error record shows insufficient data, such as "EDAC MC0: 1 CE
unknown error on unknown label",
* DMI DIMM labels are not decoded for error reporting,
* No me
Looking at how mci->{ue,ce}_per_layer[EDAC_MAX_LAYERS] is used, it
turns out that only the leaves in the memory hierarchy are consumed
(in sysfs), but not the intermediate layers, e.g.:
count = dimm->mci->ce_per_layer[dimm->mci->n_layers-1][dimm->idx];
So let's get rid of the unused counters tha
Use standard macros for page calculations.
Signed-off-by: Robert Richter
---
drivers/edac/ghes_edac.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/edac/ghes_edac.c b/drivers/edac/ghes_edac.c
index 4a13c394fa66..39702bac5eaf 100644
--- a/drivers/edac/ghes_edac.c
In a later patch we want to have one mc device per node. This patch
extracts the numa node information for each dimm. This is done by
collecting the physical address ranges from the DMI table (Memory
Array Mapped Address - Type 19 of SMBIOS spec). The node information
for a physical address is alre
Systems using ACPI GHES for error detection do not have exact
knowledge of the memory hierarchy. Compared to other memory controller
drivers the total size of each layer is unknown (card/module,
channel/slot, etc.). But there is the total number of dimms. So add a
function to allocate an mc device
According to SMBIOS Spec. 2.7 (N.2.5 Memory Error Section), a failing
DIMM (module or rank number) can be identified by its error location
consisting of node, card and module. A module handle is used to map it
to the dimms listed in the dmi table. Collect all those data from the
error record and se
In a later patch we want add more information about the memory
hierarchy (NUMA topology, DIMM label information). Rework memory
hierarchy detection to make the code extendable for this.
The general approach is roughly like:
mem_info_setup();
for_each_node(nid) {
mc
Typically for most systems, there is one edac memory controller device
per node. This patch implements the same for the ghes driver. Now,
create multiple mc devices and map the dimms based on the node id.
We need at least one node that is used as fallback if no node
information is available in the
Update on CPER DIMM naming convention and DIMM ranks.
Signed-off-by: Robert Richter
---
Documentation/admin-guide/ras.rst | 31 +++
1 file changed, 19 insertions(+), 12 deletions(-)
diff --git a/Documentation/admin-guide/ras.rst
b/Documentation/admin-guide/ras.rst
i
The ghes driver is not able yet to count legacy API counters in sysfs,
e.g.:
/sys/devices/system/edac/mc/mc0/csrow2/ce_count
/sys/devices/system/edac/mc/mc0/csrow2/ch0_ce_count
/sys/devices/system/edac/mc/mc0/csrow2/ch1_ce_count
Make counting csrows/channels generic so that the ghes driver can
This patch enables per-layer reporting of the GHES driver based on
node, card and module. A dimm can be uniquely identified by those 3
identifiers. The mc device is selected by the node id. Thus, each ghes
edac memory controller device has a 2-dimensional layer hierarchy
based on card and module in
Get rid of this macro and instead use the new function
edac_get_dimm(). Also introduce the edac_get_dimm_by_index() function
for later use.
Semantic patch used:
@@ expression mci, a, b,c; @@
-EDAC_DIMM_PTR(mci->layers, mci->dimms, mci->n_layers, a, b, c)
+edac_get_dimm(mci, a, b, c)
Signed-off-
This is in preparation of the next patch to make the changes there
more visible.
Signed-off-by: Robert Richter
---
drivers/edac/ghes_edac.c | 97 ++--
1 file changed, 53 insertions(+), 44 deletions(-)
diff --git a/drivers/edac/ghes_edac.c b/drivers/edac/ghes_
This patch extracts the DIMM label from the DMI table and puts this
information into sysfs. E.g. on a ThunderX2 system we found this now:
# grep . /sys/devices/system/edac/mc/mc*/dimm*/dimm_label
/sys/devices/system/edac/mc/mc0/dimm0/dimm_label:N0 DIMM_A0
/sys/devices/system/edac/mc/mc0/dimm1/d
We do not need to calculate the offset in the mc's dimm array, let's
just store the index in struct dimm_info and we can get rid of this
macro.
Signed-off-by: Robert Richter
---
drivers/edac/edac_mc.c | 13
drivers/edac/edac_mc_sysfs.c | 20 --
include/linux/ed
Rework edac_raw_mc_handle_error() to use struct dimm_info.
Signed-off-by: Robert Richter
---
drivers/edac/edac_mc.c | 28 +---
drivers/edac/edac_mc.h | 2 ++
drivers/edac/ghes_edac.c | 6 +-
3 files changed, 20 insertions(+), 16 deletions(-)
diff --git a/driver
Almost duplicate code, remove it.
Note: there is a difference in the calculation of the grain_bits,
using the edac_mc's version here.
Signed-off-by: Robert Richter
---
drivers/edac/edac_mc.c | 22 +++---
drivers/edac/ghes_edac.c | 9 -
2 files changed, 11 insertions(+
The detail_location[] string in struct ghes_edac_pvt is complete
useless and data is just copied around. Put everything into
e->other_detail from the beginning.
Signed-off-by: Robert Richter
---
drivers/edac/ghes_edac.c | 17 +
1 file changed, 9 insertions(+), 8 deletions(-)
dif
Always use put_device() after device_add() failed.
Signed-off-by: Robert Richter
---
drivers/edac/edac_mc_sysfs.c | 36 +++-
1 file changed, 19 insertions(+), 17 deletions(-)
diff --git a/drivers/edac/edac_mc_sysfs.c b/drivers/edac/edac_mc_sysfs.c
index 464174685
In drivers/isdn/hisax/isac.c, the function isac_interrupt() and
ISAC_l1hw() may be concurrently executed.
ISAC_l1hw()
line 499: if (!cs->tx_skb)
isac_interrupt()
line 250: dev_kfree_skb_irq(cs->tx_skb);
Thus, a possible concurrency use-after-free bug may occur in ISAC_l1hw().
To fix the
Commit 0a1eb2d474ed ("fs/proc: Stop reporting eip and esp in
/proc/PID/stat") stopped reporting eip/esp and commit fd7d56270b52
("fs/proc: Report eip/esp in /prod/PID/stat for coredumping")
reintroduced the feature to fix a regression with userspace core dump
handlers (such as minicoredumper).
Bec
On Tue, May 28, 2019 at 7:19 PM Peter Zijlstra wrote:
>
> On Tue, May 28, 2019 at 06:32:57PM +0200, Marco Elver wrote:
> > This is a pre-requisite for enabling bitops instrumentation. Some bitops
> > may safely be used with instrumentation in uaccess regions.
> >
> > For example, on x86, `test_bit
Hi João,
On 5/28/19 11:22 PM, João Paulo Rechi Vita wrote:
On Mon, May 20, 2019 at 11:28 PM Hans de Goede wrote:
Commit 78f3ac76d9e5 ("platform/x86: asus-wmi: Tell the EC the OS will
handle the display off hotkey") causes the backlight to be permanently off
on various EeePC laptop models usin
On 5/6/19 9:05 AM, Wen Yang wrote:
> The call to of_get_child_by_name returns a node pointer with refcount
> incremented thus it must be explicitly decremented after the last
> usage.
>
> Detected by coccinelle with the following warnings:
> drivers/media/platform/xilinx/xilinx-vipp.c:487:3-9: ERR
On Tue, May 28, 2019 at 09:22:14PM +0200, Jiri Kosina wrote:
> On Tue, 28 May 2019, Jiri Kosina wrote:
>
> > [ some x86/PM folks added ]
> >
> > I isolated this to 'nosmt' being present in the "outer" (resuming) kernel,
> > and am still not sure whether this is x86 issue or nvme/PCI/blk-mq issue
From: Ong Boon Leong
With xPCS functions now ready, we add them into the main driver and
ethtool logics. To differentiate from EQoS MAC PCS and DWC Ethernet
xPCS, we introduce 'has_xpcs' in platform data as a mean to indicate
whether GBE controller includes xPCS or not.
To support platform-speci
From: Ong Boon Leong
xPCS is DWC Ethernet Physical Coding Sublayer that may be integrated
into a GbE controller that uses DWC EQoS MAC controller. An example of
HW configuration is shown below:-
<-GBE Controller-->|<--External PHY chip-->
+--+ ++
From: Kweh Hock Leong
DWMAC4 is capable to support clause 45 mdio communication.
This patch enable the feature on stmmac_mdio_write() and
stmmac_mdio_read() by following phy_write_mmd() and
phy_read_mmd() mdiobus read write implementation format.
Reviewed-by: Li, Yifan
Signed-off-by: Kweh Hock
This patch-set is to enable Ethernet controller
(DW Ethernet QoS and DW Ethernet PCS) with SGMII interface in Elkhart Lake.
The DW Ethernet PCS is the Physical Coding Sublayer that is between Ethernet
MAC and PHY and uses MDIO Clause-45 as Communication.
Kweh Hock Leong (1):
net: stmmac: enable
From: Ong Boon Leong
We introduce support for driver that has v5.10 IP and is also using
xPCS as MMD. This can be easily enabled for other product that integrates
xPCS that is not using v5.00 IP.
Reviewed-by: Chuah Kim Tatt
Reviewed-by: Voon Weifeng
Reviewed-by: Kweh Hock Leong
Reviewed-by: B
Added EHL SGMII 1Gbps PCI ID. Different MII and speed will have
different PCI ID.
Signed-off-by: Voon Weifeng
---
drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c | 111 +++
1 file changed, 111 insertions(+)
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c
b/dr
On 2019/5/29 14:58, David Miller wrote:
> From: Yunsheng Lin
> Date: Mon, 27 May 2019 09:47:54 +0800
>
>> When user has configured a large number of virtual netdev, such
>> as 4K vlans, the carrier on/off operation of the real netdev
>> will also cause it's virtual netdev's link state to be proce
On Tue, May 28, 2019 at 11:31:45PM +0200, Jiri Kosina wrote:
> diff --git a/arch/x86/power/cpu.c b/arch/x86/power/cpu.c
> index a7d966964c6f..bde8ce1f6c6c 100644
> --- a/arch/x86/power/cpu.c
> +++ b/arch/x86/power/cpu.c
> @@ -299,9 +299,20 @@ int hibernate_resume_nonboot_cpu_disable(void)
>
On Wed, May 29, 2019 at 02:37:06PM +0900, Chanwoo Choi wrote:
> Hi,
>
> On 19. 5. 29. 오전 1:50, Charles Keepax wrote:
> > Ensure the case when regmap_update_bits_check fails and the change
> > variable is not updated is handled correctly.
> >
> > Signed-off-by: Charles Keepax
> > ---
> > regm
From: Robin Gong
More channel interrupts, one more clock, and only one
dmamux on i.mx7ulp-edma.
Signed-off-by: Robin Gong
---
Documentation/devicetree/bindings/dma/fsl-edma.txt | 44 +++---
1 file changed, 39 insertions(+), 5 deletions(-)
diff --git a/Documentation/devicetree/
From: Robin Gong
Prepare for edmav2 on i.mx7ulp whose dmamux register is 32bit. No function
impacted.
Signed-off-by: Robin Gong
---
drivers/dma/fsl-edma-common.c | 18 ++
1 file changed, 14 insertions(+), 4 deletions(-)
diff --git a/drivers/dma/fsl-edma-common.c b/drivers/dma/
From: Robin Gong
Add edma2 for i.mx7ulp by version v3, since v2 has already
been used by mcf-edma.
The big changes based on v1 are belows:
1. only one dmamux.
2. another clock dma_clk except dmamux clk.
3. 16 independent interrupts instead of only one interrupt for
all channels.
Signed-off-by:
From: Robin Gong
This patch set add new version of edma for i.mx7ulp, the main changes
are as belows:
1. only one dmamux.
2. another clock dma_clk except dmamux clk.
3. 16 independent interrupts instead of only one interrupt for
all channels.
For the first change, need modify fsl-e
From: Robin Gong
There are some differences between vf610 and next i.mx7ulp. Put such
differences into static driver data for distiguish easily in driver.
Signed-off-by: Robin Gong
---
drivers/dma/fsl-edma-common.h | 10 ++
drivers/dma/fsl-edma.c| 36 +++
From: Robin Gong
Update to 'dmamux_nr' instead of static macro DMAMUX_NR since
new version edma only has one dmamux.
Signed-off-by: Robin Gong
---
drivers/dma/fsl-edma-common.c | 2 +-
drivers/dma/mcf-edma.c| 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/dm
From: Robin Gong
Add edma device node in dts.
Signed-off-by: Robin Gong
---
arch/arm/boot/dts/imx7ulp.dtsi | 28
1 file changed, 28 insertions(+)
diff --git a/arch/arm/boot/dts/imx7ulp.dtsi b/arch/arm/boot/dts/imx7ulp.dtsi
index d6b7110..b4f7adf 100644
--- a/arch/
From: Robin Gong
Next version of edma such as edmav2 on i.mx7ulp has only one dmamux.
Add dmamux_nr instead of static macro define 'DMAMUX_NR'. No any
function change here.
Signed-off-by: Robin Gong
---
drivers/dma/fsl-edma-common.h | 1 +
drivers/dma/fsl-edma.c| 11 ++-
2 fil
Здравейте,
съвременното доплащане на храна под формата на ваучери за храна, които могат да
бъдат използвани в най-голямата мрежа от заведения за хранене в страната, е
инструмент, който ефективно повишава ефективността на персонала.
Изборът на нашите ваучери за храна като форма на социална придо
From: Robin Gong
The next v3 i.mx7ulp edma is based on v1, so change version
check logic for v2 instead.
Signed-off-by: Robin Gong
---
drivers/dma/fsl-edma-common.c | 40
1 file changed, 20 insertions(+), 20 deletions(-)
diff --git a/drivers/dma/fsl-ed
On Mon, May 20, 2019 at 4:21 PM Stephen Boyd wrote:
> > + vibrator@fd8c3450 {
> > + compatible = "qcom,msm8974-vibrator";
> > + reg = <0xfd8c3450 0x400>;
>
> This is inside the multimedia clk controller. The resource reservation
> mechanism should be complaining
In drivers/isdn/hisax/hfc_2bds0.c, the function hfc2bds0_interrupt() and
HFCD_l1hw() may be concurrently executed.
HFCD_l1hw()
line 969: if (!cs->tx_skb)
hfc2bds0_interrupt()
line 875: dev_kfree_skb_irq(cs->tx_skb);
Thus, a possible concurrency use-after-free bug may occur in HFCD_l1hw()
The arm64 page table dump code can race with concurrent modification of the
kernel page tables. When a leaf entries are modified concurrently, the dump
code may log stale or inconsistent information for a VA range, but this is
otherwise not harmful.
When intermediate levels of table are freed, the
This series enables memory hot remove on arm64 after fixing a memblock
removal ordering problem in generic __remove_memory() and one possible
arm64 platform specific kernel page table race condition. This series
is based on latest v5.2-rc2 tag.
Testing:
Memory hot remove has been tested on arm64
Memory hot remove uses get_nid_for_pfn() while tearing down linked sysfs
entries between memory block and node. It first checks pfn validity with
pfn_valid_within() before fetching nid. With CONFIG_HOLES_IN_ZONE config
(arm64 has this enabled) pfn_valid_within() calls pfn_valid().
pfn_valid() is a
The arch code for hot-remove must tear down portions of the linear map and
vmemmap corresponding to memory being removed. In both cases the page
tables mapping these regions must be freed, and when sparse vmemmap is in
use the memory backing the vmemmap must also be freed.
This patch adds a new re
On Tue, May 28, 2019 at 07:32:28PM +0200, Peter Zijlstra wrote:
> On Tue, May 28, 2019 at 04:32:24PM +0100, Will Deacon wrote:
> > On Tue, May 28, 2019 at 04:01:03PM +0200, Peter Zijlstra wrote:
> > > On Tue, May 28, 2019 at 08:31:29PM +0800, Young Xiao wrote:
> > > > When a kthread calls call_user
Hi,
On 5/28/19 8:11 PM, Dave Hansen wrote:
On 5/28/19 10:45 AM, Benjamin Tissoires wrote:
On Tue, May 28, 2019 at 7:15 PM Jiri Kosina wrote:
Just to confirm -- I guess reverting 4ceabaf79 and a025a18fe would work
this around, right?
Yes, reverting that pair on top of 5.2-rc1 works around th
Currently the default clock rates for the HDA and HDA2CODEC_2X clocks
are both 19.2MHz. However, the default rates for these clocks should
actually be 51MHz and 48MHz, respectively. Correct the default clock
rates for these clocks by specifying them in the clock init table for
Tegra210.
Signed-off
Add DT node for SERDES0 and SERDES1.
Signed-off-by: Kishon Vijay Abraham I
---
arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 41
1 file changed, 41 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
index 99d2402
Add mux-controller DT node as a child node of scm_conf. This is
required for muxing SERDES between USB, PCIe and ICSS2 SGMII.
Signed-off-by: Kishon Vijay Abraham I
---
arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-am
GIC_ITS used in AM654 platform has the same configuration as that of
GIC_ITS used in Socionext SoCs. Add "socionext,synquacer-pre-its"
property to get PCI MSI working.
Signed-off-by: Kishon Vijay Abraham I
---
arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 1 +
1 file changed, 1 insertion(+)
diff -
Add PCIe Root Complex DT node.
Signed-off-by: Kishon Vijay Abraham I
---
arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 53
arch/arm64/boot/dts/ti/k3-am65.dtsi | 1 +
2 files changed, 54 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
b/arch/arm64
Patch series adds PCIe and SERDES DT nodes to k3-am65.dtsi and keeps
them disabled in k3-am654-base-board.dts since there are no PCIe
slots in the base board.
PCIe slots are actually present in add on boards. Once overlay support
is merged, I'll add overlay DTS files to enable PCIe.
All the drive
AM654 base board does not have any PCIe slots. Disable all the
SERDES and PCIe instances.
Signed-off-by: Kishon Vijay Abraham I
---
.../arm64/boot/dts/ti/k3-am654-base-board.dts | 24 +++
1 file changed, 24 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dt
Add PCIe Endpoint DT node.
Signed-off-by: Kishon Vijay Abraham I
---
arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 26
1 file changed, 26 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
index 09f18b1e70f2..fb8
On Wed, 29 May 2019, Peter Zijlstra wrote:
> > > I verified that it succesfully makes it to the point where restore_image()
> > > is called from swsusp_arch_resume() (and verified that only BSP is alive
> > > at that time), but the old kernel never comes back and triplefault-like
> > > reboot happ
hi Ulf
On 5/27/19 8:17 PM, Ulf Hansson wrote:
On Fri, 26 Apr 2019 at 09:46, Ludovic Barre wrote:
From: Ludovic Barre
The "busy_detect_flag" is used to read/clear busy value of
mmci status. The "busy_detect_mask" is used to manage busy irq of
mmci mask.
For sdmmc variant, the 2 properties ha
On Wed, 29 May 2019 15:47:40 +0900
Masami Hiramatsu wrote:
> Hi Steve,
>
> I found that these interfaces seem tightly coupled with fgraph_ops. But that
> cause a problem when I'm using it from kretprobe.
I was thinking that the kretprobes could use the fgraph_ops like
kprobes uses ftrace_ops.
Hi,
On 5/22/19 12:50 PM, Heikki Krogerus wrote:
Hi,
I'm not splitting this series in two after all. After thinking about
this for some time, I decided to add support for static software
nodes. I did not want to support them because I don't want to make it
easy to maintain board files, but in en
Changes in v5:
1. run checkpatch.pl to fix coding style issue.
2. apply reverse xmas tree ordering.
3. add output log of "ethtool -t eth0"
1. get hash table size in hw feature reigster, and add support
for taller hash table(128/256) in dwmac4.
2. only clear GMAC_PACKET_FILTER bits used in this function,
to avoid side effect to functions of other bits.
stmmac selftests output log:
ethtool -t eth0
The test result is FAI
On Tue, May 28, 2019 at 05:16:22PM +0200, Daniel Bristot de Oliveira wrote:
> prempt_disable/enable tracepoints occurs only in the preemption
> enabled <-> disable transition. As preempt_latency_stop() and
> preempt_latency_start() already do this control, avoid code
> duplication by using these fu
To set frequency on specific cpus using cpupower, following syntax can
be used :
cpupower -c #i frequency-set -f #f -r
While setting frequency using cpupower frequency-set command, if we use
'-r' option, it is expected to set frequency for all cpus related to
cpu #i. But it is observed to be missi
Hi,
On 5/22/19 12:51 PM, Heikki Krogerus wrote:
Software nodes provide two features that we will need later.
1) Software nodes can have references to other software nodes.
2) Software nodes can exist before a device entry is created.
Signed-off-by: Heikki Krogerus
---
drivers/platform/x86/in
Hi,
Why am I not seeing references to coresight-cpu-debug in here? In
other places in this patchset CPU debug has been changed, but there
appears to be no platform agnostic name here, nor any ACPI type name
either. Is cpu-debug remaining device tree only? Should CPU debug not
be treated like ETM a
> Hi Walter,
>
> Please describe your use case.
> For testing context the generic KASAN works better and it does have
> quarantine already. For prod/canary environment the quarantine may be
> unacceptable in most cases.
> I think we also want to use tag-based KASAN as a base for ARM MTE
> support
Hi,
On 5/22/19 12:51 PM, Heikki Krogerus wrote:
Supplying also external devices, the DisplayPort connector
and the USB role switch, software fwnodes. After this the
driver has access to all the components tied to the USB
Type-C connector and can start creating software node
references to actuall
On 29/05/2019 10:33, Peter Zijlstra wrote:
> On Tue, May 28, 2019 at 05:16:23PM +0200, Daniel Bristot de Oliveira wrote:
>> The preempt_disable/enable tracepoint only traces in the disable <-> enable
>> case, which is correct. But think about this case:
>>
>> %< ---
They are not used any more since
commit 7558562a70fb ("clk: ti: Drop legacy clk-3xxx-legacy code")
Reported-by: Hulk Robot
Suggested-by: Tero Kristo
Signed-off-by: YueHaibing
---
v3: remove ti_clk_build_component_div and _get_div_table_from_setup
v2: also remove mux/div unused functions
---
dr
The "oneshot" tracer records every address (ip, parent_ip) exactly once.
As a result, "oneshot" can be used to efficiently create kernel function
coverage/usage reports such as in undertaker-tailor[0].
In order to provide this functionality, "oneshot" uses a
configurable hashset for blacklisting a
On 5/9/19 11:09 AM, eugen.hris...@microchip.com wrote:
> From: Eugen Hristev
>
> This splits the Atmel ISC driver into a common base: atmel-isc-base.c
> and the driver probe/dt part , atmel-isc.c
> This is needed to keep a common ground for the sensor controller which will
> be reused.
> The atme
On Tue 28 May 2019 at 17:35, Karsten Merker wrote:
> On Tue, May 28, 2019 at 05:10:42PM +0200, Loys Ollivier wrote:
>> On Tue 28 May 2019 at 01:32, Paul Walmsley wrote:
>>
>> > An update for those testing RISC-V patches: here's a new branch of
>> > riscv-pk/bbl that doesn't try to read or modi
On Wed, May 29, 2019 at 11:35 AM Walter Wu wrote:
>
> > Hi Walter,
> >
> > Please describe your use case.
> > For testing context the generic KASAN works better and it does have
> > quarantine already. For prod/canary environment the quarantine may be
> > unacceptable in most cases.
> > I think we
Currently, there is only a 1 ms sleep after asserting PERST.
Reading the datasheets for different endpoints, some require PERST to be
asserted for 10 ms in order for the endpoint to perform a reset, others
require it to be asserted for 50 ms.
Several SoCs using this driver uses PCIe Mini Card, wh
On Tue, May 28, 2019 at 04:03:18PM +0100, Raphael Gault wrote:
> +static int emulate_pmu(struct pt_regs *regs, u32 insn)
> +{
> + u32 sys_reg, rt;
> + u32 pmuserenr;
> +
> + sys_reg = (u32)aarch64_insn_decode_immediate(AARCH64_INSN_IMM_16, insn)
> << 5;
> + rt = aarch64_insn_decode
Ensure the case when regmap_update_bits_check fails and the change
variable is not updated is handled correctly.
Signed-off-by: Charles Keepax
---
Changes since v1:
- Print error message in driver remove
Thanks,
Charles
drivers/extcon/extcon-arizona.c | 33 -
On Tue, May 28, 2019 at 04:03:17PM +0100, Raphael Gault wrote:
> +static int armv8pmu_access_event_idx(struct perf_event *event)
> +{
> + if (!(event->hw.flags & ARMPMU_EL0_RD_CNTR))
> + return 0;
> +
> + /*
> + * We remap the cycle counter index to 32 to
> + * match t
On Tue, May 28, 2019 at 04:02:31PM -0700, Ruslan Babayev wrote:
> Changes:
> v2:
> - more descriptive commit body
> v3:
> - made 'i2c_acpi_find_adapter_by_handle' static inline
> v4:
> - don't initialize i2c_adapter to NULL. Instead see below...
> - handle the case of neithe
On 29/05/2019 10:41, Peter Zijlstra wrote:
> On Tue, May 28, 2019 at 05:16:24PM +0200, Daniel Bristot de Oliveira wrote:
>> #if defined(CONFIG_PREEMPT) && (defined(CONFIG_DEBUG_PREEMPT) || \
>> defined(CONFIG_TRACE_PREEMPT_TOGGLE))
>> +
>> +DEFINE_PER_CPU(int, __traced
On Tue, May 28, 2019 at 04:02:33PM -0700, Ruslan Babayev wrote:
> Lookup I2C adapter using the "i2c-bus" device property on ACPI based
> systems similar to how it's done with DT.
>
> An example DSD describing an SFP on an ACPI based system:
>
> Device (SFP0)
> {
> Name (_HID, "PRP0001")
>
Hello!
On 29.05.2019 11:29, Michal Rostecki wrote:
Function load_sk_storage_btf expects that libbpf__probe_raw_btf is
returning a btf descriptor, but before this change it was returning
an information about whether the probe was successful (0 or 1).
load_sk_storage_btf was using that value as a
--
Hello Good day,
Am Hamza Kabore, a senior staff in the EcoBank International Burkina
Faso, working as Bill & Exchange Manager. I discovered an abandoned
sum of 12.8 million usd in my department and i want the the fund to be
transferred to your account.
We shall share it 50% - 50%. No ri
Hi,
On 5/23/19 2:03 PM, Luís Ferreira wrote:
Hi Hams,
https://github.com/systemd/systemd/pull/12322
https://github.com/hadess/iio-sensor-proxy/pull/262
As all the pull requests to systemd and iio-sensor-proxy has already
been merged, I just need your review on this:
https://github.com/systemd/
On Wed, May 29, 2019 at 10:16:59AM +0200, Jesper Dangaard Brouer wrote:
On Thu, 23 May 2019 21:20:35 +0300
Ivan Khoronzhuk wrote:
+static struct page *cpsw_alloc_page(struct cpsw_common *cpsw)
+{
+ struct page_pool *pool = cpsw->rx_page_pool;
+ struct page *page, *prev_page = NULL;
Hi,
This patch requires all #MC exception errors set MCG_STATUS_RIPV = 1?
Because on offline CPUs, for #MC exception errors set MCG_STATUS_RIPV = 0
(like "Recoverable-not-continuable SRAR Type" Errors), this patch doesn't seem
to work. if this patch's "return; " in a wrong place?
Thanks
To
On Wed, May 29, 2019 at 11:46:10AM +0200, Marco Elver wrote:
> On Wed, 29 May 2019 at 10:55, Dmitry Vyukov wrote:
> >
> > On Tue, May 28, 2019 at 7:19 PM Peter Zijlstra wrote:
> > >
> > > On Tue, May 28, 2019 at 06:32:57PM +0200, Marco Elver wrote:
> > > > This is a pre-requisite for enabling bit
This patchset introduces some misc patches for the driver. Nothing
particularly stands out, maybe apart from a patch to delete a PHY's
timer when necessary.
John Garry (1):
scsi: hisi_sas: Reduce HISI_SAS_SGE_PAGE_CNT in size
Luo Jiaxing (1):
scsi: hisi_sas: Ignore the error code between phy
From: Xiaofei Tan
The argument of dev_err() called by multi_bit_ecc_error_process_v3_hw()
is not right. We pass two arguments, but there is only one printk format
specifier in the string.
Besides, move the print format string to dev_err(). Then compiler can
find such issue in earlier stage.
Sig
From: Luo Jiaxing
Several error code will be generated between PHY down to up.
This issue was introduced by HW design, so the designers come to
a conclusion that we should ignore these several error code.
Signed-off-by: Jiaxing Luo
Signed-off-by: John Garry
---
drivers/scsi/hisi_sas/hisi_sas
Macro HISI_SAS_SGE_PAGE_CNT is defined to SG_CHUNK_SIZE, which is
128.
This means that sizeof(struct hisi_sas_slot_buf_table) is 4192. This is
just over a 4K, which can mean inefficient DMA memory usage (for no PI).
Reduce the size of HISI_SAS_SGE_PAGE_CNT to 124 to fit in a 4K page. With
this ch
From: Xiang Chen
For v3 hw, stash is enabled to promote performance, but it does little
help for promoting performance according to current test. What's more, it
causes exception for some situations, so disable it.
Signed-off-by: Xiang Chen
Signed-off-by: John Garry
---
drivers/scsi/hisi_sas/
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