On Mon, Apr 08, 2019 at 07:44:21AM +, Anson Huang wrote:
> Update i.MX6DL automotive part's opp table according to i.MX6DL
> automotive datasheet Rev.9, 11/2018, it adds 996MHz set-point
> support as below:
>
> LDO enabled(min value):
> 996MHz: VDDARM: 1.275V, VDDSOC: 1.175V;
> 792MHz: VDDARM:
On Wed, Apr 10, 2019 at 04:04:42PM -0700, Atish Patra wrote:
> nosmp command line option sets max_cpus to zero. No secondary harts
> will boot if this is enabled. But present cpu mask will still point to
> all possible masks.
>
> Fix present cpu mask for nosmp usecase.
>
> Signed-off-by: Atish Pa
On 2019-03-28 20:58, Sibi Sankar wrote:
This RFC series aims to add cpu based scaling support to the passive
governor and scale DDR with a generic interconnect bandwidth based
devfreq driver on SDM845 SoC. This series achieves similar
functionality
to Georgi's Patch series (https://patchwork.ke
On Mon, Apr 08, 2019 at 06:53:03PM +, Abel Vesa wrote:
> i.MX8MQ needs it for RTC support.
>
> Signed-off-by: Abel Vesa
Applied, thanks.
This is ping..
Does anyone have any comments?
On 2019/03/25 12:05, Sugaya Taichi wrote:
This series fixes a bug and cleanup code about timer driver for
Milbeaut M10V.
Since it is difficult to separate, it is integrated into a series.
Sugaya Taichi (3):
clocksource/drivers/timer-milbeaut: Fi
> > I think that the problem could be related to how the DMA channel is
> requested.
> > At the moment the function used are:
>
> > pxa2xx_spi_dma_setup --> dma_request_slave_channel_compat -->
> > --> __dma_request_slave_channel_compat --> dma_request_slave_channel -->
> > --> dma_request_chan
>
On 04/10/2019 08:27 PM, Kees Cook wrote:
On Wed, Apr 10, 2019 at 12:33 AM Alexandre Ghiti wrote:
On 04/10/2019 08:59 AM, Christoph Hellwig wrote:
On Thu, Apr 04, 2019 at 01:51:25AM -0400, Alexandre Ghiti wrote:
- fix the case where stack randomization should not be taken into
account.
Hm
On Wed, Apr 10, 2019 at 10:25:16PM -0400, Waiman Long wrote:
> On 04/10/2019 02:44 PM, Peter Zijlstra wrote:
> > However there is another site that fiddles with the HANDOFF bit, namely
> > __rwsem_down_write_failed_common(), and that does:
> >
> > + atomic_long_or(RWS
On 09/04/2019 19:23, Guenter Roeck wrote:
> Introduce local variable 'struct device *dev' and use it instead of
> dereferencing it repeatedly.
>
> The conversion was done automatically with coccinelle using the
> following semantic patches. The semantic patches and the scripts
> used to generate t
On Wed, Apr 10, 2019 at 02:49:09PM -0500, Madhumthia Prabakaran wrote:
> On Wed, Apr 10, 2019 at 09:49:54AM +0300, Dan Carpenter wrote:
> > On Tue, Apr 09, 2019 at 11:16:17AM -0500, Madhumitha Prabakaran wrote:
> > > diff --git a/drivers/staging/rtl8723bs/include/drv_types.h
> > > b/drivers/stagin
On Mon, Apr 01, 2019 at 02:51:11AM +, Anson Huang wrote:
> Add #cooling-cells for i.MX6SLL cpu-freq cooling device usage.
>
> Signed-off-by: Anson Huang
Applied, thanks.
On Wed, Apr 10, 2019 at 02:42:22PM -0400, Waiman Long wrote:
> With the commit 59aabfc7e959 ("locking/rwsem: Reduce spinlock contention
> in wakeup after up_read()/up_write()"), the rwsem_wake() forgoes doing
> a wakeup if the wait_lock cannot be directly acquired and an optimistic
> spinning locke
On Wed, 10 Apr 2019 21:07:56 +0200
Arnd Bergmann wrote:
> On Wed, Apr 10, 2019 at 6:14 PM Steven Rostedt wrote:
> > On Wed, 10 Apr 2019 18:03:57 +0200 Martin Schwidefsky
> > wrote:
> >
> > > > --- a/arch/s390/include/asm/ftrace.h
> > > > +++ b/arch/s390/include/asm/ftrace.h
> > > > @@ -13,7
On Tue, Apr 09, 2019 at 04:59:55AM +, Anson Huang wrote:
> The System Controller Firmware (SCFW) controls RTC, thermal
> and WDOG etc., these resources' interrupt function are managed
> by SCU. When any IRQ pending, SCU will notify Linux via MU general
> interrupt channel #3, and Linux kernel n
On Tue, Apr 09, 2019 at 04:59:49AM +, Anson Huang wrote:
> Add scu general interrupt function support.
>
> Signed-off-by: Anson Huang
> Reviewed-by: Rob Herring
> Reviewed-by: Dong Aisheng
Applied, thanks.
On Tue, Apr 09, 2019 at 05:00:01AM +, Anson Huang wrote:
> On i.MX8QXP, SCU uses MU1 general interrupt channel #3 to notify
> user for IRQs of RTC alarm, thermal alarm and WDOG etc., mailbox
> RX doorbell mode is used for this function, this patch adds
> support for it.
>
> Signed-off-by: Anso
Hi Sylwester,
As per my knowledge HK soc introduce this table to support
overclocking of cpufreq for Odroid XU3 XU4 family for boards.
ARM Cortex-A15 Quad CPU (Eagle) 1800 to 2000
ARM Cortex-A7 Quard CPU (Kingfisher) 1400 to 1500
For Exynos5422 below table
asv-table-[0-3] AVS range from 200 to
On Wed, 10 Apr 2019 20:57:21 +0200
Arnd Bergmann wrote:
> On Wed, Apr 10, 2019 at 5:59 PM Martin Schwidefsky
> wrote:
> > On Tue, 9 Apr 2019 11:54:30 +0200 Harald Freudenberger
> > wrote:
> > > On 08.04.19 23:26, Arnd Bergmann wrote:
> > > > }
> > > Thanks Arnd, but as Nathan
hi,
在 2019/4/4 上午11:03, Daniel Lezcano 写道:
On 01/04/2019 08:43, Elaine Zhang wrote:
Based on the TSADC Tshut mode to select pinctrl,
instead of setting pinctrl based on architecture
(Not depends on pinctrl setting by "init" or "default").
And it requires setting the tshut polarity before select
On Wed, Apr 10, 2019 at 10:28:37AM -0300, Arnaldo Carvalho de Melo wrote:
> > > You forgot to convert that one, doing it for you,
> >
> > Also in perf_event__sample_event_size() we need to do the same thing,
> > right?
>
> and perf_event__synthesize_sample()
>
> Done, resulting patch is at the e
On Thu, Apr 11, 2019 at 01:49:39AM +0800, Frank Lee wrote:
> On Wed, Apr 10, 2019 at 10:57 PM Maxime Ripard
> wrote:
> >
> > On Tue, Apr 09, 2019 at 01:25:58PM -0400, Yangtao Li wrote:
> > > Allwinner Process Voltage Scaling Tables defines the voltage and
> > > frequency value based on the speedb
On 32-bits platform with more than 32 registers, the 64 bits mask is
truncate to the lower 32 bits and the return value of hweight_long will
always smaller than 32. When kernel outputs more than 32 registers, but
the user perf program only counts 32, there will be a data mismatch
result to overflow
This patch add support for DWARF register mappings and libdw registers
initialization, which is used by perf callchain analyzing when
--call-graph=dwarf is given.
CC: Peter Zijlstra
CC: Ingo Molnar
CC: Arnaldo Carvalho de Melo
CC: Alexander Shishkin
CC: Jiri Olsa
CC: Namhyung Kim
Signed-off
This patch set add perf DWARF unwinding support for C-SKY.
Including user registers/stack dump API, and libdw support.
CC: Peter Zijlstra
CC: Ingo Molnar
CC: Arnaldo Carvalho de Melo
CC: Alexander Shishkin
CC: Jiri Olsa
CC: Namhyung Kim
CC: Guo Ren
Changes since v3:
- update with patch f
OMAP2 depends on ARCH_MULTI_V6, which makes sure that the kernel is
compiled with -march=armv6. The compiler frontend will pass the
architecture to the assembler. There is no explicit architecture
specification necessary.
Signed-off-by: Stefan Agner
---
Changes since v2:
- New patch
arch/arm/ma
The LLVM Target parser currently does not allow to specify the security
extension as part of -march (see also LLVM Bug 40186 [0]). When trying
to use Clang with LLVM's integrated assembler, this leads to build
errors such as this:
clang-8: error: the clang compiler does not support '-Wa,-march=ar
This patch implements the perf registers sampling and validation API
for csky arch. The valid registers and their register ID are defined in
perf_regs.h. Perf tool can backtrace in userspace with unwind library
and the registers/user stack dump support.
CC: Guo Ren
Signed-off-by: Mao Han
---
a
In every other instance where mrc is used the coprocessor operand
is prefix with p (e.g. p15). Use the p prefix in this case too.
This fixes a build issue when using LLVM's integrated assembler:
arch/arm/mach-mvebu/coherency_ll.S:69:6: error: invalid operand for
instruction
mrc 15, 0, r3, cr0
The label mvebu_boot_wa_start is not necessary and causes a build
issue when building with LLVM's integrated assembler:
AS arch/arm/mach-mvebu/pmsu_ll.o
arch/arm/mach-mvebu/pmsu_ll.S:59:1: error: invalid symbol redefinition
mvebu_boot_wa_start:
^
Drop the label.
Signed-off-by: Stef
at 16:33, Benjamin Tissoires wrote:
On Mon, Jan 21, 2019 at 8:03 AM Kai-Heng Feng
wrote:
There are some new HP laptops with Elantech touchpad don't support
multitouch.
Currently we use ETP_NEW_IC_SMBUS_HOST_NOTIFY() to check if SMBus is
supported, but in addition to firmware version, the b
On Wed 10-04-19 18:16:18, Tobin C. Harding wrote:
> On Wed, Apr 10, 2019 at 10:02:36AM +0200, Vlastimil Babka wrote:
> > On 4/10/19 4:47 AM, Tobin C. Harding wrote:
> > > Recently a 2 year old bug was found in the SLAB allocator that crashes
> > > the kernel. This seems to imply that not that many
On Thu, Apr 11, 2019 at 1:16 AM Kees Cook wrote:
>
> This is a proposed alternative for the memory initialization series,
> which refactoring the existing gcc plugins into a separate Kconfig
> file and collects all the related options together with some more
> language to describe their difference
Hi,
This patch set add perf callchain(FP/DWARF) support for RISC-V.
It comes from the csky version callchain support with some
slight modifications. The patchset base on Linux 5.1-rc4:
15ade5d2e7775667cf191cf2f94327a4889f8b9d
CC: Palmer Dabbelt
CC: Guo Ren
Mao Han (3):
riscv: Add perf callch
This patch add support for DWARF register mappings and libdw registers
initialization, which is used by perf callchain analyzing when
--call-graph=dwarf is given.
Signed-off-by: Mao Han
CC: Palmer Dabbelt
---
tools/arch/riscv/include/uapi/asm/perf_regs.h | 42
tools/perf/Makefile.
This patch implements the perf registers sampling and validation API
for riscv arch. The valid registers and their register ID are defined in
perf_regs.h. Perf tool can backtrace in userspace with unwind library
and the registers/user stack dump support.
Signed-off-by: Mao Han
CC: Palmer Dabbelt
This patch add support for perf callchain sampling on riscv platform.
The return address of leaf function is retrieved from pt_regs as
it is not saved in the outmost frame.
Signed-off-by: Mao Han
CC: Palmer Dabbelt
---
arch/riscv/kernel/Makefile | 3 +-
arch/riscv/kernel/perf_callcha
Hi Daniel,
> -Original Message-
> From: Daniel Lezcano
> Sent: 2019年4月4日 10:35
> To: Andy Tang ; shawn...@kernel.org
> Cc: Leo Li ; robh...@kernel.org; mark.rutl...@arm.com;
> linux-arm-ker...@lists.infradead.org; devicet...@vger.kernel.org;
> linux-kernel@vger.kernel.org; linux...@vger.
On Thu, Apr 11, 2019 at 1:16 AM Kees Cook wrote:
>
> CONFIG_INIT_STACK_ALL turns on stack initialization based on
> -ftrivial-auto-var-init in Clang builds and on
> -fplugin-arg-structleak_plugin-byref-all in GCC builds.
Is CONFIG_INIT_STACK_ALL wired up to GCC plugin in any way?
I could not unde
Hi,
On Wed, Apr 10, 2019 at 01:41:38PM -0400, Yangtao Li wrote:
> For some SoCs, the CPU frequency subset and voltage value of each OPP
> varies based on the silicon variant in use. The sunxi-cpufreq-nvmem
> driver reads the efuse value from the SoC to provide the OPP framework
> with required inf
On Wed, Apr 10, 2019 at 02:42:19PM -0400, Waiman Long wrote:
> The owner field in the rw_semaphore structure is used primarily for
> optimistic spinning. However, identifying the rwsem owner can also be
> helpful in debugging as well as tracing locking related issues when
> analyzing crash dump. Th
On Wed, Apr 10, 2019 at 02:49:09PM -0500, Madhumthia Prabakaran wrote:
> On Wed, Apr 10, 2019 at 09:49:54AM +0300, Dan Carpenter wrote:
> > On Tue, Apr 09, 2019 at 11:16:17AM -0500, Madhumitha Prabakaran wrote:
> > > diff --git a/drivers/staging/rtl8723bs/include/drv_types.h
> > > b/drivers/stagin
On 4/11/19 5:26 AM, Qian Cai wrote:
> "cat /proc/slab_allocators" could hang forever on SMP machines with
> kmemleak or object debugging enabled due to other CPUs running do_drain()
> will keep making kmemleak_object or debug_objects_cache dirty and unable
> to escape the first loop in leaks_show()
On Sun, 2019-03-10 at 17:31 -0700, Sean Wang wrote:
> Hi, Long
>
> List some comments as the below and this week I will find a board to
> test and then improve the driver.
>
> Sean
>
> On Wed, Mar 6, 2019 at 5:45 PM Long Cheng wrote:
> >
> > In DMA engine framework, add 8250 uart dma t
On Wed, Apr 10, 2019 at 08:44:01PM -0400, Steven Rostedt wrote:
> On Wed, 10 Apr 2019 16:29:02 -0400
> Joel Fernandes wrote:
>
> > The srcu structure pointer array is modified at module load time because the
> > array is fixed up by the module loader at load-time with the final locations
> > of t
On Thu, Apr 11, 2019 at 4:21 AM Yurii Pavlovskyi
wrote:
>
> The asus-wmi driver does not clean up the hwmon device on exit or error.
> To reproduce the bug, repeat rmmod, insmod to verify that device number
> /sys/devices/platform/asus-nb-wmi/hwmon/hwmon?? grows every time. Add
> pointer to the de
Unix is still the backbone of the internet. And Irix took it to the desktop in
its time, a bit too far away from the original maybe, and did not continue,
while Unix did, and is now as BSD, in Mac Systems, and on the desktop many
places.
We suggest full available source support, and integratin
clk: add driver for the SiFive FU540 PRCI and PLLs it controls
Add a driver for the SiFive FU540 PRCI IP block, which handles clock and
some device reset control for the SiFive FU540 chip. Also add a driver-
independent library for the Analog Bits Wide-Range PLL (WRPLL), used by
the PRCI driver t
Hi,
On 4/11/19 10:55 AM, Michal Hocko wrote:
Please please have it more rigorous then what happened when SLUB was
forced to become a default
This is the hard part.
Even if you are able to show that SLUB is as fast as SLAB for all the
benchmarks you run, there's bound to be that one workload
Add common library code for the Analog Bits Wide-Range PLL (WRPLL) IP
block, as implemented in TSMC CLN28HPC.
There is no bus interface or register target associated with this PLL.
This library is intended to be used by drivers for IP blocks that
expose registers connected to the PLL configuration
On Mi, 2019-04-10 at 14:35 -0600, Raul E Rangel wrote:
> This change will send a CHANGE event to udev with the DEAD environment
> variable set when the HC dies. I chose this instead of any of the other
> udev events because it's representing a state change in the host
> controller. The only other e
Add driver code for the SiFive FU540 PRCI IP block. This IP block
handles reset and clock control for the SiFive FU540 device and
implements SoC-level clock tree controls and dividers.
Based on code written by Wesley Terpstra :
https://github.com/riscv/riscv-linux/commit/999529edf517ed75b56659d45
Add DT binding documentation for the Linux driver for the SiFive
PRCI clock & reset control IP block, as found on the SiFive
FU540 chip.
This version includes changes requested by Stephen Boyd
and Rob Herring , and
fixes some errors in the initial version.
Signed-off-by: Paul Walmsley
Signed-of
On Wed, 10 Apr 2019, Joel Fernandes (Google) wrote:
> For the purposes of hardening modules by adding sections to
> ro_after_init sections, prepare for addition of new ro_after_init
> entries which we do in future patches. Create a table to which new
> entries could be added later. This makes it l
After applying:
1,2,5,3
Do we want to do something like the below?
There is absolutely no reason anymore we need spread the implementation
over 3 files: rwsem.h rwsem.c rwsem-xadd.c. And I went insane chasing
things around.
Note the below also includes a number of cleanups, there were still
Ls1088a has 2 thermal sensors, core cluster and SoC platform. Core cluster
sensor is used to monitor the temperature of core and SoC platform is for
platform. The current dts only support the first sensor.
This patch adds the second sensor node to dts to enable it.
Signed-off-by: Yuantian Tang
--
On Wed 10-04-19 12:14:55, David Hildenbrand wrote:
> While current node handling is probably terribly broken for memory block
> devices that span several nodes (only possible when added during boot,
> and something like that should be blocked completely), properly put the
> device reference we obta
Add YAML DT binding documentation for the SiFive FU540 SoC. This
SoC is documented at:
https://static.dev.sifive.com/FU540-C000-v1.0.pdf
Passes dt-doc-validate, as of yaml-bindings commit 4c79d42e9216.
Signed-off-by: Paul Walmsley
Signed-off-by: Paul Walmsley
Cc: Rob Herring
Cc: Mark Rut
Add support for building flattened DT files from DT source files under
arch/riscv/boot/dts. Follow existing kernel precedent from other SoC
architectures. Start our board support by adding initial support for
the SiFive FU540 SoC and the first development board that uses it, the
SiFive HiFive Unl
On Thu, 11 Apr 2019 05:16:56 +0200,
Pierre-Louis Bossart wrote:
>
> SoundWire support will be provided in Linux with the Sound Open
> Firmware (SOF) on Intel platforms. Before we start adding the missing
> pieces, there are a number of warnings and style issues reported by
> checkpatch, cppcheck a
case ESAI_HCKT_EXTAL and case ESAI_HCKR_EXTAL should be
independent of each other, so replace fall-through with break.
Fixes: 43d24e76b698 ("ASoC: fsl_esai: Add ESAI CPU DAI driver")
Signed-off-by: Shengjiu Wang
Acked-by: Nicolin Chen
Cc:
---
Changes in v5
- remove new line after Fixes
Changes
On 04/11/19 at 08:16am, Junichi Nomura wrote:
> On 4/11/19 5:09 PM, Borislav Petkov wrote:
> > On Wed, Apr 10, 2019 at 11:34:51PM +, Junichi Nomura wrote:
> >> But efi_get_rsdp_addr() needs to check whether the kernel was
> >> kexec booted to avoid accessing invalid EFI table address.
> >> efi_
Enable CONFIG_ARCH_SIFIVE in the RISC-V defconfig so
DTB files for SiFive boards are generated by default.
Signed-off-by: Paul Walmsley
Signed-off-by: Paul Walmsley
Cc: Palmer Dabbelt
Cc: Albert Ou
Cc: linux-ri...@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
---
arch/riscv/configs/def
Similar to ARM64, add support for building DTB files from DT source
data for RISC-V boards.
This patch starts with the infrastructure needed for SiFive boards.
Boards from other vendors would add support here in a similar form.
Signed-off-by: Paul Walmsley
Signed-off-by: Paul Walmsley
Cc: Palme
Add initial support for the SiFive FU540-C000 SoC. This is a 28nm SoC
based around the SiFive U54-MC core complex and a TileLink
interconnect.
This file is expected to grow as more device drivers are added to the
kernel.
Signed-off-by: Paul Walmsley
Signed-off-by: Paul Walmsley
Cc: Rob Herring
At Rob's request, we're starting to migrate our DT binding
documentation to json-schema YAML format. Start by converting our cpu
binding documentation. While doing so, document more properties and
nodes. This includes adding binding documentation support for the E51
and U54 CPU cores ("harts") t
Add initial board data for the SiFive HiFive Unleashed A00.
Currently the data populated in this DT file describes the board
DRAM configuration and the external clock sources that supply the
PRCI.
This second version adds onboard SPI device data, fixes the board's
memory size, and adds changes ba
On Thu, 11 Apr 2019 05:16:57 +0200,
Pierre-Louis Bossart wrote:
>
> the number of elements and size are inverted, fix.
>
> This probably only worked because the number of properties is
> hard-coded to 1.
Well, both are mathematically equivalent :)
Takashi
>
> Fixes: 71bb8a1b059e ('soundwire:
On Thu, Apr 11, 2019 at 09:55:56AM +0200, Michal Hocko wrote:
> > > FWIW, our enterprise kernel use it (latest is 4.12 based), and openSUSE
> > > kernels as well (with openSUSE Tumbleweed that includes latest
> > > kernel.org stables). AFAIK we don't enable SLAB_DEBUG even in general
> > > debug ke
Add TS clock used by two temperature sensor
Signed-off-by: Guillaume La Roque
---
drivers/clk/meson/g12a.c | 31 +++
drivers/clk/meson/g12a.h | 3 ++-
2 files changed, 33 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c
i
Add clock id used by temperature sensor for G12A Socs
Signed-off-by: Guillaume La Roque
---
include/dt-bindings/clock/g12a-clkc.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/dt-bindings/clock/g12a-clkc.h
b/include/dt-bindings/clock/g12a-clkc.h
index 30303728fe09..85cfcab10507 10
In case of cross-compilation, there may be two pkg-config tools, one for
the host and one for the target. Enable to override the default name.
Fixes: 056d28d135bc ("objtool: Query pkg-config for libelf location")
Signed-off-by: Nicolas Dichtel
---
Makefile | 3 ++-
tools/objtool/Ma
This patch series add support of Clock for temperature sensor
on Amlogic G12a SoC.
Guillaume
Guillaume La Roque (2):
dt-bindings: clk: g12a-clkc: add Temperature Sensor clock ID
clk: meson-g12a: Add Temperature Sensor clock
drivers/clk/meson/g12a.c | 31
On Wed, Apr 10, 2019 at 09:27:51AM -0700, Guenter Roeck wrote:
> Introduce local variable 'struct device *dev' and use it instead of
> dereferencing it repeatedly.
>
> The conversion was done automatically with coccinelle using the
> following semantic patches. The semantic patches and the scripts
Hi Anand,
I'm using this frequencies on the board since 3 years, without any stability
issues. The kind of worklaod used is intensive CPU-bound benchmarks running
for 20 mins at least in order to stress the system, I'm studying schedulability
under high thermal constraints.
So, I would say these
On Thu, Apr 11, 2019 at 1:16 AM Kees Cook wrote:
> diff --git a/scripts/gcc-plugins/Kconfig b/scripts/gcc-plugins/Kconfig
> index 74271dba4f94..01874ef0f883 100644
> --- a/scripts/gcc-plugins/Kconfig
> +++ b/scripts/gcc-plugins/Kconfig
> @@ -13,10 +13,11 @@ config HAVE_GCC_PLUGINS
> An a
Am Donnerstag, 11. April 2019, 10:39:40 CEST schrieb Nicolas Dichtel:
> In case of cross-compilation, there may be two pkg-config tools, one for
> the host and one for the target. Enable to override the default name.
>
> Fixes: 056d28d135bc ("objtool: Query pkg-config for libelf location")
> Signe
On Thu, Apr 11, 2019 at 12:14 AM 'Nick Desaulniers' via Clang Built
Linux wrote:
> On Wed, Apr 10, 2019 at 1:13 PM Arnd Bergmann wrote:
> >
> > The purgatory and boot Makefiles do not inherit the original cflags,
> > so clang falls back to the default target architecture when building it,
> > typ
On Wed, Apr 10, 2019 at 09:27:53AM -0700, Guenter Roeck wrote:
> Use device managed functions to simplify error handling, reduce
> source code size, improve readability, and reduce the likelyhood of bugs.
> Other improvements as listed below.
>
> The conversion was done automatically with coccinel
On Wed, 6 Mar 2019, Andreas Schwab wrote:
> Trying to log in on the serial console causes the system to freeze. The
> last message is:
>
> [ 115.597858] sifive-serial 1001.serial: BRKINT/PARMRK flag not supported
Have not seen that problem.
If you're still seeing this, could you follow up
commit 5b0d62108b46 ("mmc: sdhci-omap: Add platform specific reset
callback") skips data resets during tuning operation. Because of this,
a data error or data finish interrupt might still arrive after a command
error has been handled and the mrq ended. This ends up with a "mmc0: Got
data interrupt
This series adds a serial driver, with console support, for the
UART IP block present on the SiFive FU540 SoC. The programming
model is straightforward, but unique.
Boot-tested on a SiFive FU540 HiFive-U board, using BBL and the
open-source FSBL (with appropriate patches to the DT data).
This fo
Add a serial driver for the SiFive UART, found on SiFive FU540 devices
(among others).
The underlying serial IP block is relatively basic, and currently does
not support serial break detection. Further information on the IP
block can be found in the documentation and Chisel sources:
https://
Add DT binding documentation for the Linux driver for the SiFive
asynchronous serial IP block.
This revision incorporates changes based on feedback from Rob
Herring .
Signed-off-by: Paul Walmsley
Signed-off-by: Paul Walmsley
Cc: linux-ser...@vger.kernel.org
Cc: devicet...@vger.kernel.org
Cc: li
On Wed, Apr 10, 2019 at 09:47:20PM +0200, Peter Zijlstra wrote:
> Sure, those are actually forced 0 with the existing thing.
>
> I'll go fold smething like back in. Thanks!
> > @@ -3472,7 +3475,7 @@ icl_get_event_constraints(struct cpu_hw_events *cpuc,
> > int idx,
> > * Force instruction:pp
Hi Christoph,
On Thu, 11 Apr 2019 at 09:10, Christoph Hellwig wrote:
>
> Just like we do for all other block drivers. Especially as the limit
> imposed at the moment might be way to pessimistic for iommus.
I would appreciate some information in the changelog, as it's quite
unclear of what this
From: Paolo Bonzini
> Sent: 10 April 2019 18:09
> On 10/04/19 16:57, Sean Christopherson wrote:
> > On Wed, Apr 10, 2019 at 12:55:53PM +, David Laight wrote:
> >> From: Paolo Bonzini
> >>> Sent: 10 April 2019 10:55
> >>>
> >>> This check will soon be done on every nested vmentry and vmexit,
> >
On Wed, Apr 10, 2019 at 11:57:09AM -0700, kan.li...@linux.intel.com wrote:
> +static struct event_constraint *
> +tnt_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
> + struct perf_event *event)
That 'tnt' still cracks me up, I keep seeing explosions.
> +{
> +
On 10 April 2019 17:39, Hans de Goede wrote:
> On 10-04-19 18:14, Adam Thomson wrote:
> > On 10 April 2019 16:45, Hans de Goede wrote:
> >
> >> Hi Kyle,
> >>
> >> On 10-04-19 14:49, Kyle Tso wrote:
> >>> On Wed, Apr 10, 2019 at 6:32 PM Adam Thomson
> >>> wrote:
>
> On 09 April 2019 15:4
On Wed, Apr 10, 2019 at 02:54:16PM +0800, Chunfeng Yun wrote:
> Use devm_clk_get_optional() to get optional clock
>
> Cc: Ryder Lee
> Cc: Honghui Zhang
> Signed-off-by: Chunfeng Yun
> Acked-by: Ryder Lee
> Acked-by: Honghui Zhang
> ---
> v3: add Acked-by Ryder and Honghui
> ---
> drivers/pci
On 11.04.19 10:41, Michal Hocko wrote:
> On Wed 10-04-19 12:14:55, David Hildenbrand wrote:
>> While current node handling is probably terribly broken for memory block
>> devices that span several nodes (only possible when added during boot,
>> and something like that should be blocked completely),
On Wed, Apr 10, 2019 at 10:33:20PM -0500, Josh Poimboeuf wrote:
> On Wed, Apr 10, 2019 at 12:28:34PM +0200, Thomas Gleixner wrote:
> > +struct stack_trace {
> > + unsigned int nr_entries, max_entries;
> > + unsigned long *entries;
> > + int skip; /* input argument: How many entries to
On Wed, Apr 10, 2019 at 11:50:51AM -0400, Joe Lawrence wrote:
> -clean: archclean vmlinuxclean
> +klpclean:
> + $(Q) rm -f $(objtree)/Symbols.list
nit: $(SLIST) can be used here.
> +clean: archclean vmlinuxclean klpclean
>
> # mrproper - Delete all generated files, including .config
> #
>
On Thu, Apr 11, 2019 at 11:05:41AM +0800, Aaron Lu wrote:
> On Wed, Apr 10, 2019 at 04:44:18PM +0200, Peter Zijlstra wrote:
> > When core_cookie==0 we shouldn't schedule the other siblings at all.
>
> Not even with another untagged task?
>
> I was thinking to leave host side tasks untagged, like
_I hope I did this right... Apologies if I made a procedure mistake._
The following changes since commit
582549e3fbe137eb6ce9be591aca25ca36b4:
Merge tag 'for-linus' of
git://git.kernel.org/pub/scm/linux/kernel/git/rdma/rdma (2019-04-10
09:39:04 -1000)
are available in the Git repository at
These were found with smatch, and then generalized when applicable.
Signed-off-by: Paolo Bonzini
---
arch/x86/kvm/lapic.c | 4 +++-
include/linux/kvm_host.h | 10 ++
virt/kvm/irqchip.c | 5 +++--
virt/kvm/kvm_main.c | 6 --
4 files changed, 16 insertions(+), 9 delet
Commit ea837f1c0503 ("kbuild: make modpost processing configurable")
was intended to give KBUILD_MODPOST_WARN flexibility to be configurable.
Right now KBUILD_MODPOST_WARN gets just ignored when KBUILD_EXTMOD is
set which happens per default when building modules out of the tree.
This change gives
Le 11/04/2019 à 10:52, Rolf Eike Beer a écrit :
> Am Donnerstag, 11. April 2019, 10:39:40 CEST schrieb Nicolas Dichtel:
>> In case of cross-compilation, there may be two pkg-config tools, one for
>> the host and one for the target. Enable to override the default name.
>>
>> Fixes: 056d28d135bc ("ob
On Thu, Apr 04, 2019 at 04:36:07PM +0530, Kishon Vijay Abraham I wrote:
> Hi Lorenzo,
>
> This series includes a couple of patches, one which fixes
> inadvertent removal of pcitest.sh from kernel repo when
> doing a "clean" and other lets the user use 'h' option to
> display the list of options su
seems subject is incomplete in v2, v3 posted:
https://lore.kernel.org/patchwork/patch/1060505/
Thanks!
- Wladislav
On 10.04.2019 11:23, Wiebe, Wladislav (Nokia - DE/Ulm) wrote:
> Commit ea837f1c0503 ("kbuild: make modpost processing configurable")
> was intended to give KBUILD_MODPOST_WARN flexi
On Thu, 11 Apr 2019 17:24:09 +0800
masonccy...@mxic.com.tw wrote:
> Hi Boris,
>
>
> > > > > > Subject
> > > > > >
> > > > > > Re: [PATCH] mtd: rawnand: Add Macronix NAND read retry and
> > > randomizer
> > > > > support
> > > > > >
> > > > > > On Tue, 9 Apr 2019 17:35:39 +0800
> > >
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