On Mon, Apr 08, 2019 at 04:12:09PM +0800, Zhao Yakui wrote:
> ACRN is an open-source hypervisor maintained by Linuxfoundation.
I think tglx wanted to say "by the Linux Foundation" here.
> This is to add the Linux guest support on acrn-hypervisor.
I think you were told already:
"Please do not us
From: YueHaibing
When building with CONFIG_SPI_MEM is not set
gc warns this:
drivers/spi/spi-zynq-qspi.o: In function `zynq_qspi_supports_op':
spi-zynq-qspi.c:(.text+0x1da): undefined reference to
`spi_mem_default_supports_op'
Fixes: 67dca5e580f1 ("spi: spi-mem: Add support for Zynq QSPI contr
On Mon, Apr 08, 2019 at 11:09:46AM +0200, Borislav Petkov wrote:
> Hi all,
>
> here's v5 which keeps the HWCR functionality in kvm/x86.c so that
> emulation of AMD guests on Intel hw still can work.
>
> --
> From: Borislav Petkov
>
> The AMD hardware configuration register has some useful bits
Document the ast2400, ast2500 PCI-to-AHB bridge control driver bindings.
Signed-off-by: Patrick Venture
Reviewed-by: Rob Herring
---
Changes for v10:
- Chopped out nearly identical information.
Changes for v9:
- Added missing details about syscon parent
Changes for v8:
- None
Changes for v7:
-
On 4/8/19 4:34 PM, Sedat Dilek wrote:
v2:
sdi@iniza:~/src/linux-kernel/linux$ git --no-pager diff
diff --git a/arch/x86/crypto/camellia-aesni-avx-asm_64.S
b/arch/x86/crypto/camellia-aesni-avx-asm_64.S
index a14af6eb09cb..712d6a7e8b8f 100644
--- a/arch/x86/crypto/camellia-aesni-avx-asm_64.S
+++ b
Hello,
overall looks good for me.
I would just prefer to change the define name for temperature to
INV_ICM20602_SCAN_TEMP. It is the chip temperature that can be used for
temperature compensation for both accel and gyro data.
But it is really just a details.
Best regards,
Jean-Baptiste Maneyr
The ASPEED AST2400, and AST2500 in some configurations include a
PCI-to-AHB MMIO bridge. This bridge allows a server to read and write
in the BMC's physical address space. This feature is especially useful
when using this bridge to send large files to the BMC.
The host may use this to send down
+cc Alessandro Rubini
On 2019/4/8 22:37, Yue Haibing wrote:
> From: YueHaibing
>
> Syzkaller report this:
>
> kasan: GPF could be caused by NULL-ptr deref or user memory access
> general protection fault: [#1] SMP KASAN PTI
> CPU: 0 PID: 3692 Comm: syz-executor.0 Tainted: G C
On Mon, Apr 8, 2019 at 4:42 PM Denys Vlasenko wrote:
>
> On 4/8/19 4:34 PM, Sedat Dilek wrote:
> > v2:
> >
> > sdi@iniza:~/src/linux-kernel/linux$ git --no-pager diff
> > diff --git a/arch/x86/crypto/camellia-aesni-avx-asm_64.S
> > b/arch/x86/crypto/camellia-aesni-avx-asm_64.S
> > index a14af6eb09
On Tue, Apr 02, 2019 at 12:45:02PM -0700, kan.li...@linux.intel.com wrote:
> +static u64 pebs_update_adaptive_cfg(struct perf_event *event)
> +{
> + struct perf_event_attr *attr = &event->attr;
> + u64 sample_type = attr->sample_type;
> + u64 pebs_data_cfg = 0;
> + bool gprs, tsx_we
On Mon, Apr 08, 2019 at 07:41:15AM -0700, Sean Christopherson wrote:
> > +{
> > + if (guest_cpuid_is_amd(vcpu)) {
> > + struct msr_data tmp;
> > +
> > + tmp.index = MSR_K7_HWCR;
> > +
> > + if (kvm_get_msr_common(vcpu, &tmp))
>
> No need to get through kvm_get_msr_c
We have arch/x86/crypto/chacha-avx2-x86_64.S and
arch/x86/crypto/chacha-avx512vl-x86_64.S:
.rodata.cst32.CTR2BL
.rodata.cst32.CTR4BL
.rodata.cst32.CTR2BL
.rodata.cst32.CTR4BL
...and in arch/x86/crypto/sha256-avx2-asm.S and
arch/x86/crypto/sha512-avx2-asm.S:
.rodata.cst32.PSHUFFLE_BYTE_FLIP_MASK
You can prefix your subject now like this:
x86/acrn: Use ...
On Mon, Apr 08, 2019 at 04:12:10PM +0800, Zhao Yakui wrote:
> Linux kernel uses the HYPERVISOR_CALLBACK_VECTOR for hypervisor upcall
> vector. And it is already used for Xen and HyperV.
> After Acrn hypervisor is detected, it will also
On Wed, May 9, 2018 at 7:03 PM syzbot
wrote:
>
> Hello,
>
> syzbot found the following crash on:
>
> HEAD commit:036db8bd9637 Merge branch 'for-4.17-fixes' of git://git.ke..
> git tree: upstream
> console output: https://syzkaller.appspot.com/x/log.txt?x=14d187e780
> kernel config:
On Mon, Apr 8, 2019 at 12:21 AM David Rheinsberg
wrote:
>
> Hi
>
> A recent commit changed how `/sys/module/apparmor/parameters/enabled`
> looks. It was "Y"/"N" before, now it is an integer. I *think* the
> commit that changed this was:
Oooh... the _output_ appears differently based on the type.
On 4/8/19 4:57 PM, Sedat Dilek wrote:
We have arch/x86/crypto/chacha-avx2-x86_64.S and
arch/x86/crypto/chacha-avx512vl-x86_64.S:
.rodata.cst32.CTR2BL
.rodata.cst32.CTR4BL
.rodata.cst32.CTR2BL
.rodata.cst32.CTR4BL
...and in arch/x86/crypto/sha256-avx2-asm.S and
arch/x86/crypto/sha512-avx2-asm.S:
On Mon, Apr 8, 2019 at 7:09 AM shuah wrote:
> The patch is series in now in linux-kselftest next for 5.2
Yay, awesome! :) Thanks!
--
Kees Cook
When calling debugfs functions, there is no need to ever check the
return value. The function can work or not, but the code logic should
never do something different based on this.
Cc: Greg Kroah-Hartman
Signed-off-by: Enric Balletbo i Serra
---
drivers/platform/chrome/cros_ec_debugfs.c | 35
On 4/8/19 9:04 AM, Johannes Thumshirn wrote:
> [+Cc Michal ]
> On Mon, Apr 08, 2019 at 04:54:39PM +0200, Paolo Valente wrote:
>>
>>
>>> Il giorno 8 apr 2019, alle ore 16:49, Johannes Thumshirn
>>> ha scritto:
>>>
>>> On Mon, Apr 08, 2019 at 04:39:35PM +0200, Paolo Valente wrote:
From: Angelo
On Tue, Apr 02, 2019 at 12:45:05PM -0700, kan.li...@linux.intel.com wrote:
> +static struct event_constraint *
> +icl_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
> + struct perf_event *event)
> +{
> + /*
> + * Fixed counter 0 has less skid.
> + * F
> Il giorno 8 apr 2019, alle ore 17:05, Jens Axboe ha scritto:
>
> On 4/8/19 9:04 AM, Johannes Thumshirn wrote:
>> [+Cc Michal ]
>> On Mon, Apr 08, 2019 at 04:54:39PM +0200, Paolo Valente wrote:
>>>
>>>
Il giorno 8 apr 2019, alle ore 16:49, Johannes Thumshirn
ha scritto:
>>
On Sun, Apr 7, 2019 at 10:53 PM Stephen Rothwell wrote:
>
> Hi Dan,
>
> In commit
>
> 7c33bd4e3e97 ("libnvdimm/pmem: fix a possible OOB access when read and
> write pmem")
>
> Fixes tag
>
> Fixes: 98cc093cba1e "(block, THP: make block_device_operations.rw_page
> support THP)"
>
> has these p
On Mon, Apr 08, 2019 at 09:05:19AM -0600, Jens Axboe wrote:
> I did consider that, and that would be doable. But honestly, I'm having a
> hard time seeing what issue we are attempting to fix by doing this.
Yeah, I guess the real fix would be to update the documentation and the
expectations user-sp
On Mon, Apr 8, 2019 at 5:04 PM Denys Vlasenko wrote:
>
> On 4/8/19 4:57 PM, Sedat Dilek wrote:
> > We have arch/x86/crypto/chacha-avx2-x86_64.S and
> > arch/x86/crypto/chacha-avx512vl-x86_64.S:
> >
> > .rodata.cst32.CTR2BL
> > .rodata.cst32.CTR4BL
> > .rodata.cst32.CTR2BL
> > .rodata.cst32.CTR4BL
On Mon, Apr 08, 2019 at 04:12:11PM +0800, Zhao Yakui wrote:
> When acrn_hypervisor is detected, the hypercall is needed so that the
> acrn guest can query/config some settings. For example: it can be used
> to query the resources in hypervisor and manage the CPU/memory/device/
> interrupt for Guest
Hello, Sebastian.
On Fri, Apr 05, 2019 at 04:42:18PM +0200, Sebastian Andrzej Siewior wrote:
> On 2019-03-22 18:59:23 [+0100], To Tejun Heo wrote:
> > On 2019-03-22 10:43:34 [-0700], Tejun Heo wrote:
> > > Hello,
> Hi,
>
> > > We can switch but it doesn't really say why we'd want to. Can you
> >
The chosen clocksource and clockevent bindings have never been accepted and
parsed, remove them.
Signed-off-by: Alexandre Belloni
---
arch/arm/boot/dts/at91sam9261ek.dts | 8
1 file changed, 8 deletions(-)
diff --git a/arch/arm/boot/dts/at91sam9261ek.dts
b/arch/arm/boot/dts/at91sam926
On Sun, 7 Apr 2019, Linus Torvalds wrote:
> On Sat, Apr 6, 2019 at 12:59 PM Qian Cai wrote:
> >
> > The commit 510ded33e075 ("slab: implement slab_root_caches list")
> > changes the name of the list node within "struct kmem_cache" from
> > "list" to "root_caches_node", but leaks_show() still use
On Mon, Apr 8, 2019 at 5:04 PM Denys Vlasenko wrote:
>
> On 4/8/19 4:57 PM, Sedat Dilek wrote:
> > We have arch/x86/crypto/chacha-avx2-x86_64.S and
> > arch/x86/crypto/chacha-avx512vl-x86_64.S:
> >
> > .rodata.cst32.CTR2BL
> > .rodata.cst32.CTR4BL
> > .rodata.cst32.CTR2BL
> > .rodata.cst32.CTR4BL
On Mon, Apr 8, 2019 at 5:24 AM Nitesh Narayan Lal wrote:
>
>
> On 4/5/19 8:09 PM, Alexander Duyck wrote:
> > So I am starting this thread as a spot to collect my thoughts on the
> > current guest free page hinting design as well as point out a few
> > possible things we could do to improve upon it
On Mon, Apr 8, 2019 at 8:05 AM Enric Balletbo i Serra
wrote:
>
> When calling debugfs functions, there is no need to ever check the
> return value. The function can work or not, but the code logic should
> never do something different based on this.
>
> Cc: Greg Kroah-Hartman
> Signed-off-by: En
> Il giorno 8 apr 2019, alle ore 17:13, Jens Axboe ha scritto:
>
> On 4/8/19 9:08 AM, Johannes Thumshirn wrote:
>> On Mon, Apr 08, 2019 at 09:05:19AM -0600, Jens Axboe wrote:
>>> I did consider that, and that would be doable. But honestly, I'm having a
>>> hard time seeing what issue we are at
On 4/8/19 4:06 AM, Peng Ma wrote:
> Hi axboe,
>
> If you have no comments on these paths, please merge.
> Thank you very much.
> Patch link:
> http://patchwork.ozlabs.org/patch/1055028/
> http://patchwork.ozlabs.org/patch/1054189/
Can you resend, it's not clear which is which here, and what parts
Add an info message for the PXA2xx device driver start-up,
with the indication of the transfer mode used (DMA or GPIO).
This info is useful to individuate the timing when
the module starts.
Signed-off-by: Flavio Suligoi
---
drivers/spi/spi-pxa2xx.c | 3 +++
1 file changed, 3 insertions(+)
diff
Add support for 1V1 1V8 USB3V3 power regulators.
Signed-off-by: Pascal Paillet
---
drivers/regulator/Kconfig | 7 ++
drivers/regulator/Makefile| 1 +
drivers/regulator/stm32-pwr.c | 193 ++
3 files changed, 201 insertions(+)
create mode 100644
Document devicetree bindings for stm32mp1 pwr regulators.
Signed-off-by: Pascal Paillet
---
.../bindings/regulator/st,stm32mp1-pwr-reg.txt | 43 ++
1 file changed, 43 insertions(+)
create mode 100644
Documentation/devicetree/bindings/regulator/st,stm32mp1-pwr-reg.txt
d
The POWER block of the STM32MP1 integrates 3 fixed regulators with a ready
status bit for each one. The goal of this patchset is to add support those
regulators.
Pascal Paillet (2):
dt-bindings: regulator: Add stm32mp1 pwr regulators
regulator: Add support for stm32 power regulators
.../bind
On Fri, Feb 08, 2019 at 04:10:14PM +0100, Torsten Duwe wrote:
> In preparation for arm64 supporting ftrace built on other compiler
> options, let's have makefiles remove the $(CC_FLAGS_FTRACE)
> flags, whatever these may be, rather than assuming '-pg'.
>
> There should be no functional cha
On 2/8/19 6:10 PM, Torsten Duwe wrote:
> In preparation for arm64 supporting ftrace built on other compiler
> options, let's have makefiles remove the $(CC_FLAGS_FTRACE)
> flags, whatever these may be, rather than assuming '-pg'.
>
> There should be no functional change as a result of t
On Mon, Mar 11, 2019 at 12:49:46PM +0100, Torsten Duwe wrote:
> On Wed, Feb 13, 2019 at 11:11:04AM +, Julien Thierry wrote:
> > Hi Torsten,
> >
> > On 08/02/2019 15:08, Torsten Duwe wrote:
> > > Patch series v8, as discussed.
> > > The whole series applies cleanly on 5.0-rc5
>
> So what's the
I currently have something like the below on top, is that correct?
If so, I'll fold it back in.
--- a/arch/x86/events/core.c
+++ b/arch/x86/events/core.c
@@ -563,16 +563,17 @@ int x86_pmu_hw_config(struct perf_event
/* sample_regs_user never support XMM registers */
if (unlikel
Hi Lee,
On 2/4/19 6:06, Lee Jones wrote:
> On Fri, 08 Mar 2019, Enric Balletbo i Serra wrote:
>
>> From: Vincent Palatin
>>
>> Allow to poll on the cros_ec device to receive the MKBP events.
>>
>> The /dev/cros_[ec|fp|..] file operations now implements the poll
>> operation. The userspace can no
On Mon, Apr 08, 2019 at 08:18:35AM -0700, Alexander Duyck wrote:
> On Mon, Apr 8, 2019 at 5:24 AM Nitesh Narayan Lal wrote:
> >
> >
> > On 4/5/19 8:09 PM, Alexander Duyck wrote:
> > > So I am starting this thread as a spot to collect my thoughts on the
> > > current guest free page hinting design
Hi
On 4/7/19 5:50 PM, Pavel Machek wrote:
> Hi!
>
>>> Changes since v1:
>>>
>>> - synchronized DT label properties in DT bindings with what has been agreed
>>> for the patch "ARM: dts: omap4-droid4: Update backlight dt properties"
>>>
>>> The following changes since commit 9e98c678c2d6ae3a17cb2
On Sat, Apr 06, 2019 at 09:12:22PM -0400, Qian Cai wrote:
> The commit 665ac7e92757 ("acpi/hmat: Register processor domain to its
> memory") introduced an uninitialized "struct memory_target" that could
> cause an incorrect branching.
Thanks for the catch. We do have another patch submitted a few
On 4/8/2019 11:06 AM, Peter Zijlstra wrote:
On Tue, Apr 02, 2019 at 12:45:05PM -0700, kan.li...@linux.intel.com wrote:
+static struct event_constraint *
+icl_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
+ struct perf_event *event)
+{
+ /*
+*
From: Guo Ren
Before this patch csky-linux need CONFIG_RAM_BASE to determine start
physical address. Now we use phys_offset variable to replace the macro
of PHYS_OFFSET and we setup phys_offset with real physical address which
is determined during startup in head.S.
With this patch we needn't re
On Mon, Apr 08, 2019 at 10:49:32AM -0400, Mathieu Desnoyers wrote:
> - On Apr 8, 2019, at 10:22 AM, paulmck paul...@linux.ibm.com wrote:
>
> > On Mon, Apr 08, 2019 at 09:05:34AM -0400, Mathieu Desnoyers wrote:
> >> - On Apr 7, 2019, at 10:27 PM, paulmck paul...@linux.ibm.com wrote:
> >>
>
THe VDSO code uses the kernel helper that was originally designed
to abstract the access between 32 and 64bit systems. It worked so
far because this function is declared as 'inline'.
As we're about to revamp that part of the code, the VDSO would
break. Let's fix it by doing what should have been d
Only arch_timer_read_counter will guarantee that workarounds are
applied. So let's use this one instead of arch_counter_get_cntvct.
Signed-off-by: Marc Zyngier
---
drivers/watchdog/sbsa_gwdt.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/watchdog/sbsa_gwdt.c b/driv
The static key used to deal with the errata workaround that plague a
significant number of arm64 systems (who thought that building a timer
was that hard?) has proved to be a disaster when dealing with
lockdep. We try to activate it in contexts that were never expected,
and things break pretty loud
Let's start with the removal of the arch_timer_read_ool_enabled
static key in arch_timer_reg_read_stable. IT is not a fast path,
and we can simplify things a bit.
Signed-off-by: Marc Zyngier
---
arch/arm64/include/asm/arch_timer.h | 42 +++--
1 file changed, 28 insertions
The use of a static key in a hotplug path has proved to be a real
nightmare, and makes it impossible to have scream-free lockdep
kernel.
Let's remove the static key altogether, and focus on something saner.
Signed-off-by: Marc Zyngier
---
arch/arm64/include/asm/arch_timer.h | 4
drivers/
Only arch_timer_read_counter will guarantee that workarounds are
applied. So let's use this one instead of arch_counter_get_cntvct.
Signed-off-by: Marc Zyngier
---
arch/arm64/kernel/traps.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/kernel/traps.c b/arch/a
When a given timer is affected by an erratum and requires an
alternative implementation of set_next_event, we do a rather
complicated dance to detect and call the workaround on each
set_next_event call.
This is clearly idiotic, as we can perfectly detect whether
this CPU requires a workaround whil
Instead of always going via arch_counter_get_cntvct_stable to
access the counter workaround, let's have arch_timer_read_counter
to point to the right method.
For that, we need to track whether any CPU in the system has a
workaround for the counter. This is done by having an atomic
variable trackin
Hi Enrico,
Many thanks to send this upstream.
On 4/4/19 18:00, Jett ✈ Rink wrote:
> Reviewed-by: Jett Rink
>
> On Wed, Apr 3, 2019 at 4:40 PM wrote:
>>
>> From: Enrico Granata
>>
>> As new transfer mechanisms are added to the EC codebase, they may
>> not support v2 of the EC protocol.
>>
>> I
Pavel
Thanks for the review
On 4/7/19 5:17 PM, Pavel Machek wrote:
> Hi!
>
>> Changes since v1:
>>
>> - synchronized DT label properties in DT bindings with what has been agreed
>> for the patch "ARM: dts: omap4-droid4: Update backlight dt properties"
>>
>> The following changes since commit 9
On Mon, Apr 08, 2019 at 04:49:01PM +0100, Marc Zyngier wrote:
> THe VDSO code uses the kernel helper that was originally designed
Nit: s/THe/The/
> to abstract the access between 32 and 64bit systems. It worked so
> far because this function is declared as 'inline'.
>
> As we're about to revamp
On Mon, Apr 08, 2019 at 04:49:02PM +0100, Marc Zyngier wrote:
> Only arch_timer_read_counter will guarantee that workarounds are
> applied. So let's use this one instead of arch_counter_get_cntvct.
>
> Signed-off-by: Marc Zyngier
Acked-by: Mark Rutland
Mark.
> ---
> drivers/watchdog/sbsa_gwd
On Mon, Apr 08, 2019 at 04:49:03PM +0100, Marc Zyngier wrote:
> Only arch_timer_read_counter will guarantee that workarounds are
> applied. So let's use this one instead of arch_counter_get_cntvct.
>
> Signed-off-by: Marc Zyngier
Acked-by: Mark Rutland
Mark.
> ---
> arch/arm64/kernel/traps.c
On 2019-04-08 8:34 a.m., Wesley Sheng wrote:
> Wesley Sheng (2):
> switchtec: Fix false maximum supported PCIe function number issue
> switchtec: Fix unintended mask of MRPC event
This series looks good to me:
Reviewed-by: Logan Gunthorpe
Thanks,
Logan
On 2019-04-08 8:45 a.m., Wesley Sheng wrote:
> Joey Zhang (2):
> ntb_hw_switchtec: Remove redundant steps of
> switchtec_ntb_reinit_peer() function
> ntb_hw_switchtec: Fix setup MW with failure bug
>
> Wesley Sheng (1):
> ntb_hw_switchtec: Skip unnecessary re-setup of shared memory wi
On 08/04/2019 10:07, David Abdurachmanov wrote:
> This is only used on arm and arm64 platforms. Add COMPILE_TEST option.
>
> Tested with 5.1-rc3+ on Fedora/RISCV. CONFIG_ARM_TIMER_SP804 no more shows
> up in riscv config.
>
> Signed-off-by: David Abdurachmanov
Applied for 5.2
Thanks
-- Dani
On Mon, Apr 08, 2019 at 04:49:04PM +0100, Marc Zyngier wrote:
> When a given timer is affected by an erratum and requires an
> alternative implementation of set_next_event, we do a rather
> complicated dance to detect and call the workaround on each
> set_next_event call.
>
> This is clearly idiot
On Mon, Apr 08, 2019 at 04:49:05PM +0100, Marc Zyngier wrote:
> Let's start with the removal of the arch_timer_read_ool_enabled
> static key in arch_timer_reg_read_stable. IT is not a fast path,
Nit: s/IT/It/
> and we can simplify things a bit.
>
> Signed-off-by: Marc Zyngier
Acked-by: Mark Ru
On Mon, Apr 08, 2019 at 04:49:06PM +0100, Marc Zyngier wrote:
> The use of a static key in a hotplug path has proved to be a real
> nightmare, and makes it impossible to have scream-free lockdep
> kernel.
>
> Let's remove the static key altogether, and focus on something saner.
>
> Signed-off-by:
On Fri, Feb 1, 2019 at 9:13 AM Thomas Garnier wrote:
>
> On Thu, Jan 31, 2019 at 6:31 PM Christopher Lameter wrote:
> >
> > On Thu, 31 Jan 2019, Thomas Garnier wrote:
> >
> > > The per-cpu symbols are in a section that is zero based to create
> > > offsets. The compiler doesn't see them as offset
On 4/8/2019 11:41 AM, Peter Zijlstra wrote:
I currently have something like the below on top, is that correct?
Yes, it's correct.
If so, I'll fold it back in.
Thanks. It's really appreciated.
Kan
--- a/arch/x86/events/core.c
+++ b/arch/x86/events/core.c
@@ -563,16 +563,17 @@ int x8
Before commit c5459b829b71 ("LSM: Plumb visibility into optional "enabled"
state"), /sys/module/apparmor/parameters/enabled would show "Y" or "N"
since it was using the "bool" handler. After being changed to "int",
this switched to "1" or "0", breaking the userspace AppArmor detection
of dbus-broke
On Mon, Apr 08, 2019 at 04:49:07PM +0100, Marc Zyngier wrote:
> Instead of always going via arch_counter_get_cntvct_stable to
> access the counter workaround, let's have arch_timer_read_counter
> to point to the right method.
Nit: s/to point/point/
> For that, we need to track whether any CPU in
On Mon, Apr 8, 2019 at 5:47 AM Daniel Bristot de Oliveira
wrote:
>
> On 4/4/19 2:01 AM, Andy Lutomirski wrote:
> >> To resolve this problem, the set/unset of the IRQ/NMI context needs to
> >> be done before the execution of the first C execution, and after its
> >> return. By doing so, and using t
On Wed, Apr 3, 2019 at 7:46 PM Heikki Krogerus
wrote:
>
> Software nodes provide two features that we will need later.
> 1) Software nodes can have references to other software nodes.
> 2) Software nodes can exist before a device entry is created.
> #include
> #include
> #include
> +#includ
On 4/7/19 10:41 PM, Stephen Rothwell wrote:
> Hi all,
>
> Changes since 20190405:
>
on i386 or x86_64:
modular:
ERROR: "is_stm32_timer_trigger" [drivers/iio/adc/stm32-dfsdm-adc.ko] undefined!
or builtin:
ld: drivers/iio/adc/stm32-dfsdm-adc.o: in function `stm32_dfsdm_postenable':
stm32-dfsdm-a
On Wed, Apr 3, 2019 at 7:46 PM Heikki Krogerus
wrote:
>
> In ACPI, and now also in DT, the USB connectors usually have
> their own device nodes. In case of USB Type-C, those
> connector (port) nodes are child nodes of the controller or
> PHY device, in our case the fusb302. The software fwnodes
>
On Fri, Apr 5, 2019 at 10:55 PM Maxime Ripard wrote:
>
> Hi,
>
> On Fri, Apr 05, 2019 at 06:24:55AM -0400, Yangtao Li wrote:
> > Allwinner Process Voltage Scaling Tables defines the voltage and
> > frequency value based on the speedbin blown in the efuse combination.
> > The sunxi-cpufreq-nvmem d
Hi,
* Masahiro Yamada [190408 07:56]:
> is only generated and included
> by arch/arm/mach-omap2/, so it does not need to reside in the
> globally visible include/generated/.
>
> I moved and renamed it to arch/arm/mach-omap2/pm-asm-offsets.h
> since the prefix 'omap2-' is just redundant in mach-
On Sun, Apr 7, 2019 at 11:46 PM Thomas Gleixner wrote:
>
> On Sun, 7 Apr 2019, Andy Lutomirski wrote:
> > On Sun, Apr 7, 2019 at 3:44 PM Thomas Gleixner wrote:
> > > Actually we have: save_stack_trace()
> > >
> >
> > Like I did here:
> >
> > https://git.kernel.org/pub/scm/linux/kernel/git/luto/li
On Mon, Apr 8, 2019 at 6:31 AM Reshetova, Elena
wrote:
> Originally I was thinking that in-stack randomization makes sense
> only for x86_64, since this is what VMAP stack on x86 depends on.
> Without VMAP stack and guard pages, there are easier ways to attack,
> so hardening there does not really
@@ -963,40 +963,42 @@ static u64 pebs_update_adaptive_cfg(stru
u64 pebs_data_cfg = 0;
bool gprs, tsx_weight;
- if ((sample_type & ~(PERF_SAMPLE_IP|PERF_SAMPLE_TIME)) ||
- attr->precise_ip < 2) {
+ if (!(sample_type & ~(PERF_SAMPLE_IP|PERF_SAMPLE_TIME)) &&
+ attr-
On Fri, Apr 05, 2019 at 09:50:47AM -0700, Florian Fainelli wrote:
> Broadcom's Brahma-B53 CPUs support the same type of events that the
> Cortex-A53 supports, recognize its CPUID and map it to the cortex-a53
> events.
>
> Signed-off-by: Florian Fainelli
> ---
> tools/perf/pmu-events/arch/arm64/m
hi Will:
>
> Maybe, but I don't think we've seen a patch which accomplishes that. I think
> I'll go ahead and commit the basic one-liner, then we can always improve it
> afterwards if somebody sends a patch. It's not like this is a fastpath.
Sorry for not showing the patches I try to explain to si
In case memory resources for *buf* and *paths* were allocated,
jump to *out* and release them before return.
Addresses-Coverity-ID: 1444328 ("Resource leak")
Fixes: 6f3da20e151f ("perf report: Support builtin perf script in scripts menu")
Signed-off-by: Gustavo A. R. Silva
---
tools/perf/ui/brow
On Mon, Apr 08, 2019 at 12:25:17PM -0400, Liang, Kan wrote:
>
> > > @@ -963,40 +963,42 @@ static u64 pebs_update_adaptive_cfg(stru
> > > u64 pebs_data_cfg = 0;
> > > bool gprs, tsx_weight;
> > > - if ((sample_type & ~(PERF_SAMPLE_IP|PERF_SAMPLE_TIME)) ||
> > > - attr->precise
Hi Rob,
the following patch has been pushed in 2016 by commit 51f0aeb2d21f1.
Being able to specify which timer should act as a clocksource or a
clockevent is often requested. Doing this from the driver itself forces
to do some assumption in the timer definition ordering in the DT.
That impacts
The following is schematic diagram of the program before and after the
modification.
Before:
if (memstart_addr + linear_region_size < memblock_end_of_DRAM()) {} --(a)
if (memory_limit != PHYS_ADDR_MAX) {} --(b)
if (IS_ENABLED(CONFIG_BLK_DEV_INITRD) && phys_initrd_size
in the previous case, initrd_start and initrd_end can be successfully
returned either (base < memblock_start_of_DRAM()) or (base + size >
memblock_start_of_DRAM() + linear_region_size).
That means even linear mapping range check fail for initrd_start and
initrd_end, it still can get virtual addres
On 06.04.19 02:09, Alexander Duyck wrote:
> So I am starting this thread as a spot to collect my thoughts on the
> current guest free page hinting design as well as point out a few
> possible things we could do to improve upon it.
>
> 1. The current design isn't likely going to scale well to multi
Fix file descriptor leaks by closing fp before return.
Addresses-Coverity-ID: 1444591 ("Resource leak")
Addresses-Coverity-ID: 1444592 ("Resource leak")
Fixes: 5ea7647b333f ("tools/power turbostat: Warn on bad ACPI LPIT data")
Signed-off-by: Gustavo A. R. Silva
---
tools/power/x86/turbostat/turb
On Mon, Apr 08, 2019 at 09:18:00AM -0700, Andy Lutomirski wrote:
> On Sun, Apr 7, 2019 at 11:46 PM Thomas Gleixner wrote:
> >
> > On Sun, 7 Apr 2019, Andy Lutomirski wrote:
> > > On Sun, Apr 7, 2019 at 3:44 PM Thomas Gleixner wrote:
> > > > Actually we have: save_stack_trace()
> > > >
> > >
> > >
On Wed, Apr 3, 2019 at 7:46 PM Heikki Krogerus
wrote:
>
> Supplying also external devices - the DisplayPort connector
> and the USB role switch - software fwnodes. After this the
> driver has access to all the components tied to the USB
> Type-C connector and can start creating software node
> ref
On Mon, 8 Apr 2019, Andy Lutomirski wrote:
> On Sun, Apr 7, 2019 at 11:46 PM Thomas Gleixner wrote:
> >
> > On Sun, 7 Apr 2019, Andy Lutomirski wrote:
> > > On Sun, Apr 7, 2019 at 3:44 PM Thomas Gleixner wrote:
> > > > Actually we have: save_stack_trace()
> > > >
> > >
> > > Like I did here:
> >
On Wed, Apr 3, 2019 at 7:46 PM Heikki Krogerus
wrote:
>
> Now that the software nodes support references, and the
> device connection API support parsing fwnode references,
> replacing the old connection descriptions with software node
> references. Relying on device names when matching the
> conn
On 4/4/19 3:42 PM, Thomas Gleixner wrote:
> On Thu, 4 Apr 2019, Hook, Gary wrote:
>
>> Enablement of AMD's Secure Memory Encryption feature is determined
>> very early in the boot cycle. Part of this procedure involves scanning
>> the command line for the paramater 'mem_encrypt'.
>>
>> To determin
Hi Florian,
On Sun, Apr 07, 2019 at 02:34:22PM -0700, Florian Fainelli wrote:
> The Cortex-A72 supports all ARMv8 recommended events up to the
> RC_ST_SPEC (0x91) event, create an appropriate JSON file for mapping
> those events and update the mapfile.csv for matching the Cortex-A72 MIDR
> to that
* Tony Lindgren [190325 22:00]:
> @@ -200,6 +278,12 @@ static int sysc_get_clocks(struct sysc *ddata)
> if (ddata->nr_clocks < 1)
> return 0;
>
> + if ((ddata->cfg.quirks & SYSC_QUIRK_EXT_OPT_CLOCK)) {
> + error = sysc_init_ext_opt_clock(ddata, NULL);
> +
Get the reset control for the QSPI controller and bring it out of reset.
Suggested-by: Tien-Fong Chee
Signed-off-by: Dinh Nguyen
---
drivers/mtd/spi-nor/cadence-quadspi.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c
b/drivers/mtd/spi-nor
Hi Michal,
On Mon, Apr 08, 2019 at 04:36:15PM +0200, Michal Simek wrote:
> On 08. 04. 19 16:17, Alan Tull wrote:
> > On Mon, Apr 8, 2019 at 7:39 AM Nava kishore Manne wrote:
> >>
> >> Hi Alan,
> >>
> >> Thanks for look into it and providing the ACK.
> >> I got one minor comments from Moritz Fisch
On Fri, Apr 5, 2019 at 11:36 PM Rajat Jain wrote:
>
> Convert the intel_pmc_core driver to a platform driver, and attach using
> the ACPI enumeration method (via the ACPI device "INT33A1").
>
> Signed-off-by: Rajat Jain
> -static const struct x86_cpu_id intel_pmc_core_ids[] = {
> - INTEL_C
On 08.04.19 13:16, Morris Ku wrote:
> +> There are 10's of examples available. Please take a look around some
> +> of the existing drivers to see how their functionality is split.
> +
>
> Could you please clearly tell me the name of driver for reference.
drivers/platform/x86/pcengines-apuv2.c
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