Moi,
On Tue, Mar 26, 2019 at 04:06:33PM +0200, Heikki Krogerus wrote:
> Hi,
>
> On Tue, Mar 26, 2019 at 03:13:53PM +0200, Andy Shevchenko wrote:
> > > > > On ACPI based systems the resulting strings look like
> > > > >
> > > > > \_SB.PCI0.CIO2.port@1.endpoint@0
> > > > >
> > > > > where t
On Fri, Mar 22, 2019 at 8:31 AM Bartosz Golaszewski wrote:
>
> From: Bartosz Golaszewski
>
> Enable cpufreq-dt support for da850-evm. The cvdd is supplied by the
> tps6507 pmic with configurable output voltage, so all operating points
> can be enabled.
>
> Signed-off-by: Bartosz Golaszewski
> --
On 03/26/19 at 03:03pm, Michal Hocko wrote:
> On Tue 26-03-19 21:45:22, Baoquan He wrote:
> > On 03/26/19 at 11:17am, Michal Hocko wrote:
> > > On Tue 26-03-19 18:08:17, Baoquan He wrote:
> > > > On 03/26/19 at 10:29am, Michal Hocko wrote:
> > > > > On Tue 26-03-19 17:02:25, Baoquan He wrote:
> > >
Hi, Vignesh
Thanks for your suggestion. I will send a new patch.
At 2019-03-19 13:22:15, "Vignesh Raghavendra" wrote:
>Hi,
>
>On 13/03/19 7:15 PM, Liu Xiang wrote:
>> In some is25lp256, the DWORD1 of JEDEC Basic Flash Parameter Header
>> is 0xfff920e5. So the DWORD1[18:17] Address Bytes bi
On Tue, 26 Mar 2019 12:25:37 +0100,
Timo Wischer wrote:
>
> On 3/26/19 09:35, Takashi Iwai wrote:
>
> On Tue, 26 Mar 2019 08:49:33 +0100,
> wrote:
>
> From: Timo Wischer
>
> snd_pcm_link() can be called by the user as long as the device is not
> yet
On Tue, 2019-03-26 at 08:10 -0400, Mimi Zohar wrote:
> Hi Jarrko,
>
> On Tue, 2019-03-26 at 13:37 +0200, Jarkko Sakkinen wrote:
> > Mimi,
> >
> > Can you fix this and I can ack and send PR through my tree?
>
> Making the "trusted.h" include file public was part of David's "KEYS:
> Support TPM-wr
On Tue, Mar 26, 2019 at 05:17:40AM -0700, Huang, Kai wrote:
> On Wed, 2019-03-20 at 18:21 +0200, Jarkko Sakkinen wrote:
> > From: Sean Christopherson
> >
> > Similar to other large Intel features such as VMX and TXT, SGX must be
> > explicitly enabled in IA32_FEATURE_CONTROL MSR to be truly usabl
On Tue, Mar 26, 2019 at 04:12:43PM +0200, Sakari Ailus wrote:
> On Tue, Mar 26, 2019 at 04:06:33PM +0200, Heikki Krogerus wrote:
> > On Tue, Mar 26, 2019 at 03:13:53PM +0200, Andy Shevchenko wrote:
> > > > > Do we support swnode here?
> > > >
> > > > Good question. The swnodes have no hierarchy a
On Tue, Mar 26, 2019 at 04:12:43PM +0200, Sakari Ailus wrote:
> Moi,
>
> On Tue, Mar 26, 2019 at 04:06:33PM +0200, Heikki Krogerus wrote:
> > Hi,
> >
> > On Tue, Mar 26, 2019 at 03:13:53PM +0200, Andy Shevchenko wrote:
> > > > > > On ACPI based systems the resulting strings look like
> > > > > >
Base firmware node and clock child node binding are part of mainline kernel.
This patchset adds documentation to describe rest of the firmware child node
bindings.
Complete firmware DT node example is shown below for ease of understanding:
firmware {
zynqmp_firmware: zynqmp-firmware {
From: Rajan Vaja
Add documentation to describe ZynqMP power domain bindings.
Signed-off-by: Rajan Vaja
Signed-off-by: Jolly Shah
Reviewed-by: Rob Herring
---
.../bindings/power/xlnx,zynqmp-genpd.txt | 34
include/dt-bindings/power/xlnx-zynqmp-power.h | 39 ++
From: Rajan Vaja
Add documentation to describe Xilinx ZynqMP power management
bindings.
Signed-off-by: Rajan Vaja
Signed-off-by: Jolly Shah
Reviewed-by: Rob Herring
---
.../power/reset/xlnx,zynqmp-power.txt | 25 +++
1 file changed, 25 insertions(+)
create mode 10064
Add documentation to describe Xilinx ZynqMP reset driver
bindings.
Signed-off-by: Nava kishore Manne
Signed-off-by: Jolly Shah
Reviewed-by: Rob Herring
---
.../bindings/reset/xlnx,zynqmp-reset.txt | 52 +++
.../dt-bindings/reset/xlnx-zynqmp-resets.h| 130 ++
2 fil
From: Rajan Vaja
Add documentation to describe Xilinx ZynqMP pin controller
bindings.
Signed-off-by: Rajan Vaja
Signed-off-by: Jolly Shah
Reviewed-by: Rob Herring
---
.../bindings/pinctrl/xlnx,zynqmp-pinctrl.txt | 275 ++
1 file changed, 275 insertions(+)
create mode 100644
Add documentation to describe Xilinx ZynqMP nvmem driver
bindings.
Signed-off-by: Nava kishore Manne
Reviewed-by: Rob Herring
---
.../bindings/nvmem/xlnx,zynqmp-nvmem.txt | 47 +++
1 file changed, 47 insertions(+)
create mode 100644
Documentation/devicetree/bindings/nvmem
Add documentation to describe Xilinx ZynqMP fpga driver
bindings.
Signed-off-by: Nava kishore Manne
---
Changes for v5:
-Moved pcap node as a child to firwmare
node as suggested by Rob.
Changes for v4:
-Modified binding description as suggested by
On Tue 26-03-19 22:18:03, Baoquan He wrote:
> On 03/26/19 at 03:03pm, Michal Hocko wrote:
> > On Tue 26-03-19 21:45:22, Baoquan He wrote:
> > > On 03/26/19 at 11:17am, Michal Hocko wrote:
> > > > On Tue 26-03-19 18:08:17, Baoquan He wrote:
> > > > > On 03/26/19 at 10:29am, Michal Hocko wrote:
> > >
On Tue, Mar 26, 2019 at 09:40:07AM +0800, Yafang Shao wrote:
> When CONFIG_RCU_TRACE is not set, all these tracepoints are define as
> do-nothing macro.
> We'd better make those inline functions that take proper arguments.
>
> As RCU_TRACE() is defined as do-nothing marco as well when
> CONFIG_RCU
To transfer via SPI the tegra20-slink driver first sets the command
register, which contains the chip select value, and after that the
command2 register, which contains the chip select line. This leads to a
small spike in the chip selct 0 line between the set of the value and
the selection of the c
On 3/20/19 4:08 PM, Miroslav Benes wrote:
diff --git a/scripts/Makefile.build b/scripts/Makefile.build
index fd03d60f6c5a..1e28ad21314c 100644
--- a/scripts/Makefile.build
+++ b/scripts/Makefile.build
@@ -247,6 +247,11 @@ cmd_gen_ksymdeps = \
$(CONFIG_SHELL) $(srctree)/scripts/gen_ksym
On Tue, Mar 26, 2019 at 01:29:54PM +0100, Rafael J. Wysocki wrote:
> On Tue, Mar 26, 2019 at 1:02 PM Leon Romanovsky wrote:
> >
> > From: Leon Romanovsky
> >
> > Kernel is booted with less possible CPUs (possible_cpus kernel boot
> > option) than available CPUs will have prints like this:
> >
> >
Changes since v5:
Use devm_platform_ioremap_resource().
Shravan Kumar Ramani (1):
gpio: add driver for Mellanox BlueField GPIO controller
drivers/gpio/Kconfig | 7 +++
drivers/gpio/Makefile | 1 +
drivers/gpio/gpio-mlxbf.c | 153 ++
3 fi
The patch
regulator: sc2731: Constify regulators
has been applied to the regulator tree at
https://git.kernel.org/pub/scm/linux/kernel/git/broonie/regulator.git
All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent
The patch
ASoC: fsl: Add Audio Mixer CPU DAI driver
has been applied to the asoc tree at
https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git
All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Lin
The patch
regulator: tps65217: Fix off-by-one for latest seletor of tps65217_uv1_ranges
has been applied to the regulator tree at
https://git.kernel.org/pub/scm/linux/kernel/git/broonie/regulator.git
All being well this means that it will be integrated into the linux-next
tree (usually s
The patch
regulator: da9063: convert header to SPDX
has been applied to the regulator tree at
https://git.kernel.org/pub/scm/linux/kernel/git/broonie/regulator.git
All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and se
The patch
spi: stm32-qspi: add spi_master_put in release function
has been applied to the spi tree at
https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git
All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and
The patch
spi: stm32-qspi: add dma support
has been applied to the spi tree at
https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git
All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
th
The patch
regulator: act8865: Constify regulator_ops
has been applied to the regulator tree at
https://git.kernel.org/pub/scm/linux/kernel/git/broonie/regulator.git
All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and s
The patch
regulator: act8865: Convert to regulator core's simplified DT parsing code
has been applied to the regulator tree at
https://git.kernel.org/pub/scm/linux/kernel/git/broonie/regulator.git
All being well this means that it will be integrated into the linux-next
tree (usually some
This patch adds support for the GPIO controller used by Mellanox
BlueField SOCs.
Reviewed-by: David Woods
Signed-off-by: Shravan Kumar Ramani
---
drivers/gpio/Kconfig | 7 +++
drivers/gpio/Makefile | 1 +
drivers/gpio/gpio-mlxbf.c | 153 +
The patch
ASoC: add fsl_audmix DT binding documentation
has been applied to the asoc tree at
https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git
All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to
On Tue, Mar 26, 2019 at 03:30:50PM +0100, Randolph Maaßen wrote:
> To transfer via SPI the tegra20-slink driver first sets the command
> register, which contains the chip select value, and after that the
> command2 register, which contains the chip select line. This leads to a
> small spike in the
On Mon, 25 Mar 2019 17:23:34 -0400
Steven Rostedt wrote:
> On Wed, 13 Feb 2019 01:12:44 +0900
> Masami Hiramatsu wrote:
>
> > Prohibit probing on IRQ handlers in irqentry_text because
> > if it interrupts user mode, at that point we haven't changed
> > to kernel space yet and which eventually l
Hello, Roman.
> >
> > So, does it mean that this function always returns two following elements?
> > Can't it return a single element using the return statement instead?
> > The second one can be calculated as ->next?
> >
> Yes, they follow each other and if you return "prev" for example you can
On Tue, Mar 26, 2019 at 01:40:57PM +0100, Thomas Gleixner wrote:
> On Tue, 26 Mar 2019, Huang, Kai wrote:
> > On Wed, 2019-03-20 at 18:21 +0200, Jarkko Sakkinen wrote:
> > > 13 files changed, 1657 insertions(+), 2 deletions(-)
> > > create mode 100644 arch/x86/include/uapi/asm/sgx.h
> > > create
This patch adds the suspend/resume callbacks for Marvell 10G PHYs. The
three PCS (base-t, base-r and 1000base-x) are set in low power (the PCS
are powered down) when the PHY isn't used.
Signed-off-by: Antoine Tenart
Reviewed-by: Andrew Lunn
---
drivers/net/phy/marvell10g.c | 14 ++
When the 88x2110 PHY support was added, the suspend and resume callbacks
were forgotten. This patch adds them to the 88x2110 PHY callback
definition.
Signed-off-by: Antoine Tenart
Reviewed-by: Andrew Lunn
---
drivers/net/phy/marvell10g.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/dri
On 2/12/19 18:50, Krzysztof Kozlowski wrote:
> The DTS patch depends on bindings header with clock ID. I will take it
> through samsung-soc for consecutive release.
> Krzysztof Kozlowski (4):
> dt-bindings: clock: exynos: Put CLK_UART3 in order
> dt-bindings: clock: exynos: Add ADC clock ID
On Mon, Feb 25, 2019 at 05:58:21PM +0100, Paweł Chmiel wrote:
> From: Tomasz Figa
>
> This patch adds documentation for binding of extcont Fairchild
> Semiconductor FSA9480 microusb switch.
> This usb port accessory detector and switch, can be found for example in
> some Samsung s5pv210 based pho
Hi James,
On 03/26/2019 09:25 AM, James Bottomley wrote:
Looking at the contents of linux/keys/trusted.h, it looks like the
wrong decision to move it. The contents are way too improperly named
and duplicative to be in a standard header. It's mostly actually TPM
code including a redefinition of
On Mon, Feb 25, 2019 at 10:59:19PM -0800, Bjorn Andersson wrote:
> qcom_qmp_phy_init() is extended to support the additional register
> writes needed in PCS MISC and the appropriate sequences and resources
> are defined for SDM845.
>
> Signed-off-by: Bjorn Andersson
> ---
> .../devicetree/bindin
Andi,
On Mon, 25 Mar 2019, Andi Kleen wrote:
> >So on user space to kernel space transitions swapping in kernel GS should
> >simply do:
> > userGS = RDGSBASE()
> > WRGSBASE(kernelGS)
>
> This would also need to find kernelGS first, by doing RDPID and then
> reading it from mem
> On 26 Mar 2019, at 15:48, Vitaly Kuznetsov wrote:
>
> Liran Alon writes:
>
>>> On 26 Mar 2019, at 15:07, Vitaly Kuznetsov wrote:
>>> - Instread of putting the temporary HF_SMM_MASK drop to
>>> rsm_enter_protected_mode() (as was suggested by Liran), move it to
>>> emulator_set_cr() modifyi
Add an mfd driver for Intel Merrifield Basin Cove PMIC.
Signed-off-by: Andy Shevchenko
---
- corrected name of Power Source detection driver
drivers/mfd/Kconfig | 11 ++
drivers/mfd/Makefile | 1 +
drivers/mfd/intel_soc_pmic_mrfld.c | 157 +++
Le 19/03/2019 à 14:20, Razvan Stefanescu a écrit :
> Use a helper function to check that a port needs to use half duplex
> communication, replacing several occurrences of multi-line bit checking.
>
> Fixes: b389f173aaa1 ("tty/serial: atmel: RS485 half duplex w/DMA: enable
> RX after TX is done")
>
On Sat, Mar 02, 2019 at 11:06:36PM +, Colin King wrote:
> From: Colin Ian King
>
> The non-null check on udata is redundant as this check was performed
> just a few statements earlier and the check is always true as udata
> must be non-null at this point. Remove redundant the check on udata
>
On 3/26/19 4:45 AM, Adrian Hunter wrote:
Hi
Doing:
make -C tools clean
Results in:
git diff --stat
tools/pci/pcitest.sh | 72
tools/testing/selftests/livepatch/test-callbacks.sh | 587
-
On Tue, Mar 26, 2019 at 3:41 PM Leon Romanovsky wrote:
>
> On Tue, Mar 26, 2019 at 01:29:54PM +0100, Rafael J. Wysocki wrote:
> > On Tue, Mar 26, 2019 at 1:02 PM Leon Romanovsky wrote:
> > >
> > > From: Leon Romanovsky
> > >
> > > Kernel is booted with less possible CPUs (possible_cpus kernel bo
On Thu, 28 Feb 2019 12:31:53 +0530, Naga Sureshkumar Relli wrote:
> This patch adds the dts binding document for Zynq SOC QSPI
> controller.
>
> Signed-off-by: Naga Sureshkumar Relli
> ---
> .../devicetree/bindings/spi/spi-zynq-qspi.txt | 25
> ++
> 1 file changed, 25 i
Le 19/03/2019 à 14:20, Razvan Stefanescu a écrit :
> In half-duplex operation, RX should be started after TX completes.
>
> If DMA is used, there is a case when the DMA transfer completes but the
> TX FIFO is not emptied, so the RX cannot be restarted just yet.
>
> Use a boolean variable to store
On Wed, 2019-03-20 at 20:50 -0400, Richard Guy Briggs wrote:
> On 2019-03-20 19:48, Paul Moore wrote:
> > On Sat, Mar 16, 2019 at 8:10 AM Richard Guy Briggs wrote:
> > > In commit fa516b66a1bf ("EVM: Allow runtime modification of the set of
> > > verified xattrs"), the call to audit_log_start() is
On Fri 2019-03-22 17:29:30, Sakari Ailus wrote:
> Add support for %pfw conversion specifier (with "f" and "P" modifiers) to
> support printing full path of the node, including its name ("f") and only
> the node's name ("P") in the printk family of functions. The two flags
> have equivalent function
On 03/23, Thomas Gleixner wrote:
>
> On Thu, 28 Feb 2019, Gustavo A. R. Silva wrote:
>
> > arch/x86/include/asm/syscall.h | 28
> > 1 file changed, 28 insertions(+)
>
> Second thoughts. So this adds 28 /* fall through */ comments. Now I
> appreciate the effort, but c
Tegra194 has six PCIe controllers based on Synopsys DesignWare core.
There are two Universal PHY (UPHY) blocks with each supporting 12(HSIO:
Hisg Speed IO) and 8(NVHS: NVIDIA High Speed) lanes respectively.
Controllers:0~4 use UPHY lanes from HSIO brick whereas Controller:5 uses
UPHY lanes from NVH
Remove multiple write enable and disable sequences of dbi registers as
Tegra194 implements writes to BAR-0 register (offset: 0x10) controlled by
DBI write-lock enable bit thereby not allowing any further writes to BAR-0
register in config space to take place. Hence disabling write permission
only t
save pci_bus pointer created by PCIe sub-system's
pci_scan_root_bus_bridge() to be used by host controller drivers for post
processing. Tegra host controller driver needs it for the following
reasons
- to derive pci_host_bridge structure from pci_bus which is used to
configure iATU's outbound regio
move PCIe config space capability search API to common designware file
as this can be used by both host and ep mode codes.
It also adds extended capability search APIs.
Signed-off-by: Vidya Sagar
---
drivers/pci/controller/dwc/pcie-designware-ep.c | 37 +
drivers/pci/controller/dwc/p
Add #defines for the Data Link Feature and Physical Layer 16.0 GT/s
features.
Signed-off-by: Vidya Sagar
---
include/uapi/linux/pci_regs.h | 22 +-
1 file changed, 21 insertions(+), 1 deletion(-)
diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
inde
Add support for Tegra194 PCIe controllers. These controllers are based
on Synopsys DesignWare core IP.
Signed-off-by: Vidya Sagar
---
.../bindings/pci/nvidia,tegra194-pcie.txt | 209 +
.../devicetree/bindings/phy/phy-tegra194-p2u.txt | 34
2 files changed, 24
Add P2U (PIPE to UPHY) and PCIe controller nodes to device tree.
The Tegra194 SoC contains six PCIe controllers and twenty P2U instances
grouped into two different PHY bricks namely High-Speed IO (HSIO-12 P2Us)
and NVIDIA High Speed (NVHS-8 P2Us) respectively.
Signed-off-by: Vidya Sagar
---
arch
Enable PCIe controller nodes to enable respective PCIe slots on
P2972- board. Following is the ownership of slots by different
PCIe controllers.
Controller-0 : M.2 Key-M slot
Controller-1 : On-board Marvell eSATA controller
Controller-3 : M.2 Key-E slot
Signed-off-by: Vidya Sagar
---
arch/ar
Synopsys DesignWare core based PCIe controllers in Tegra 194 SoC interface
with Universal PHY (UPHY) module through a PIPE2UPHY (P2U) module.
For each PCIe lane of a controller, there is a P2U unit instantiated at
hardware level. This driver provides support for the programming required
for each P2
Add PCIe host controller driver for DesignWare core based
PCIe controller IP present in Tegra194.
Signed-off-by: Vidya Sagar
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 2d9c39033c1a..2ddea5
Add support for Synopsys DesignWare core IP based PCIe host controller
present in Tegra194 SoC.
Signed-off-by: Vidya Sagar
---
drivers/pci/controller/dwc/Kconfig | 10 +
drivers/pci/controller/dwc/Makefile|1 +
drivers/pci/controller/dwc/pcie-tegra194.c | 1862 +
On 3/26/19 15:23, Takashi Iwai wrote:
On Tue, 26 Mar 2019 12:25:37 +0100,
Timo Wischer wrote:
On 3/26/19 09:35, Takashi Iwai wrote:
On Tue, 26 Mar 2019 08:49:33 +0100,
wrote:
From: Timo Wischer
snd_pcm_link() can be called by the user as long as the
On Tue, Mar 26, 2019 at 11:50:52PM +0900, Masami Hiramatsu wrote:
> On Mon, 25 Mar 2019 17:23:34 -0400
> Steven Rostedt wrote:
>
> > On Wed, 13 Feb 2019 01:12:44 +0900
> > Masami Hiramatsu wrote:
> >
> > > Prohibit probing on IRQ handlers in irqentry_text because
> > > if it interrupts user mod
On Tue, Mar 26, 2019 at 08:13:11PM +0800, Yafang Shao wrote:
> When CONFIG_RCU_TRACE is not set, all these tracepoints are defined as
> do-nothing macro.
> We'd better make those inline functions that take proper arguments.
>
> As RCU_TRACE() is defined as do-nothing marco as well when
> CONFIG_RC
On 26/03/2019 06:29, Greg Kroah-Hartman wrote:
> This is the start of the stable review cycle for the 4.9.166 release.
> There are 30 patches in this series, all will be posted as a response
> to this one. If anyone has any issues with these being applied, please
> let me know.
>
> Responses sh
On 26/03/2019 06:29, Greg Kroah-Hartman wrote:
> This is the start of the stable review cycle for the 4.14.109 release.
> There are 41 patches in this series, all will be posted as a response
> to this one. If anyone has any issues with these being applied, please
> let me know.
>
> Responses s
From: Neil Leeder
Add support for the SMMU Performance Monitor Counter Group
information from ACPI. This is in preparation for its use
in the SMMUv3 PMU driver.
Signed-off-by: Neil Leeder
Signed-off-by: Hanjun Guo
Signed-off-by: Shameer Kolothum
Reviewed-by: Robin Murphy
Acked-by: Lorenzo Pi
On 26/03/2019 06:29, Greg Kroah-Hartman wrote:
> This is the start of the stable review cycle for the 4.19.32 release.
> There are 45 patches in this series, all will be posted as a response
> to this one. If anyone has any issues with these being applied, please
> let me know.
>
> Responses sh
This adds a driver for the SMMUv3 PMU into the perf framework.
It includes an IORT update to support PM Counter Groups.
This is based on the initial work done by Neil Leeder[1]
SMMUv3 PMCG devices are named as smmuv3_pmcg_
where is the physical page address of the SMMU PMCG.
For example, the PMC
From: Neil Leeder
Adds a new driver to support the SMMUv3 PMU and add it into the
perf events framework.
Each SMMU node may have multiple PMUs associated with it, each of
which may support different events.
SMMUv3 PMCG devices are named as smmuv3_pmcg_ where
is the physical page address of the
This adds support for MSI-based counter overflow interrupt.
Signed-off-by: Shameer Kolothum
Reviewed-by: Robin Murphy
---
drivers/perf/arm_smmuv3_pmu.c | 58 +++
1 file changed, 58 insertions(+)
diff --git a/drivers/perf/arm_smmuv3_pmu.c b/drivers/perf/a
HiSilicon erratum 162001800 describes the limitation of
SMMUv3 PMCG implementation on HiSilicon Hip08 platforms.
On these platforms, the PMCG event counter registers
(SMMU_PMCG_EVCNTRn) are read only and as a result it
is not possible to set the initial counter period value
on event monitor start.
On 26/03/2019 06:29, Greg Kroah-Hartman wrote:
> This is the start of the stable review cycle for the 5.0.5 release.
> There are 52 patches in this series, all will be posted as a response
> to this one. If anyone has any issues with these being applied, please
> let me know.
>
> Responses shou
Coding style fixup and rebase of v3, and resubmit of the Kconfig patch
that got dropped from v2. No other changes.
Thanks for your continued attention and reviews!
George
Hi, Vignesh
At 2019-03-19 13:22:15, "Vignesh Raghavendra" wrote:
>Hi,
>
>On 13/03/19 7:15 PM, Liu Xiang wrote:
>> In some is25lp256, the DWORD1 of JEDEC Basic Flash Parameter Header
>> is 0xfff920e5. So the DWORD1[18:17] Address Bytes bits are 0b00,
>> means that 3-Byte only addressing. B
The module was initializing completions whenever it was going to wait on
them, and not when the completion was allocated. This is incorrect
according to the completion docs:
Calling init_completion() on the same completion object twice is
most likely a bug [...]
Re-initialization is also
On Tue 2019-03-26 15:55:57, Andy Shevchenko wrote:
> On Tue, Mar 26, 2019 at 03:39:47PM +0200, Sakari Ailus wrote:
> > On Tue, Mar 26, 2019 at 03:13:53PM +0200, Andy Shevchenko wrote:
> > > On Sun, Mar 24, 2019 at 08:17:46PM +0200, Sakari Ailus wrote:
>
> > > The patch series by Petr I mentioned t
These values are not referred to anywhere else in the kernel. Card
detect is controlled by the device tree property "mediatek,cd-poll",
and there is no driver support for eMMC whatsoever.
Signed-off-by: George Hilliard
---
v2: Rewrite of v1
v3: [Not present]
v4: Resubmit of v2
drivers/staging/m
On Tue, 26 Mar 2019 05:53:22 +
Parav Pandit wrote:
> > -Original Message-
> > From: linux-kernel-ow...@vger.kernel.org > ow...@vger.kernel.org> On Behalf Of Parav Pandit
> > Sent: Monday, March 25, 2019 10:19 PM
> > To: Alex Williamson
> > Cc: k...@vger.kernel.org; linux-kernel@vg
Hi Thomas,
thanks for reviewing this patch.
[ ... ]
>> +
>> +/*
>> + * Exponential moving average computation
>> + */
>> +static int irq_timings_ema_new(s64 value, s64 ema_old)
>
> There is a mixed bag of s64/u64 all over this code. Please stay
> consistent. We had enough sign confusion bugs
On Tue, 26 Mar 2019 12:36:22 +0530
Kirti Wankhede wrote:
> On 3/23/2019 4:50 AM, Parav Pandit wrote:
> > There are five problems with current code structure.
> > 1. mdev device is placed on the mdev bus before it is created in the
> > vendor driver. Once a device is placed on the mdev bus without
On Tue, 26 Mar 2019 08:18:15 -0700
"Paul E. McKenney" wrote:
> On Tue, Mar 26, 2019 at 08:13:11PM +0800, Yafang Shao wrote:
> > When CONFIG_RCU_TRACE is not set, all these tracepoints are defined as
> > do-nothing macro.
> > We'd better make those inline functions that take proper arguments.
> >
> -Original Message-
> From: Kirti Wankhede
> Sent: Tuesday, March 26, 2019 2:06 AM
> To: Parav Pandit ; k...@vger.kernel.org; linux-
> ker...@vger.kernel.org; alex.william...@redhat.com
> Cc: Neo Jia
> Subject: Re: [PATCH 8/8] vfio/mdev: Improve the create/remove sequence
>
>
>
> On
On Tue, Mar 26, 2019 at 04:12:27PM +0100, Rafael J. Wysocki wrote:
> On Tue, Mar 26, 2019 at 3:41 PM Leon Romanovsky wrote:
> >
> > On Tue, Mar 26, 2019 at 01:29:54PM +0100, Rafael J. Wysocki wrote:
> > > On Tue, Mar 26, 2019 at 1:02 PM Leon Romanovsky wrote:
> > > >
> > > > From: Leon Romanovsky
On Mon, 2019-03-25 at 15:09 -0700, Matthew Garrett wrote:
> Systems in lockdown mode should block the kexec of untrusted kernels.
> For x86 and ARM we can ensure that a kernel is trustworthy by validating
> a PE signature, but this isn't possible on other architectures. On those
> platforms we can
On Tue, 26 Mar 2019 12:37:37 +
"Liu, Yi L" wrote:
> > From: Alex Williamson [mailto:alex.william...@redhat.com]
> > Sent: Tuesday, March 26, 2019 2:17 AM
> > To: Liu, Yi L
> > Subject: Re: [RFC v2 1/2] vfio/pci: export common symbols in vfio-pci
> >
> > On Sat, 23 Mar 2019 11:06:44 +
>
Commit-ID: db779ef67ffeadbb44e9e818eb64dbe528e2f48f
Gitweb: https://git.kernel.org/tip/db779ef67ffeadbb44e9e818eb64dbe528e2f48f
Author: Bhupesh Sharma
AuthorDate: Tue, 26 Mar 2019 12:20:28 +0530
Committer: Borislav Petkov
CommitDate: Tue, 26 Mar 2019 16:36:03 +0100
proc/kcore: Remove u
This patch adds a parsing failures counter to struct tep_handle. The counter can
be used to track failures on parsing event format files. It is updated
automatically by tep_parse_event(), when failure is detected. The patch also
adds two new APIs for accessing the counter:
tep_get_parsing_failures
This patch series does a cleanup of traceevent implementation and APIs:
- All "pevent" function parameters and local variables are renamed to "tep".
This makes the implementation consistent with the chosen naming convention,
tep (trace event parser), and avoids any confusion with the old "
Kmemleak could quickly fail to allocate an object structure and then
disable itself in a low-memory situation. For example, running a mmap()
workload triggering swapping and OOM. This is especially problematic for
running things like LTP testsuite where one OOM test case would disable
the whole kme
This patch renames from "pevent" to "tep":
- all "pevent" input arguments of libtraceevent internal functions.
- all local "pevent" variables of libtraceevent.
This makes the implementation consistent with the chosen naming convention,
tep (trace event parser), and will avoid any confusion with t
This patch renames "struct tep_handle *pevent" input arguments of libtraceevent
APIs to "struct tep_handle *tep". This makes the API consistent with the chosen
naming convention: tep (trace event parser), instead of the old pevent.
Signed-off-by: Tzvetomir Stoyanov
---
tools/lib/traceevent/event
This patch removes trivial filter tep APIs:
enum tep_filter_trivial_type
tep_filter_event_has_trivial()
tep_update_trivial()
tep_filter_clear_trivial()
Trivial filters is an optimization, used only in the first
version of KernelShark. The API is deprecated, the next KernelShark
release does no
This patch renames "pevent" member of the struct tep_event to "tep". This makes
the struct consistent with the chosen naming convention:
tep (trace event parser), instead of the old pevent.
Signed-off-by: Tzvetomir Stoyanov
---
tools/lib/traceevent/event-parse.c| 32 +
This patch renames "pevent" member of the struct tep_event_filter to "tep".
This makes the struct consistent with the chosen naming convention:
tep (trace event parser), instead of the old pevent.
Signed-off-by: Tzvetomir Stoyanov
---
tools/lib/traceevent/event-parse.h | 2 +-
tools/lib/tracee
This patch removes call to exit() from tep_filter_add_filter_str(). A library
function should not force the application to exit. In the current implementation
tep_filter_add_filter_str() calls exit() when a special "test_filters" mode is
set, used only for debugging purposes. When this mode is set
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