On 23/03/2019 23:10, Kangjie Lu wrote:
> As other functions in this module do, edev should be checked to
> ensure that it is not NULL.
> The fix inserts such as check to avoid potential NULL pointer
> dereference.
>
> Signed-off-by: Kangjie Lu
> ---
> drivers/firmware/edd.c | 2 ++
> 1 file chan
Hello,
syzbot found the following crash on:
HEAD commit:babf09c3 Merge tag 'tag-chrome-platform-fixes-for-v5.1-rc2..
git tree: upstream
console output: https://syzkaller.appspot.com/x/log.txt?x=1509f28b20
kernel config: https://syzkaller.appspot.com/x/.config?x=9a31fb246de2a622
da
Patch 1 switches MSR_MISC_FEATURES_ENABLE between host and guest to avoid
cpuid faulting and ring3mwait of host leaking to guest. Because cpuid
faulting eanbled in host may potentially cause guest boot failure, and kvm
doesn't expose ring3mwait to guest yet, it should be leaked to guest.
Patch 2 o
KVM needs to switch MSR_MISC_FEATURES_ENABLES between host and guest in
every pcpu/vcpu context switch. Since WRMSR is expensive, this patch tries
to save cycles by avoiding WRMSR MSR_MISC_FEATURES_ENABLES whenever possible.
If host's value is zero, nothing needs to be done, since guest can use
kv
There are two defined bits in MSR_MISC_FEATURES_ENABLES, bit 0 for cpuid
faulting and bit 1 for ring3mwait.
== cpuid Faulting ==
cpuid faulting is a feature about CPUID instruction. When cpuid faulting
is enabled, all execution of the CPUID instruction outside system-management
mode (SMM) cause a
On Mon, 25 Mar 2019, Matti Vaittinen wrote:
> Hello again Lee & all,
>
> On Thu, Feb 28, 2019 at 10:22:48AM +0200, Matti Vaittinen wrote:
> > On Thu, Feb 28, 2019 at 08:10:55AM +, Lee Jones wrote:
> > > On Thu, 28 Feb 2019, Matti Vaittinen wrote:
> > >
> > > > Hello Lee and Mark,
> > > >
>
This patch series
*) adds support for SERDES module in am654
*) modifies phy_reset API to invoke pm_runtime_get/pm_runtime_put since
the reset callback can access registers.
*) Add *release* phy_ops to be invoked when the consumer relinquishes
PHY
Changes from v2:
*) Fix typos pointed out
Add a new phy_ops *release* invoked when the consumer relinquishes the
PHY using phy_put/devm_phy_put. The initializations done by the PHY
driver in of_xlate call back can be can be cleaned up here.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/phy/phy-core.c | 5 +
include/linux/phy/ph
Hi Mimi
On 03/22/19 at 03:35pm, Mimi Zohar wrote:
> Verify IMA is enabled before failing tests or emitting irrelevant
> messages. Also, don't skip the test if signatures are not required.
>
> Suggested-by: Dave Young
> Signed-off-by: Mimi Zohar
> ---
> Dave, if this patch resolves the outstandi
On 22.03.19 15:43, Pierre Morel wrote:
> The AP interruptions are assigned on a queue basis and
> the GISA structure is handled on a VM basis, so that
> we need to add a structure we can retrieve from both side
> holding the information we need to handle PQAP/AQIC interception
> and setup the GISA.
PHY drivers may try to access PHY registers in the ->reset() callback.
Invoke phy_pm_runtime_get_sync() before invoking the ->reset() callback
so that the PHY drivers don't have to enable clocks by themselves before
accessing PHY registers.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/phy/p
AM654x has two SERDES instances. Each instance has three input clocks
(left input, externel reference clock and right input) and two output
clocks (left output and right output) in addition to a PLL mux clock
which the SERDES uses for Clock Multiplier Unit (CMU refclock).
The PLL mux clock can sele
Add a new SERDES driver for TI's AM654x SoC which configures
the SERDES only for PCIe. Support fo USB3 will be added later.
SERDES in am654x has three input clocks (left input, externel reference
clock and right input) and two output clocks (left output and right
output) in addition to a PLL mux c
From: Roger Quadros
Add support to select all 16 CLKSEL combinations that are shown in
"SerDes Reference Clock Distribution" in AM65 TRM.
Signed-off-by: Roger Quadros
Signed-off-by: Kishon Vijay Abraham I
---
drivers/phy/ti/phy-am654-serdes.c | 134 +++---
1 file chang
On 2019-03-22, Julien Grall wrote:
> Apologies for a possible stupid question.
It's an important question because the behavior of console printing has
changed. (Or, rather, is in the process of being changed. Depending on
complaints/approval, it may change some more.)
> On 20/03/2019 17:15, Seba
On Mon, Mar 25, 2019 at 08:02:06AM +, Lee Jones wrote:
> On Mon, 25 Mar 2019, Matti Vaittinen wrote:
>
> > Hello again Lee & all,
> >
> > On Thu, Feb 28, 2019 at 10:22:48AM +0200, Matti Vaittinen wrote:
> > > On Thu, Feb 28, 2019 at 08:10:55AM +, Lee Jones wrote:
> > > > On Thu, 28 Feb 20
On 03/25/19 at 08:53am, Borislav Petkov wrote:
> On Mon, Mar 25, 2019 at 03:27:10PM +0800, Baoquan He wrote:
> > Kexec kernel also need to get rsdp to get SRAT tables so that KASLR can
> > avoid those hotpluggable regions in boot compression stage.
> >
> > The kexec_file_load has filled in acpi_rs
On Mon, 25 Mar 2019, Zhao, Yakui wrote:
> >> +/* SPDX-License-Identifier: GPL-2.0 */ #ifndef _ASM_X86_ACRNHYPER_H
> >> +#define _ASM_X86_ACRNHYPER_H
> >> +
> >> +#include
> >> +#include
> >> +
> >> +#ifdef CONFIG_ACRN
> >> +/* ACRN Hypervisor callback */
> >> +void acrn_hv_callback_vector(void);
On 04-03-19, 23:08, Bjorn Andersson wrote:
> Enable blsp1_uart3, define its pinconf and add the bluetooth node.
>
> It seems provisioning is lacking a valid BD address, preventing the
> interface from initializing, so provide a dummy for now.
This looks good though I need to hand edit the patch o
pon., 25 mar 2019 o 00:12 Andrew Jeffery napisał(a):
>
>
>
> On Mon, 25 Mar 2019, at 09:40, Kangjie Lu wrote:
> > In case devm_kzalloc, the patch returns ENOMEM to avoid potential
> > NULL pointer dereference.
> >
> > Signed-off-by: Kangjie Lu
>
> Reviewed-by: Andrew Jeffery
>
> > ---
> > drive
On Mon, 25 Mar 2019, Zhao, Yakui wrote:
>
> >-Original Message-
> >From: Thomas Gleixner [mailto:t...@linutronix.de]
> >Sent: Saturday, March 23, 2019 12:02 AM
> >To: Zhao, Yakui
> >Cc: linux-kernel@vger.kernel.org; x...@kernel.org; Chen, Jason CJ
> >
> >Subject: Re: [RFC PATCH 3/3] arch/
The Linux RISC-V 32bit kernel is broken after we moved setup_vm() from
kernel/setup.c to mm/init.c because Linux RISC-V 32bit kernel by default
uses cmodel=medlow which results in a non-position-independent setup_vm().
This patch fixes Linux RISC-V 32bit kernel booting by:
1. Forcing cmodel=medany
Add "ti,syscon-pcie-mode" dt-binding to hold phandle to the syscon
register that should be used to configure PCIe in RC mode or EP mode.
Signed-off-by: Kishon Vijay Abraham I
---
Documentation/devicetree/bindings/pci/pci-keystone.txt | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Document
No functional change. Instead of having two functions
ks_pcie_add_pcie_port and ks_pcie_dw_host_init for initializing host,
have a single function to perform all the host initialization.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/controller/dwc/pci-keystone.c | 63 +---
Add "reg-names" binding information in order for device tree node
to be populated with the correct register strings. This will break
old dt compatibility. However Keystone PCI has never worked
in upstream kernel due to lack of SERDES support. Before SERDES
support is added, cleanup the Keystone PCI
pci-keystone driver uses irq_of_parse_and_map to get irq number of
error_irq. Use platform_get_irq instead and move platform_get_irq()
and request_irq() of error_irq from ks_pcie_add_pcie_port to ks_pcie_probe
since error_irq is common to both RC mode and EP mode.
Signed-off-by: Kishon Vijay Abrah
Use platform_get_resource_byname() instead of platform_get_resource() which
uses index to get memory resources. While at that get the memory resource
defined specifically for configuration space instead of deriving the
configuration space address from dbics address space. Since pci-keystone
driver
Add PCIe RC support for TI's AM654 SoC. The PCIe controller in AM654
uses Synopsys core revision 4.90a and uses the same TI wrapper as used
in keystone2 with certain modification. Hence AM654 will use the same
pci wrapper driver pci-keystone.c
This series was initially part of [1]. This series onl
Explicitly set the PCIe mode to BOOTCFG_DEVCFG instead of always
relying on the default values. This is required when EP mode has to
be explicitly written to BOOTCFG_DEVCFG register.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/controller/dwc/pci-keystone.c | 37 +++
Add start_link/stop_link dw_pcie_ops and invoke ks_pcie_start_link
directly from host_init. start_link/stop_link ops is required for
adding EP mode support.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/controller/dwc/pci-keystone.c | 44 +++
1 file changed, 22 insert
No functional change. Move host specific platform_get_resource to
ks_add_pcie_port and the common platform_get_resource (applicable
to both host and endpoint) to probe. This is in preparation for
adding endpoint support to pci-keystone driver.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pc
Document "atu" reg-names required to get the register space for ATU in
Synopsys designware core version >= 4.80.
Signed-off-by: Kishon Vijay Abraham I
---
Documentation/devicetree/bindings/pci/designware-pcie.txt | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/Document
hook_fault_code is an ARM32 specific API for hooking into data abort.
Since pci-keystone.c will be used for AM65X platforms which is an
ARM64 platform, allow hook_fault_code to be compiled only for ARM32.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/controller/dwc/pci-keystone.c | 4 +++
SERDES connected to the PCIe controller in AM654 requires
power on reset enable (POR_EN) to be set in the SERDES. The
SERDES driver sets POR_EN in the reset ops and it has to be
invoked before init or enable ops. In order for SERDES driver
to set POR_EN, invoke phy_reset API in pci-keystone driver.
Synopsys designware version >= 4.80 uses a separate register space
for programming ATU. The current code identifies if there exists a
separate register space by accessing the register address of ATUs
in designware version < 4.80. Accessing this address results in
abort in the case of K2G.
Fix it h
PCIe in TI's AM654 devices is by default configured to work in GEN3 mode.
However PCIe doesn't work reliably in GEN3 mode because of SERDES
configuration.
Add support to set the link speed to GEN1, GEN2 or GEN3 based on
"max-link-speed" dt property with GEN2 as the default speed if
"max-link-speed
commit beb4641a787df79a ("PCI: dwc: Add MSI-X callbacks handler") while
adding MSI-X callback handler, introduced dw_pcie_ep_find_capability and
__dw_pcie_ep_find_next_cap for finding the MSI and MSIX capability.
However if MSI or MSIX capability is the last capability (i.e there are
no additional
Add const qualifier to struct dw_pcie_ep_ops member of
struct dw_pcie_ep.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/controller/dwc/pci-dra7xx.c | 2 +-
drivers/pci/controller/dwc/pcie-artpec6.c | 2 +-
drivers/pci/controller/dwc/pcie-designware-plat.c | 2 +-
driver
Modify pci_epf_alloc_space API to take alignment size as argument in
order to argument in order to allocate aligned buffers to be mapped to
BARs.
Add 'align' parameter to epc_features which can be used by platform
drivers to specifiy the BAR allocation alignment requirements and use
this while inv
Add devicetree binding documentation for PCIe in RC mode present in
AM654 SoC.
Signed-off-by: Kishon Vijay Abraham I
---
Documentation/devicetree/bindings/pci/pci-keystone.txt | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/pci/pci-keyst
commit 834b9051992580ac8fd3966d023b ("misc: pci_endpoint_test: Add support
for PCI_ENDPOINT_TEST regs to be mapped to any BAR") while adding
test_reg_bar in order to map PCI_ENDPOINT_TEST regs to be mapped to any
BAR failed to update test_reg_bar in pci_endpoint_test. This results in
test_reg_bar h
Configure RESBAR capability to advertise the smallest size (1MB) for
couple of reasons. A) Host side resource allocation of BAR fails for
larger sizes. B) Endpoint function driver does not allocate memory
for all supported sizes in RESBAR capability.
If and when there is a usecase required to add m
Certain platforms like TI's AM654 doesn't have separate address space for
dbi2 instead they are accessed using the same address space as dbi
with some configuration bit set. In order to support such platforms,
add callbacks for accessing dbi2 address space.
Signed-off-by: Kishon Vijay Abraham I
-
of_pci_get_max_link_speed() is built only if CONFIG_PCI is enabled.
Make of_pci_get_max_link_speed() to be also used by PCI Endpoint
controllers with just CONFIG_PCI_ENDPOINT enabled.
Signed-off-by: Kishon Vijay Abraham I
Signed-off-by: Sekhar Nori
---
drivers/pci/Makefile | 2 +-
drivers/pci/
Add PCIe EP support for AM654x Platforms in pci-keystone.c
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/controller/dwc/Kconfig| 23 +-
drivers/pci/controller/dwc/pci-keystone.c | 242 +++---
2 files changed, 236 insertions(+), 29 deletions(-)
diff --git a/drive
Certain platforms like K2G reguires the outbound ATU window to be
aligned. The alignment size is already present in mem->page_size.
Use the alignment size present in mem->page_size to configre a
aligned ATU window. In order to raise an interrupt, CPU has to write
to address offset from the start of
iatu_unroll_enabled flag is set only for Designware in host mode.
However iATU unroll can be applicable for endpoint mode too. Set
iatu_unroll_enabled flag in dw_pcie_setup which is common for
both host mode and endpoint mode.
Signed-off-by: Kishon Vijay Abraham I
---
.../pci/controller/dwc/pcie
TI's AM654x PCIe EP has a restriction that BAR_0 is mapped to
application registers. "PCIe Inbound Address Translation" section in
AM65x Sitara Processors TRM (SPRUID7 – April 2018) describes BAR0 is
reserved. Configure pci_endpoint_test to use BAR_2 instead.
Also set alignment to 64K since "PCIe S
Hi Michal & Marek,
I meet an issue that the DMA (CMA used) allocation failed if there is a user
signal, Eg Ctrl+C, it causes the USB xHCI stack fails to resume due to
dma_alloc_coherent
failed. It can be easy to reproduce if the user press Ctrl+C at
suspend/resume test.
Below is the call stack:
[
Add PCIe RC support for AM654x Platforms in pci-keystone.c
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/controller/dwc/Kconfig| 2 +-
drivers/pci/controller/dwc/pci-keystone.c | 161 --
2 files changed, 148 insertions(+), 15 deletions(-)
diff --git a/drive
Hello Martin,
On Sun, Mar 24, 2019 at 11:02:16PM +0100, Martin Blumenstingl wrote:
> Back in January a "BUG: scheduling while atomic" error showed up during
> boot on my Meson8b Odroid-C1 (which uses a PWM regulator as CPU supply).
> The call trace comes down to:
> __mutex_lock
> clk_prepare_l
Hi Aditya,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on tty/tty-testing]
[also build test WARNING on v5.1-rc2 next-20190325]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day
On Mon, 25 Mar 2019, Baoquan He wrote:
> On 03/25/19 at 08:53am, Borislav Petkov wrote:
> > On Mon, Mar 25, 2019 at 03:27:10PM +0800, Baoquan He wrote:
> > > Kexec kernel also need to get rsdp to get SRAT tables so that KASLR can
> > > avoid those hotpluggable regions in boot compression stage.
>
--
Goedendag,
Wij zijn Simple Federal Credit Union die leningen verstrekt per
postadvertentie. Wij bieden verschillende soorten leningen of projecten
leningen (korte en lange termijn leningen, persoonlijke leningen,
leningen aan bedrijven, enz.) Met 3% rente. dus als u financiële
Commit 0df977eafc79 ("powerpc/6xx: Don't use SPRN_SPRG2 for storing
stack pointer while in RTAS") changes the code to use a field in
thread struct to store the stack pointer while in RTAS instead of
using SPRN_SPRG2. It therefore converts all places which were
manipulating SPRN_SPRG2 to use that fi
On Mon, 25 Mar 2019, Gen Zhang wrote:
> Hi,
> I think I found a reproducible kernel bug in version 5.0.4.
> Source file: arch/x86/kernel/unwind_orc.c:505
Thanks for report, but please refrain from sending the same thing over and
over. It's not adding any value.
Thanks,
tglx
Hello,
On Sun, Mar 24, 2019 at 11:02:17PM +0100, Martin Blumenstingl wrote:
> Holding the spin-lock for all of the code in meson_pwm_apply() can
> result in a "BUG: scheduling while atomic". This can happen because
> clk_get_rate() (which is called from meson_pwm_calc()) may sleep.
> Only hold the
Hello,
On Mon, Mar 25, 2019 at 09:41:53AM +0100, Uwe Kleine-König wrote:
> If you want to implement further cleanups, my questions and propositions
> are:
>
> - Is there a publicly available manual for this hardware? If yes, you
>can add a link to it in the header of the driver.
>
> - Why
Ming,
On Mon, 25 Mar 2019, Ming Lei wrote:
> On Mon, Mar 25, 2019 at 01:02:13PM +0800, Peter Xu wrote:
> > One thing I can think of is the real-time scenario where "isolcpus="
> > is provided, then logically we should not allow any isolated CPUs to
> > be bound to any of the multi-queue IRQs. Tho
On Fri, 15 Mar 2019, Chang S. Bae wrote:
> GSBASE is used to find per-CPU data in the kernel.
It's not used to find per cpu data. per cpu data access is using GS based
addressing.
> But when it is unknown,
What is unknown?
> the per-CPU base can be found from the per_cpu_offset table with a CP
On 03/25/19 at 09:43am, Thomas Gleixner wrote:
> On Mon, 25 Mar 2019, Baoquan He wrote:
>
> > On 03/25/19 at 08:53am, Borislav Petkov wrote:
> > > On Mon, Mar 25, 2019 at 03:27:10PM +0800, Baoquan He wrote:
> > > > Kexec kernel also need to get rsdp to get SRAT tables so that KASLR can
> > > > avo
On 3/25/2019 1:26 PM, Lee Jones wrote:
On Fri, 22 Mar 2019, Kangjie Lu wrote:
Hi Lee Jones,
Can you review this patch?
Don't poke.
I have a very long list of reviews on my TODO. Poking only surfaces
your patch to the top of my Inbox, and since I review patches in
reverse chronological order
> -Original Message-
> From: linux-arm-kernel [mailto:linux-arm-kernel-boun...@lists.infradead.org]
> On Behalf Of Robin Murphy
> Sent: 21 March 2019 15:04
> To: Shameerali Kolothum Thodi ;
> lorenzo.pieral...@arm.com
> Cc: mark.rutl...@arm.com; vkil...@codeaurora.org;
> neil.m.lee...@gm
Hi Al, hi Linus,
On 03/25/2019 05:57 AM, Al Viro wrote:
> On Sun, Mar 24, 2019 at 06:23:24PM -0700, Linus Torvalds wrote:
>
>> Al, comments? At the very least, if we don't make
>> simple_symlink_inode_operations() do that, we should have a *big*
>> comment that if it's not part of the inode data,
Hi Aditya,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on tty/tty-testing]
[also build test WARNING on v5.1-rc2 next-20190325]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day
Hi Kangjie,
Am 24.03.19 um 23:43 schrieb Kangjie Lu:
> When kzalloc fails, "platform_state->inited = 1" is a NULL pointer
> dereference. The fix returns VCHIQ_ERROR in case it failed to
> avoid NULL pointer dereference.
>
> Signed-off-by: Kangjie Lu
please add a proper fixes tag.
> ---
> .../sta
This patch adds rv32_defconfig for 32bit systems. The only
difference between rv32_defconfig and defconfig is that
rv32_defconfig has CONFIG_ARCH_RV32I=y.
Signed-off-by: Anup Patel
---
arch/riscv/configs/rv32_defconfig | 84 +++
1 file changed, 84 insertions(+)
crea
This patchset primarily extends initial page table setup using fixmap
to boot Linux RISC-V kernel (64bit and 32bit) from any 4KB aligned address.
We also add 32bit defconfig to allow people to try 32bit Linux RISC-V
kernel as well.
The patchset is based on Linux-5.1-rc2 and tested on SiFive Unlea
Currently, the setup_bootmem() reserves memory from RAM start to the
kernel end. This prevents us from exploring ways to use the RAM below
(or before) the kernel start hence this patch updates setup_bootmem()
to only reserve memory from the kernel start to the kernel end.
Signed-off-by: Mike Rapop
The trampoline page table is redundant because:
1. There is no mapping in trampoling page table which is not covered
by swapper page table.
2. The relocate() in head.S will first load trampoline page table and
after that it will load swapper page table. Same thing can be achieved
by strai
Hi Vladislav,
we are almost there.
When submitting/applying a patch, we do run ./script/checkpatch.pl on
the final patch.
This gives us here 2 warnings (inlined below)
Also, can you versionize your submissions (use `-v` in git
format-patch: `git format-patch -v3 HEAD`).
On Sun, Mar 24, 2019 at
On Mon, 25 Mar 2019 03:53:41 +,
Qiang Zhao wrote:
>
> qeic_of_init just get device_node of qeic from dtb and call qe_ic_init,
> pass the device_node to qe_ic_init.
> So merge qeic_of_init into qe_ic_init to get the qeic node in
> qe_ic_init.
>
> Signed-off-by: Zhao Qiang
> ---
> drivers/ir
On Mon, 25 Mar 2019 03:53:37 +,
Qiang Zhao wrote:
>
> The codes of qe_ic init from a variety of platforms are redundant,
> merge them to a common function and put it to irqchip/irq-qeic.c
>
> For non-p1021_mds mpc85xx_mds boards, use "qe_ic_init(np, 0,
> qe_ic_cascade_low_mpic, qe_ic_cascade
On Wed, Mar 20, 2019 at 10:53 PM David Howells wrote:
>
> Signed-off-by: David Howells
> cc: Ilya Dryomov
> cc: "Yan, Zheng"
> cc: Sage Weil
> cc: ceph-de...@vger.kernel.org
> ---
>
> drivers/block/rbd.c | 362 +++-
> fs/ceph/cache.c |9 -
> fs
Currently, we have to boot RISCV64 kernel from a 2MB aligned physical
address and RISCV32 kernel from a 4MB aligned physical address. This
constraint is because initial pagetable setup (i.e. setup_vm()) maps
entire RAM using hugepages (i.e. 2MB for 3-level pagetable and 4MB for
2-level pagetable).
On Mon, 25 Mar 2019 03:53:48 +,
Qiang Zhao wrote:
>
> QEIC was supported on PowerPC, and dependent on PPC,
> Now it is supported on other platforms, so remove PPCisms.
>
> Signed-off-by: Zhao Qiang
> ---
> arch/powerpc/platforms/83xx/km83xx.c |1 -
> arch/powerpc/platforms/83x
Hi Finn,
On Tue, Mar 5, 2019 at 10:55 AM Finn Thain wrote:
> On Tue, 5 Mar 2019, Geert Uytterhoeven wrote:
> > On Tue, Mar 5, 2019 at 7:13 AM Finn Thain
> > wrote:
> > > On Sat, 1 Dec 2018, Finn Thain wrote:
> > > > This series removes "select ARCH_USES_GETTIMEOFFSET" from arch/m68k
> > > > and
On Fri, Mar 22, 2019 at 2:47 PM Thomas Preston
wrote:
>
> Add an example for the magic PRP0001 device ID which allows matching
> ACPI devices against drivers using OF Device Tree compatible property.
> It wasn't clear to me that PRP0001 could be used in _CID.
Mika, Andy, can you have a look at th
Each eTSEC MAC has its own TBI (SGMII) PCS and private MDIO bus.
But due to a DTS oversight, both SGMII-compatible MACs of the LS1021 SoC
are pointing towards the same internal PCS. Therefore nobody is
controlling the internal PCS of eTSEC0.
Upon initial ndo_open, the SGMII link is ok by virtue of
On Fri, Mar 22, 2019 at 01:48:11AM +, Anson Huang wrote:
> i.MX7ULP has TPM(Low Power Timer/Pulse Width Modulation Module)
> inside, it can support multiple PWM channels, all the channels
> share same counter and period setting, but each channel can
> configure its duty and polarity independent
On Sun, 2019-03-24 at 23:02 +0100, Martin Blumenstingl wrote:
> Back in January a "BUG: scheduling while atomic" error showed up during
> boot on my Meson8b Odroid-C1 (which uses a PWM regulator as CPU supply).
> The call trace comes down to:
> __mutex_lock
> clk_prepare_lock
> clk_core_get_r
On 22.03.19 20:06, Andy Shevchenko wrote:
> On Fri, Mar 22, 2019 at 07:32:28PM +0100, Enrico Weigelt, metux IT consult
> wrote:
>> On 21.03.19 10:23, Andy Shevchenko wrote:
>>
>>> ...and on top of that GPIO sysfs interface is deprecated.
>>
>> I don't like the idea of deprecating this. It might no
Hi,
On 25/03/19 2:04 PM, Kishon Vijay Abraham I wrote:
> Add PCIe RC support for TI's AM654 SoC. The PCIe controller in AM654
> uses Synopsys core revision 4.90a and uses the same TI wrapper as used
> in keystone2 with certain modification. Hence AM654 will use the same
> pci wrapper driver pci-ke
On Mon, Mar 25, 2019 at 03:22:23PM +0900, William Breathitt Gray wrote:
> +/**
> + * find_next_clump8 - find next 8-bit clump with set bits in a memory region
> + * @clump: location to store copy of found clump
> + * @addr: address to base the search on
> + * @offset: bit offset at which to start s
Add PCIe RC support for TI's AM654 SoC. The PCIe controller in AM654
uses Synopsys core revision 4.90a and uses the same TI wrapper as used
in keystone2 with certain modification. Hence AM654 will use the same
pci wrapper driver pci-keystone.c
This series was initially part of [1]. This series onl
Add "reg-names" binding information in order for device tree node
to be populated with the correct register strings. This will break
old dt compatibility. However Keystone PCI has never worked
in upstream kernel due to lack of SERDES support. Before SERDES
support is added, cleanup the Keystone PCI
pci-keystone driver uses irq_of_parse_and_map to get irq number of
error_irq. Use platform_get_irq instead and move platform_get_irq()
and request_irq() of error_irq from ks_pcie_add_pcie_port to ks_pcie_probe
since error_irq is common to both RC mode and EP mode.
Signed-off-by: Kishon Vijay Abrah
No functional change. Move host specific platform_get_resource to
ks_add_pcie_port and the common platform_get_resource (applicable
to both host and endpoint) to probe. This is in preparation for
adding endpoint support to pci-keystone driver.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pc
Explicitly set the PCIe mode to BOOTCFG_DEVCFG instead of always
relying on the default values. This is required when EP mode has to
be explicitly written to BOOTCFG_DEVCFG register.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/controller/dwc/pci-keystone.c | 37 +++
Use platform_get_resource_byname() instead of platform_get_resource() which
uses index to get memory resources. While at that get the memory resource
defined specifically for configuration space instead of deriving the
configuration space address from dbics address space. Since pci-keystone
driver
SERDES connected to the PCIe controller in AM654 requires
power on reset enable (POR_EN) to be set in the SERDES. The
SERDES driver sets POR_EN in the reset ops and it has to be
invoked before init or enable ops. In order for SERDES driver
to set POR_EN, invoke phy_reset API in pci-keystone driver.
Add PCIe RC support for AM654x Platforms in pci-keystone.c
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/controller/dwc/Kconfig| 2 +-
drivers/pci/controller/dwc/pci-keystone.c | 161 --
2 files changed, 148 insertions(+), 15 deletions(-)
diff --git a/drive
Add "ti,syscon-pcie-mode" dt-binding to hold phandle to the syscon
register that should be used to configure PCIe in RC mode or EP mode.
Signed-off-by: Kishon Vijay Abraham I
Reviewed-by: Rob Herring
---
Documentation/devicetree/bindings/pci/pci-keystone.txt | 2 ++
1 file changed, 2 insertions
No functional change. Instead of having two functions
ks_pcie_add_pcie_port and ks_pcie_dw_host_init for initializing host,
have a single function to perform all the host initialization.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/controller/dwc/pci-keystone.c | 63 +---
Add start_link/stop_link dw_pcie_ops and invoke ks_pcie_start_link
directly from host_init. start_link/stop_link ops is required for
adding EP mode support.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/controller/dwc/pci-keystone.c | 44 +++
1 file changed, 22 insert
Document "atu" reg-names required to get the register space for ATU in
Synopsys designware core version >= 4.80.
Signed-off-by: Kishon Vijay Abraham I
---
Documentation/devicetree/bindings/pci/designware-pcie.txt | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/Document
Synopsys designware version >= 4.80 uses a separate register space
for programming ATU. The current code identifies if there exists a
separate register space by accessing the register address of ATUs
in designware version < 4.80. Accessing this address results in
abort in the case of K2G.
Fix it h
hook_fault_code is an ARM32 specific API for hooking into data abort.
Since pci-keystone.c will be used for AM65X platforms which is an
ARM64 platform, allow hook_fault_code to be compiled only for ARM32.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/controller/dwc/pci-keystone.c | 4 +++
PCIe in TI's AM654 devices is by default configured to work in GEN3 mode.
However PCIe doesn't work reliably in GEN3 mode because of SERDES
configuration.
Add support to set the link speed to GEN1, GEN2 or GEN3 based on
"max-link-speed" dt property with GEN2 as the default speed if
"max-link-speed
Modify pci_epf_alloc_space API to take alignment size as argument in
order to argument in order to allocate aligned buffers to be mapped to
BARs.
Add 'align' parameter to epc_features which can be used by platform
drivers to specifiy the BAR allocation alignment requirements and use
this while inv
101 - 200 of 1175 matches
Mail list logo
