Best Regards!
Anson Huang
> -Original Message-
> From: Uwe Kleine-König [mailto:u.kleine-koe...@pengutronix.de]
> Sent: 2019年3月19日 14:55
> To: Anson Huang
> Cc: thierry.red...@gmail.com; robh...@kernel.org; mark.rutl...@arm.com;
> shawn...@kernel.org; s.ha...@pengutronix.de; ker...@peng
i.MX7ULP EVK board has MIPI-DSI display, its backlight is supplied by
TPM PWM module, this patch set enables i.MX7ULP TPM PWM driver support
and also add backlight support for MIPI-DSI display.
Anson Huang (5):
dt-bindings: pwm: Add i.MX TPM PWM binding
pwm: Add i.MX TPM PWM driver support
A
Add i.MX TPM(Low Power Timer/Pulse Width Modulation Module) PWM binding.
Signed-off-by: Anson Huang
---
Changes since V5:
- improve compatible string;
- change #pwm-cells to 3;
- "pwm" -> "PWM";
---
.../devicetree/bindings/pwm/imx-tpm-pwm.txt| 22 +
i.MX7ULP has TPM(Low Power Timer/Pulse Width Modulation Module)
inside, it can support multiple PWM channels, all the channels
share same counter and period setting, but each channel can
configure its duty and polarity independently.
There are several TPM modules in i.MX7ULP, the number of channel
Select CONFIG_PWM_IMX_TPM by default to support i.MX7ULP
TPM PWM.
Signed-off-by: Anson Huang
---
No changes.
---
arch/arm/configs/imx_v6_v7_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/imx_v6_v7_defconfig
b/arch/arm/configs/imx_v6_v7_defconfig
index 5586a50..57
Add i.MX7ULP EVK board PWM0 support.
Signed-off-by: Anson Huang
---
Changes since V5:
- change #pwm-cells to 3.
---
arch/arm/boot/dts/imx7ulp.dtsi | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/boot/dts/imx7ulp.dtsi b/arch/arm/boot/dts/imx7ulp.dtsi
index eb349fd
This patch adds i.MX7ULP EVK board MIPI-DSI backlight support.
Signed-off-by: Anson Huang
---
Changes since V5:
- change #pwm-cells to 3, add polarity settings.
---
arch/arm/boot/dts/imx7ulp-evk.dts | 21 +
1 file changed, 21 insertions(+)
diff --git a/arch/arm/boot/
Hi Peter,
On Tue, Mar 19, 2019 at 11:07:22AM +0800, Peter Xu wrote:
> Add a global sysctl knob "vm.unprivileged_userfaultfd" to control
> whether userfaultfd is allowed by unprivileged users. When this is
> set to zero, only privileged users (root user, or users with the
> CAP_SYS_PTRACE capabili
On 18. 03. 19 20:42, Stephen Boyd wrote:
> Quoting Michal Simek (2019-03-18 05:48:52)
>> On 05. 03. 19 0:27, Jolly Shah wrote:
>>> From: Rajan Vaja
>>>
>>> Zero divider is valid and default for some of ZynqMP
>>> clocks. Allow zero divisor when CLK_DIVIDER_ALLOW_ZERO
>>> for the clock is set.
>>>
On Tue, Mar 19, 2019 at 3:16 AM Uwe Kleine-König
wrote:
>
> Hello,
>
> [I put Thierry into To: because some remaining questions depend on his
> views]
>
> On Mon, Mar 18, 2019 at 05:17:14PM +0530, Yash Shah wrote:
> > Adds a PWM driver for PWM chip present in SiFive's HiFive Unleashed SoC.
> >
> >
If it is not in the default location compilation would fail at several points.
Signed-off-by: Rolf Eike Beer
---
Makefile | 4 +++-
tools/objtool/Makefile | 7 +--
2 files changed, 8 insertions(+), 3 deletions(-)
diff --git a/Makefile b/Makefile
index 9ef547fc7ffe..666b52c1c5f
Use regulator core's simplified DT parsing code to simply the driver
implementation.
Signed-off-by: Axel Lin
---
drivers/regulator/88pm8607.c | 43
1 file changed, 9 insertions(+), 34 deletions(-)
diff --git a/drivers/regulator/88pm8607.c b/drivers/regulator
clk_gate_ufs_subsys is a system bus clock, turning off it will
introduce lockup issue during system suspend flow. Let's mark
clk_gate_ufs_subsys as critical clock, thus keeps it on during
system suspend and resume.
Fixes: d374e6fd5088 ("clk: hisilicon: Add clock driver for hi3660 SoC")
Cc: sta...
Hi Faiz,
On 19/03/19 12:05 PM, Faiz Abbas wrote:
> Make sdhci_send_command() public so that it can be called from platform
> drivers.
This should be sdhci_finish_command here and also in subject
How about using "mmc: sdhci: Export sdhci_finish_command()"?
Thanks
Kishon
>
> Signed-off-by: Faiz A
Signed-off-by: Weiyi Lu
---
drivers/soc/mediatek/mtk-scpsys.c | 16
1 file changed, 4 insertions(+), 12 deletions(-)
diff --git a/drivers/soc/mediatek/mtk-scpsys.c
b/drivers/soc/mediatek/mtk-scpsys.c
index 5b24bb4bfbf6..9f52f501178b 100644
--- a/drivers/soc/mediatek/mtk-scpsys.
Resend scpsys patches from v4[1].
Based on v5.1-rc1 with MT8183 dts v9 patch[2] and
MT8183 SMI dt-binding v6 patch[3].
[1] https://patchwork.kernel.org/patch/10792071/
[2] https://patchwork.kernel.org/patch/10856987/
[3] https://patchwork.kernel.org/patch/10816827/
changes since v4:
- add propert
Add scpsys driver for MT8183
Signed-off-by: Weiyi Lu
---
drivers/soc/mediatek/mtk-scpsys.c | 226 ++
1 file changed, 226 insertions(+)
diff --git a/drivers/soc/mediatek/mtk-scpsys.c
b/drivers/soc/mediatek/mtk-scpsys.c
index 94c10f69655d..f1d82cdb219e 100644
--- a/dr
For some power domains like vpu_core on MT8183 whose sram need to
do clock and internal isolation while power on/off sram.
We add a flag "sram_iso_ctrl" in scp_domain_data to judge if we
need to do the extra sram isolation control or not.
Signed-off-by: Weiyi Lu
---
drivers/soc/mediatek/mtk-scps
Add subsys CG control flow before/after the bus protect control
due to bus protection need SMI bus relative CGs enabled to feedback
its ack.
Signed-off-by: Weiyi Lu
---
drivers/soc/mediatek/mtk-scpsys.c | 72 ++-
1 file changed, 70 insertions(+), 2 deletions(-)
diff
Try to stop extending the clk_id or clk_names if there are
more and more new BASIC clocks. To get its own clocks by the
basic_clk_name of each power domain.
Signed-off-by: Weiyi Lu
---
drivers/soc/mediatek/mtk-scpsys.c | 27 +++
1 file changed, 19 insertions(+), 8 deletio
Put sram enable and disable control in separate functions.
Signed-off-by: Weiyi Lu
---
drivers/soc/mediatek/mtk-scpsys.c | 79 ---
1 file changed, 51 insertions(+), 28 deletions(-)
diff --git a/drivers/soc/mediatek/mtk-scpsys.c
b/drivers/soc/mediatek/mtk-scpsys.c
in
Use USEC_PER_SEC to indicate the polling timeout directly.
And add documentation of scp_domain_data.
Signed-off-by: Weiyi Lu
---
drivers/soc/mediatek/mtk-scpsys.c | 14 +-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/drivers/soc/mediatek/mtk-scpsys.c
b/drivers/soc/m
Put bus protection enable and disable control in separate functions.
Signed-off-by: Weiyi Lu
---
drivers/soc/mediatek/mtk-scpsys.c | 48 ++-
1 file changed, 34 insertions(+), 14 deletions(-)
diff --git a/drivers/soc/mediatek/mtk-scpsys.c
b/drivers/soc/mediatek/mtk-s
Put clock enable and disable control in separate function.
Signed-off-by: Weiyi Lu
---
drivers/soc/mediatek/mtk-scpsys.c | 49 ---
1 file changed, 32 insertions(+), 17 deletions(-)
diff --git a/drivers/soc/mediatek/mtk-scpsys.c
b/drivers/soc/mediatek/mtk-scpsys.c
in
Put regulator enable and disable control in separate functions.
Signed-off-by: Weiyi Lu
---
drivers/soc/mediatek/mtk-scpsys.c | 32 ++-
1 file changed, 23 insertions(+), 9 deletions(-)
diff --git a/drivers/soc/mediatek/mtk-scpsys.c
b/drivers/soc/mediatek/mtk-scpsys.
Add power dt-bindings of MT8183 and introduces "BASIC" and
"SUBSYS" clock types in binding document.
The "BASIC" type is compatible to the original power control with
clock name [a-z]+[0-9]*, e.g. mm, vpu1.
The "SUBSYS" type is used for bus protection control with clock
name [a-z]+-[0-9]+, e.g. isp
For scpsys driver using regmap based syscon driver API.
Signed-off-by: Weiyi Lu
---
.../bindings/memory-controllers/mediatek,smi-common.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt
b
Add power controller node and smi-common node for MT8183
In scpsys node, it contains clocks and regmapping of
infracfg and smi-common for bus protection.
Signed-off-by: Weiyi Lu
---
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 62
1 file changed, 62 insertions(+)
diff --g
Both MT8183 & MT6765 have more control steps of bus protection
than previous project. And there add more bus protection registers
reside at infracfg & smi-common. Also add new APIs for multiple
step bus protection control with more customize arguments.
Signed-off-by: Weiyi Lu
---
drivers/soc/med
On Tue, Mar 19, 2019 at 06:50:12AM +, Anson Huang wrote:
> i.MX7ULP has TPM(Low Power Timer/Pulse Width Modulation Module)
> inside, it can support multiple PWM channels, all the channels
> share same counter and period setting, but each channel can
> configure its duty and polarity independent
Hi Kishon,
On 19/03/19 1:28 PM, Kishon Vijay Abraham I wrote:
> Hi Faiz,
>
> On 19/03/19 12:05 PM, Faiz Abbas wrote:
>> Make sdhci_send_command() public so that it can be called from platform
>> drivers.
>
> This should be sdhci_finish_command here and also in subject
> How about using "mmc: sdh
Hi Faiz,
On 19/03/19 12:05 PM, Faiz Abbas wrote:
> commit 5b0d62108b46 ("mmc: sdhci-omap: Add platform specific reset
> callback") skips data resets during tuning operation. Because of this,
> a data error or data finish interrupt might still arrive after a command
> error has been handled and the
On Tue, Mar 19, 2019 at 12:52:12PM +0530, Yash Shah wrote:
> On Tue, Mar 19, 2019 at 3:16 AM Uwe Kleine-König
> wrote:
> > On Mon, Mar 18, 2019 at 05:17:14PM +0530, Yash Shah wrote:
> > > + val = PWM_SIFIVE_PWMCFG_EN_ALWAYS |
> > > + FIELD_PREP(PWM_SIFIVE_PWMCFG_SCALE, scale);
> > >
On Mon, Mar 18, 2019 at 3:09 PM Sergey Senozhatsky
wrote:
>
> On (03/18/19 14:42), Dmitry Vyukov wrote:
> > > There is also SYSLOG_ACTION_CONSOLE_OFF, which disables logging.
> >
> > That one I somehow figured earlier, here is the exact check:
> > https://github.com/google/syzkaller/blob/61f9c92f3
CET - Control-flow Enforcement Technology, it's used to
protect against return/jump oriented programming (ROP)
attacks. It provides the following capabilities to defend
against ROP/JOP style control-flow subversion attacks:
- Shadow Stack (SHSTK):
A second stack for the program tha
Control-flow Enforcement Technology (CET) provides protection against
return/jump-oriented programming (ROP) attacks. To make kvm Guest OS own
the capability, this patch-set is required. It enables CET related CPUID
report, xsaves/xrstors, vmx entry configuration etc. for Guest OS.
PATCH 1: De
From: Sean Christopherson
A handful of CET MSRs are not context switched through "traditional"
methods, e.g. VMCS or manual switching, but rather are passed through
to the guest and are saved and restored by XSAVES/XRSTORS, i.e. the
guest's FPU state.
Load the guest's FPU state if userspace is a
The CET runtime settings, i.e., CET state control bits(IA32_U_CET/
IA32_S_CET), CET SSP(IA32_PL3_SSP/IA32_PL0_SSP) and SSP table address
(IA32_INTERRUPT_SSP_TABLE_ADDR) are task/thread specific, therefore,
OS needs to save/restore the states properly during context switch,
e.g., task/thread switchi
Now that KVM supports setting CET related bits.
Previously, KVM did not support setting any bits in XSS
and so hardcoded its check to inject a #GP if Guest
attempted to write a non-zero value to IA32_XSS.
Signed-off-by: Zhang Yi Z
Signed-off-by: Yang Weijiang
---
arch/x86/include/asm/kvm_host.h
According to latest Software Development Manual vol.2/3.2,
for CPUID.(EAX=0xD,ECX=1), it should report xsaves area size
containing all states enabled by XCR0|IA32_MSR_XSS.
Signed-off-by: Zhang Yi Z
Signed-off-by: Yang Weijiang
---
arch/x86/kvm/cpuid.c | 3 ++-
1 file changed, 2 insertions(+),
"Load Guest CET state" bit controls whether guest CET states
will be loaded at Guest entry. Before doing that, KVM needs
to check if CPU CET feature is available.
Signed-off-by: Zhang Yi Z
Signed-off-by: Yang Weijiang
---
arch/x86/kvm/vmx.c | 18 ++
1 file changed, 18 insertions
When VMExit occurs, the Guest CET MSRs are stored in two different
places, U_CET/PL0_SSP/PL1_SSP/PL2_SSP/PL3_SSP are stored in fpu
xsave area, they are operated by XSAVES/XRSTORS, so before access
these MSRs, kvm_load_guest_fpu is required to restore them to Host MSRs.
After finish operation, need
CET SHSTK and IBT capability are reported via
CPUID.(EAX=7, ECX=0):ECX[bit 7] and EDX[bit 20] respectively.
CR4.CET[bit 23] is CET master enable bit, it controls CET feature
enabling. CET user mode and supervisor mode xsaves component size
is reported via CPUID.(EAX=0xD, ECX=1):ECX[bit 11] and ECX[
On Tue, Mar 19, 2019 at 07:09:56AM +, Anson Huang wrote:
> i.MX7ULP EVK board has MIPI-DSI display, its backlight is supplied by
> TPM PWM module, this patch set enables i.MX7ULP TPM PWM driver support
> and also add backlight support for MIPI-DSI display.
Given that you actually changed somet
CONFIG_RETPOLINE has severely degraded indirect function call
performance, so it's worth putting some effort into reducing
the number of times cmp() is called.
This patch avoids badly unbalanced merges on unlucky input sizes.
It slightly increases the code size, but saves an average of 0.2*n
calls
This uses fewer comparisons than the previous code (approaching half
as many for large random inputs), but produces identical results;
it actually performs the exact same series of swap operations.
Specifically, it reduces the average number of compares from
2*n*log2(n) - 3*n + o(n) to n*log2(n)
Rather than a fixed-size array of pending sorted runs, use the ->prev
links to keep track of things. This reduces stack usage, eliminates
some ugly overflow handling, and reduces the code size.
Also:
* merge() no longer needs to handle NULL inputs, so simplify.
* The same applies to merge_and_res
Rather than having special-case swap functions for 4- and 8-byte objects,
special-case aligned multiples of 4 or 8 bytes. This speeds up most
users of sort() by avoiding fallback to the byte copy loop.
Despite what commit ca96ab859ab4 ("lib/sort: Add 64 bit swap function")
claims, very few users
There are 8 parents, use 0x7
Fixes: 085a4ea93d54 ("clk: meson: g12a: add peripheral clock controller")
Signed-off-by: Maxime Jourdan
---
drivers/clk/meson/g12a.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c
index cfb9
(Resend because earlier send had GIT_AUTHOR_DATE in the e-mail
headers and got filed with last month's archives. And probably
tripped a few spam filters.)
v1->v2: Various spelling, naming and code style cleanups.
Generally positive and no negative responses to the
goals and algori
Similar to what's being done in the net code, this takes advantage of
the fact that most invocations use only a few common swap functions, and
replaces indirect calls to them with (highly predictable) conditional
branches. (The downside, of course, is that if you *do* use a custom
swap function, t
Stephen,
Thanks for the review
On 18/03/2019 at 20:54, Stephen Boyd wrote:
> Quoting Nicolas Ferre (2019-03-18 03:50:45)
>> From: Matthias Wieloch
>>
>> The prescaler formula of the programmable clock has changed for sama5d2.
>> Update
>> the driver accordingly.
>>
>> Fixes: a2038077de9a ("clk:
On 18/03/2019 21:13, Martin Blumenstingl wrote:
> Hi Neil,
>
> On Mon, Mar 18, 2019 at 11:06 AM Neil Armstrong
> wrote:
>>
>> From: Guillaume La Roque
>>
>> Add system regulators for the X96 Max Set-Top-Box.
>>
>> Still missing
>> * VDD_EE (0.8V - PWM controlled)
>> * VDD_CPU (PWM controlled)
>
On 19/03/2019 09:26, Maxime Jourdan wrote:
> There are 8 parents, use 0x7
>
> Fixes: 085a4ea93d54 ("clk: meson: g12a: add peripheral clock controller")
> Signed-off-by: Maxime Jourdan
> ---
> drivers/clk/meson/g12a.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/d
On Mon 18-03-19 11:27:12, Kees Cook wrote:
> On Wed, Mar 13, 2019 at 8:47 AM Jan Kara wrote:
> >
> > On Wed 13-03-19 08:35:33, Kees Cook wrote:
> > > On Wed, Mar 13, 2019 at 7:35 AM Jan Kara wrote:
> > > > On Tue 12-03-19 23:26:22, Kees Cook wrote:
> > > > > On Mon, Mar 11, 2019 at 1:42 PM syzbot
On Tue 19-03-19 02:36:59, Jann Horn wrote:
> When dev_exception_add() returns an error (due to a failed memory
> allocation), make sure that we move the RCU preemption count back to where
> it was before we were called. We dropped the RCU read lock inside the loop
> body, so we can't just "break".
On Mon 18-03-19 19:42:37, Alexander Lochmann wrote:
> We used LockDoc to derive locking rules for each member
> of struct transaction_t.
> Based on those results, we extended the existing documentation
> by more members of struct inode, and updated the existing
> documentation.
>
> Signed-off-by:
Hello
how are you today? My name is Lina i am 25 years old, i am a girl. I
saw your profile and i am really interesting about you and i hope to
talk with you of course if you would like too. But I do have the mind
that you could be a nice person is my believe and there are respectful
people out th
On Mär 19 2019, Masahiro Yamada wrote:
> How about this patch?
> https://patchwork.kernel.org/patch/10858809/
Thanks, this makes it work again.
Andreas.
--
Andreas Schwab, SUSE Labs, sch...@suse.de
GPG Key fingerprint = 0196 BAD8 1CE9 1970 F4BE 1748 E4D4 88E3 0EEA B9D7
"And now for something
On 18/03/2019 21:02, Martin Blumenstingl wrote:
> Hi Neil,
>
> On Mon, Mar 18, 2019 at 10:59 AM Neil Armstrong
> wrote:
>>
>> Add nodes and properties for the AO Clocks and Resets.
>>
>> Signed-off-by: Neil Armstrong
>> Signed-off-by: Jerome Brunet
>> ---
>> arch/arm64/boot/dts/amlogic/meson-
On Tue, 19 Mar 2019 at 01:38, Shawn Lin wrote:
>
>
> On 2019/3/19 6:50, kernelci.org bot wrote:
> > * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
> > * This automated bisection report was sent to you on the basis *
> > * that you may be involved with the breaking commit it has
Mostly like meson-gx, except that the VDEC_HEVC clock is now split in two:
HEVC and HEVCF.
Signed-off-by: Maxime Jourdan
---
drivers/clk/meson/g12a.c | 160 +++
drivers/clk/meson/g12a.h | 8 +-
2 files changed, 167 insertions(+), 1 deletion(-)
diff --git a/
As to not conflict with the IDs, this patch series is based on Neil's
last unmerged patch series: "clk: meson: add support for PCIE PLL"
Clocks are mostly the same as meson-gx, except for VDEC_HEVC which is
now split in two, HEVC and HEVCF.
Maxime Jourdan (2):
dt-bindings: clk: g12a-clkc: add V
Expose the three clocks related to the video decoder.
Signed-off-by: Maxime Jourdan
---
include/dt-bindings/clock/g12a-clkc.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/include/dt-bindings/clock/g12a-clkc.h
b/include/dt-bindings/clock/g12a-clkc.h
index 30303728fe09..82c9e0c020b2 100
On Mon 18-03-19 21:59:49, Aditya Pakki wrote:
> load_nls may fail and return an error message. The patch checks
> for such a scenario and passes the error upstream.
>
> Signed-off-by: Aditya Pakki
Thanks for the patch! But there's other code handling nls_map in
udf_fill_super() which takes care
Hi Kangjie,
Thank you for the patch! Perhaps something to improve:
url:
https://github.com/0day-ci/linux/commits/Kangjie-Lu/fs-affs-fix-a-NULL-pointer-dereference/20190314-170334
New smatch warnings:
fs/affs/file.c:951 affs_truncate() error: we previously assumed 'ext_bh' could
be null (see
Masahiro Yamada wrote:
> How about this patch?
> https://patchwork.kernel.org/patch/10858809/
>
> I hope you will be able to wrap the top Makefile again.
That works for me.
Tested-by: David Howells
Hi,
Best Regards!
Anson Huang
> -Original Message-
> From: Uwe Kleine-König [mailto:u.kleine-koe...@pengutronix.de]
> Sent: 2019年3月19日 16:04
> To: Anson Huang
> Cc: thierry.red...@gmail.com; robh...@kernel.org; mark.rutl...@arm.com;
> shawn...@kernel.org; s.ha...@pengutronix.de; ker...@p
Hi Michael,
as it seems good now, could you pick up this patch for merging?
Thanks,
Laurent
On 13/03/2019 11:25, Laurent Vivier wrote:
> resize_hpt_for_hotplug() reports a warning when it cannot
> resize the hash page table ("Unable to resize hash page
> table to target order") but in some cases
On Tue, 2019-03-19 at 09:50 +0100, Maxime Jourdan wrote:
A complete sentence would have been nice ;)
Add the video decoder clocks which are ...
> Mostly like meson-gx, except that the VDEC_HEVC clock is now split in two:
> HEVC and HEVCF.
>
> Signed-off-by: Maxime Jourdan
> ---
> drivers/clk/
On Wed, 2019-03-13 at 14:55 +0100, Neil Armstrong wrote:
> First two VPU clock parents are wrong, fix it here.
>
> Fixes: 085a4ea93d54 ("clk: meson: g12a: add peripheral clock controller")
> Signed-off-by: Neil Armstrong
> ---
> drivers/clk/meson/g12a.c | 2 +-
> 1 file changed, 1 insertion(+),
Hi,
Best Regards!
Anson Huang
> -Original Message-
> From: Uwe Kleine-König [mailto:u.kleine-koe...@pengutronix.de]
> Sent: 2019年3月19日 16:15
> To: Anson Huang
> Cc: thierry.red...@gmail.com; robh...@kernel.org; mark.rutl...@arm.com;
> shawn...@kernel.org; s.ha...@pengutronix.de; ker...@p
Web Admin Notificación de correo electrónico
Este mensaje se envía desde nuestro centro de mensajería de Web Admin a todos
los propietarios de nuestras cuentas de correo electrónico. Estamos eliminando
el acceso a todos nuestros clientes de correo web, su cuenta de correo
electrónico se actua
Add DT nodes for
- Two xHCI host controllers
- Two BDC Broadcom USB device controller
- Five USB PHY controllers
[xHCI0] [BDC0][xHCI1][BDC1]
| | | |
--- ---
|
These patches add Stingray USB PHY driver and its corresponding
DT nodes with documentation.
This patch set is based on Linux-5.0-rc2.
Changes from v5:
- Removed redundant address and size cells in DT nodes.
Changes from v4:
- Addressed Rob Herring review comments
- Removed child nodes
Web Admin Notificación de correo electrónico
Este mensaje se envía desde nuestro centro de mensajería de Web Admin a todos
los propietarios de nuestras cuentas de correo electrónico. Estamos eliminando
el acceso a todos nuestros clientes de correo web, su cuenta de correo
electrónico se actua
Add DT binding document for Stingray USB PHY.
Signed-off-by: Srinath Mannam
Reviewed-by: Rob Herring
---
.../bindings/phy/brcm,stingray-usb-phy.txt | 32 ++
1 file changed, 32 insertions(+)
create mode 100644
Documentation/devicetree/bindings/phy/brcm,stingray-usb-
USB PHY driver supports two types of stingray USB PHYs
- Type 1 is a combo PHY contains two PHYs, one SS and one HS.
- Type 2 is a single HS PHY.
These two PHY versons support both Generic xHCI host controller driver
and BDC Broadcom device controller driver.
Signed-off-by: Srinath Mannam
---
On 19/03/2019 08:28:40+, Nicolas Ferre wrote:
> > Ok. I can apply this clk-fixes. I presume that things are real bad and
> > it can't wait until v5.2?
>
> To be perfectly clear, it's not a regression.
> But as we're at the very beginning of the '-rc' phase and as it's a bug,
> I was thinking
On Fri, 2019-03-15 at 10:16 -0700, Stephen Boyd wrote:
> Quoting Jerome Brunet (2019-03-15 03:01:53)
> > On Tue, 2019-02-26 at 14:34 -0800, Stephen Boyd wrote:
> > > ---
> > > drivers/clk/clk.c| 260 ++-
> > > include/linux/clk-provider.h | 19 +++
> > >
On Tue, Mar 19, 2019 at 12:04:01AM -0400, Kimberly Brown wrote:
> There are two methods for signaling the host: the monitor page mechanism
> and hypercalls. The monitor page mechanism is used by performance
> critical channels (storage, networking, etc.) because it provides
> improved throughput. H
clk_gate_ufs_subsys is a system bus clock, turning off it will
introduce lockup issue during system suspend flow. Let's mark
clk_gate_ufs_subsys as critical clock, thus keeps it on during
system suspend and resume.
Fixes: d374e6fd5088 ("clk: hisilicon: Add clock driver for hi3660 SoC")
Cc: sta...
On Sun, Mar 17, 2019 at 07:31:08PM +0100, Emanuel Bennici wrote:
> The `case INTEl_WIDI_WK_CID`-Statement in Function `u8 rtw_drvextra_cmd_hdl`
> wouldn't be used because of CONFIG_INTEL_WIDI.
>
> Signed-off-by: Emanuel Bennici
> ---
> drivers/staging/rtl8723bs/core/rtw_cmd.c | 5 -
> 1 file
Hi Jerome,
On Tue, Mar 19, 2019 at 10:09 AM Jerome Brunet wrote:
>
> On Tue, 2019-03-19 at 09:50 +0100, Maxime Jourdan wrote:
>
> A complete sentence would have been nice ;)
>
> Add the video decoder clocks which are ...
>
Sorry about that, I'll apply myself in the future.
> > Mostly like meson-
A NULL pointer dereference bug was reported on a distribution kernel but
the same issue should be present on mainline kernel. It occured on s390
but should not be arch-specific. A partial oops looks like
[775277.408564] Unable to handle kernel pointer dereference in virtual kernel
address space
Hi all,
On Tue, Mar 19, 2019 at 03:52:06PM +0800, Leo Yan wrote:
> clk_gate_ufs_subsys is a system bus clock, turning off it will
> introduce lockup issue during system suspend flow. Let's mark
> clk_gate_ufs_subsys as critical clock, thus keeps it on during
> system suspend and resume.
Sorry fo
On Mon, 2019-03-04 at 14:11 +0100, Neil Armstrong wrote:
> Add the Amlogic G12A Family CPU Clock tree in read/only for now.
>
> The CPU clock can either use the SYS_PLL for > 1GHz frequencies or
> use a couple of div+mux from 1GHz/667MHz/24MHz source with 2 non-glitch
> muxes.
>
> Proper DVFS sup
On 15/03/2019 19:15, Halil Pasic wrote:
On Wed, 13 Mar 2019 17:05:01 +0100
Pierre Morel wrote:
When the mediated device is open we setup the relation with KVM unset it
when the mediated device is released.
We ensure KVM is present on opening of the mediated device.
We ensure that KVM survive
"Yan, Zheng" writes:
> On Tue, Mar 19, 2019 at 12:22 AM Luis Henriques wrote:
>>
>> "Yan, Zheng" writes:
>>
>> > On Mon, Mar 18, 2019 at 6:33 PM Luis Henriques wrote:
>> >>
>> >> "Yan, Zheng" writes:
>> >>
>> >> > On Fri, Mar 15, 2019 at 7:13 PM Luis Henriques
>> >> > wrote:
>> >> >>
>> >>
On Mon, 2019-03-04 at 14:11 +0100, Neil Armstrong wrote:
> This patchset adds support for the clock tree feeding the 4xCortex A53
> cpu cluster.
>
> This patchet does not handle clock changing, this will be added in a
> secondary patchset.
>
> The CPU clock can either use the SYS_PLL for > 1GHz f
Improve the speed of the loop jumping to the next
available register
Signed-off-by: Lucas Tanure
---
drivers/base/regmap/regmap-debugfs.c | 27 ---
1 file changed, 24 insertions(+), 3 deletions(-)
diff --git a/drivers/base/regmap/regmap-debugfs.c
b/drivers/base/regmap/r
Signed-off-by: Lucas Tanure
---
drivers/base/regmap/regmap-debugfs.c | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/drivers/base/regmap/regmap-debugfs.c
b/drivers/base/regmap/regmap-debugfs.c
index 6d3dc1429ae57..9b3f49ffc4a5f 100644
--- a/drivers/base/regmap/regmap-debu
On Tue, Mar 19, 2019 at 6:50 AM Viresh Kumar wrote:
>
> On 18-03-19, 12:49, Rafael J. Wysocki wrote:
> > To summarize, I think that it would be sufficient to do this just for
> > policy->cpu and, as Peter said, warn once if there are more CPUs in
> > the policy or policy->cpu is not the CPU runnin
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On Thu, 2019-03-07 at 15:14 +0100, Neil Armstrong wrote:
> Add the PCIe reference clock feeding the USB3 + PCIE combo PHY.
>
> This PLL needs a very precise register sequence to permit to be locked,
> thus using the specific clk-pll pcie ops.
>
> The PLL is then followed by :
> - a fixed /2 divid
On 15/03/2019 15:10, Pierre Morel wrote:
On 15/03/2019 14:26, Pierre Morel wrote:
On 15/03/2019 11:20, Cornelia Huck wrote:
On Wed, 13 Mar 2019 17:04:58 +0100
Pierre Morel wrote:
+/*
+ * handle_pqap: Handling pqap interception
+ * @vcpu: the vcpu having issue the pqap instruction
+ *
+ * We
On 19/03/2019 10:55, Jerome Brunet wrote:
> On Thu, 2019-03-07 at 15:14 +0100, Neil Armstrong wrote:
>> Add the PCIe reference clock feeding the USB3 + PCIE combo PHY.
>>
>> This PLL needs a very precise register sequence to permit to be locked,
>> thus using the specific clk-pll pcie ops.
>>
>> Th
On 14-Feb 07:48, Tejun Heo wrote:
> Hello,
Hi Tejun,
> On Fri, Feb 08, 2019 at 10:05:50AM +, Patrick Bellasi wrote:
> > a) are available only for non-root nodes, both on default and legacy
> >hierarchies, while system wide clamps are defined by a generic
> >interface which does not de
On Thu, 2019-03-07 at 15:14 +0100, Neil Armstrong wrote:
> The Amlogic G12A SoCs embeds a dedicated PLL to feed the USB3+PCIE
> Combo PHY. This PLL needs a very specific and strict register sequence
> in order to correcly enable it and deliver the 100MHz reference clock
> to the Analog PHY.
>
> Af
On 15/03/2019 18:28, Halil Pasic wrote:
On Fri, 15 Mar 2019 14:26:34 +0100
Pierre Morel wrote:
On 15/03/2019 11:20, Cornelia Huck wrote:
On Wed, 13 Mar 2019 17:04:58 +0100
Pierre Morel wrote:
+/*
+ * handle_pqap: Handling pqap interception
+ * @vcpu: the vcpu having issue the pqap instruct
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