Commit-ID: 6f568ebe2afefdc33a6fb06ef20a94f8b96455f1
Gitweb: https://git.kernel.org/tip/6f568ebe2afefdc33a6fb06ef20a94f8b96455f1
Author: Davidlohr Bueso
AuthorDate: Wed, 6 Feb 2019 10:56:02 -0800
Committer: Thomas Gleixner
CommitDate: Fri, 8 Feb 2019 13:00:35 +0100
futex: Fix barrier co
Commit-ID: 1a1fb985f2e2b85ec0d3dc2e519ee48389ec2434
Gitweb: https://git.kernel.org/tip/1a1fb985f2e2b85ec0d3dc2e519ee48389ec2434
Author: Thomas Gleixner
AuthorDate: Tue, 29 Jan 2019 23:15:12 +0100
Committer: Thomas Gleixner
CommitDate: Fri, 8 Feb 2019 13:00:36 +0100
futex: Handle early
On 2/8/19 6:14 AM, Jarkko Sakkinen wrote:
On Thu, Feb 07, 2019 at 08:51:15PM -0500, Stefan Berger wrote:
+ rc = 0;
if (chip->flags & TPM_CHIP_FLAG_IRQ)
goto out_recv;
What why?
This fix seems to only be necessary when bisecting. You may want to apply
it!
I don't want to
syzbot has found a reproducer for the following crash on:
HEAD commit:ec7fd009e87c Merge branch 'ipv6-fixes'
git tree: net
console output: https://syzkaller.appspot.com/x/log.txt?x=17fc3d9740
kernel config: https://syzkaller.appspot.com/x/.config?x=2e0064f906afee10
dashboard link:
All is needed in a kernel module to make it unremovable without a
reboot is a single line of code. This should not be possible IMHO.
#include/* Needed by all modules */
#include/* Needed for KERN_INFO */
int init_module(void)
{
printk(KERN_INFO "Hello world.\n");
T
On Mon, Feb 04, 2019 at 10:32:44PM +0200, Oded Gabbay wrote:
> +int hl_cb_ioctl(struct hl_fpriv *hpriv, void *data)
> +{
> + union hl_cb_args *args = data;
> + struct hl_device *hdev = hpriv->hdev;
> + u64 handle;
> + int rc;
> +
> + switch (args->in.op) {
> + case HL_CB_OP_
On 04/02/19 10:47 PM, Bartosz Golaszewski wrote:
> +static const struct davinci_timer_cfg da850_timer_cfg = {
> + .reg = {
> + .start = DA8XX_TIMER64P0_BASE,
> + .end= DA8XX_TIMER64P0_BASE + SZ_4K,
SZ_4K - 1
This should have prevented watchdog time
On Thu, Feb 7, 2019 at 10:24 AM wrote:
> From: Claudiu Beznea
>
> This series adds drive strenght and slew rate support for SAMX60's pin
> controller. For drive strenght we could have 2 values: low, high.
> For slew rate we could have 2 values: enable, disabled.
>
> Besides this I took the chanc
On Thu, Feb 07, 2019 at 10:40:21AM -0800, Luck, Tony wrote:
> Tried it out and it works!
Excellent, find below a proper patch!
---
Subject: x86/mm/cpa: Fix set_mce_nospec()
In commit:
fe0937b24ff5 ("x86/mm/cpa: Fold cpa_flush_range() and cpa_flush_array()
into a single cpa_flu
On Thu, Jan 31, 2019 at 6:39 PM Bjorn Andersson
wrote:
> The UFS_RESET macro serves no purpose on QCS404, remove it.
>
> Signed-off-by: Bjorn Andersson
Patch applied.
Yours,
Linus Walleij
On Fri, Feb 08, 2019 at 01:03:10PM +0100, Rafael J. Wysocki wrote:
> On Fri, Feb 8, 2019 at 12:39 PM Sudeep Holla wrote:
> >
> > On Fri, Feb 08, 2019 at 11:42:20AM +0100, Rafael J. Wysocki wrote:
> > > On Fri, Feb 8, 2019 at 11:31 AM Viresh Kumar
> > > wrote:
> > > >
> > > > On 08-02-19, 11:22,
On Fri, Feb 8, 2019 at 1:04 PM Marek Szyprowski
wrote:
>
> Hi Sudeep,
>
> On 2019-02-08 12:51, Sudeep Holla wrote:
> > On Fri, Feb 08, 2019 at 12:47:06PM +0100, Marek Szyprowski wrote:
> >> On 2019-02-08 12:00, Sudeep Holla wrote:
> >>> On Thu, Feb 07, 2019 at 01:22:25PM +0100, Marek Szyprowski wr
On Tue, Dec 04, 2018 at 02:27:32PM +0100, Stefan Agner wrote:
> The custom fault handler is currently only meant to handle kernel
> mode bus faults. Exit in case the abort happened in user mode.
>
> Signed-off-by: Stefan Agner
> ---
> drivers/pci/controller/dwc/pci-imx6.c | 10 --
> 1 fi
On Mon, Feb 04, 2019 at 10:32:48PM +0200, Oded Gabbay wrote:
> This patch add the sysfs and hwmon entries that are exposed by the driver.
>
> Goya has several sensors, from various categories such as temperature,
> voltage, current, etc. The driver exposes those sensors in the standard
> hwmon mec
On Tue, Feb 5, 2019 at 10:12 AM Bartosz Golaszewski wrote:
> From: Bartosz Golaszewski
>
> Add a DT binding document for max77650 ultra-low power PMIC. This
> describes the core mfd device and the GPIO module.
>
> Signed-off-by: Bartosz Golaszewski
This is a good solution!
Reviewed-by: Linus
On Mon, Feb 04, 2019 at 10:32:53PM +0200, Oded Gabbay wrote:
> +int __init hl_debugfs_init(void)
> +{
> + hl_debug_root = debugfs_create_dir("habanalabs", NULL);
> + if (IS_ERR_OR_NULL(hl_debug_root)) {
> + pr_err("can not create debugfs directory\n");
> + hl_debug_r
On Fri, Feb 08, 2019 at 01:04:18PM +0100, Marek Szyprowski wrote:
> Hi Sudeep,
>
> On 2019-02-08 12:51, Sudeep Holla wrote:
> > On Fri, Feb 08, 2019 at 12:47:06PM +0100, Marek Szyprowski wrote:
> >> On 2019-02-08 12:00, Sudeep Holla wrote:
> >>> On Thu, Feb 07, 2019 at 01:22:25PM +0100, Marek Szypr
On Thu, Jan 24, 2019 at 03:12:46PM -0500, Sven Van Asbroeck wrote:
> +static DEFINE_IDA(fieldbus_ida);
You forget to destroy this ida structure when the module is removed.
It's a common thing to get wrong :(
thanks,
greg k-h
On Wed, Feb 06, 2019 at 08:47:36AM -0500, Sven Van Asbroeck wrote:
> On Thu, Jan 24, 2019 at 3:12 PM Sven Van Asbroeck wrote:
> >
> > This patch:
> > 1. adds a Fieldbus subsystem
> > 2. adds support for the HMS Industrial Networks AB Profinet card.
> >
>
> Is there any feedback I may address?
Hi,
On 8/2/19 2:23, Nick Crews wrote:
> This Embedded Controller has an internal RTC that is exposed
> as a standard RTC class driver with read/write functionality.
>
> The driver is added to the drivers/rtc/ so that the maintainer of that
> directory will be able to comment on this change, as th
On Thu, Jan 24, 2019 at 03:12:51PM -0500, Sven Van Asbroeck wrote:
> The Anybus-S PROFINET IRT communication module provides instant integration
> to any Ethernet based LAN via SMTP, FTP, HTTP as well as PROFINET and
> Modbus-TCP. Additional protocols can be implemented on top of TCP/IP
> or UDP us
On Thu, Dec 06, 2018 at 08:52:25PM +0800, Wen Yang wrote:
> kmemdup has implemented the function that kmalloc() + memcpy().
> We prefer to kmemdup rather than code opened implementation.
>
> This issue was detected with the help of coccinelle.
>
> Signed-off-by: Wen Yang
> CC: Kishon Vijay Abrah
On Fri, Feb 01, 2019 at 01:09:21PM +, Srinivas Kandagatla wrote:
> The FastRPC driver implements an IPC (Inter-Processor Communication)
> mechanism that allows for clients to transparently make remote method
> invocations across DSP and APPS boundaries. This enables developers
> to offload task
On 2/8/19 6:50 AM, Jarkko Sakkinen wrote:
On Thu, Feb 07, 2019 at 09:14:54PM -0500, Stefan Berger wrote:
chip->ops = NULL;
up_write(&chip->ops_sem);
}
diff --git a/drivers/char/tpm/tpm-interface.c
b/drivers/char/tpm/tpm-interface.c
index 02e8cffd1163..fcd845ad8c3c 100644
--- a/dri
On 04/02/19 10:47 PM, Bartosz Golaszewski wrote:
> -/*
> - * T0_BOT: Timer 0, bottom : Used for clock_event & clocksource
> - * T0_TOP: Timer 0, top : Used by DSP
> - * T1_BOT, T1_TOP: Timer 1, bottom & top: Used for watchdog timer
Aren't we changing this usage model
On Fri, Feb 8, 2019 at 1:09 PM Sudeep Holla wrote:
>
> On Fri, Feb 08, 2019 at 01:03:10PM +0100, Rafael J. Wysocki wrote:
> > On Fri, Feb 8, 2019 at 12:39 PM Sudeep Holla wrote:
> > >
> > > On Fri, Feb 08, 2019 at 11:42:20AM +0100, Rafael J. Wysocki wrote:
> > > > On Fri, Feb 8, 2019 at 11:31 AM
The Milbeaut M10V SoC needs a part of sram for smp, so this adds the
M10V sram compatible and binding.
Signed-off-by: Sugaya Taichi
---
.../devicetree/bindings/sram/milbeaut-smp-sram.txt | 24 ++
1 file changed, 24 insertions(+)
create mode 100644 Documentation/devicetree/bi
This adds a compatible string "socionext,milbeaut-m10v-smp"
for Milbeaut M10V to the 32 bit ARM CPU device tree binding.
Signed-off-by: Sugaya Taichi
---
Documentation/devicetree/bindings/arm/cpus.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/arm/cpus
Hi,
Here is the series of patches the initial support for SC2000(M10V) of
Milbeaut SoCs. "M10V" is the internal name of SC2000, so commonly used in
source code.
SC2000 is a SoC of the Milbeaut series. equipped with a DSP optimized for
computer vision. It also features advanced functionalities suc
Add DT bindings document for Milbeaut M10V timer.
Signed-off-by: Sugaya Taichi
---
.../bindings/timer/socionext,milbeaut-timer.txt | 17 +
1 file changed, 17 insertions(+)
create mode 100644
Documentation/devicetree/bindings/timer/socionext,milbeaut-timer.txt
diff --gi
Add timer driver for Milbeaut SoCs series.
The timer has two 32-bit width down counters, one of which is configured
as a clockevent device and the other is configured as a clock source.
Signed-off-by: Sugaya Taichi
---
drivers/clocksource/Kconfig | 9 ++
drivers/clocksource/Makefile
Add DT bindings document for Milbeaut clock.
Signed-off-by: Sugaya Taichi
---
.../devicetree/bindings/clock/milbeaut-clock.txt | 49 ++
1 file changed, 49 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/milbeaut-clock.txt
diff --git a/Documentatio
This adds a DT binding documentation for the M10V and its evaluation
board.
Signed-off-by: Sugaya Taichi
---
Documentation/devicetree/bindings/arm/milbeaut.txt | 6 ++
1 file changed, 6 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/milbeaut.txt
diff --git a/Documen
This adds the basic M10V SoC support under arch/arm.
Since all cores are activated in the custom bootloader before booting
linux, it is necessary to wait for the secondary-cores using cpu-enable-
method and special sram.
Signed-off-by: Sugaya Taichi
---
arch/arm/Kconfig | 2 +
The M10V of the Milbeaut SoCs has an on-chip controller that derive
mostly clocks from a single external clock, using PLLs, dividers,
multiplexers and gates. Since the PLLs have already been started and
will not stop / restart, they are fixed factor. Gates will be added in
later patch (all gates ar
Add DT bindings document for Milbeaut serial driver.
Signed-off-by: Sugaya Taichi
---
.../devicetree/bindings/serial/milbeaut-uart.txt| 21 +
1 file changed, 21 insertions(+)
create mode 100644 Documentation/devicetree/bindings/serial/milbeaut-uart.txt
diff --git a/Docu
Add Milbeaut serial control including earlycon and console.
Signed-off-by: Sugaya Taichi
---
drivers/tty/serial/Kconfig | 25 ++
drivers/tty/serial/Makefile| 1 +
drivers/tty/serial/milbeaut_usio.c | 621 +
include/uapi/linux/serial_core.h
On 02/08/2019 01:39 PM, Bean Huo (beanhuo) wrote:
> Hi, Tudor
>
>> SNOR_HWCPAS_READ_OCTO was renamed to SNOR_HWCPAS_READ_OCTAL
>> please update your remote and send a new patch.
>>
> Which branch do you mean? I checked linux-mtd, not renamed yet.
spi-nor/next
>
>> The patch prefix is wrong, i
Add devicetree for Milbeaut M10V SoC and M10V Evaluation board.
Signed-off-by: Sugaya Taichi
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/milbeaut-m10v-evb.dts | 32
arch/arm/boot/dts/milbeaut-m10v.dtsi| 131
3 files change
Add Milbeaut M10V pinctrl.
The M10V has the pins that can be used GPIOs or take multiple other
functions.
Signed-off-by: Sugaya Taichi
---
drivers/pinctrl/Kconfig| 9 +
drivers/pinctrl/Makefile | 1 +
drivers/pinctrl/pinctrl-milbeaut.c | 759
This patch adds the minimal defconfig for the Milbeaut M10V.
Signed-off-by: Sugaya Taichi
---
arch/arm/configs/milbeaut_m10v_defconfig | 366 +++
1 file changed, 366 insertions(+)
create mode 100644 arch/arm/configs/milbeaut_m10v_defconfig
diff --git a/arch/arm/conf
Add entry to MAINTAINERS for Milbeaut that supported minimal drivers.
Signed-off-by: Sugaya Taichi
---
MAINTAINERS | 9 +
1 file changed, 9 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 8c68de3c..50e0479 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1806,6 +1806,15 @@ F:
pt., 8 lut 2019 o 12:43 Sekhar Nori napisał(a):
>
> On 05/02/19 9:41 PM, Bartosz Golaszewski wrote:
> > pon., 4 lut 2019 o 22:49 David Lechner napisał(a):
> >>
> >> On 1/31/19 7:38 AM, Bartosz Golaszewski wrote:
> >>> From: Bartosz Golaszewski
> >>>
> >>> This series ports the davinci platform t
On Tue, Jan 29, 2019 at 1:39 PM Z.q. Hou wrote:
>
> From: Hou Zhiqiang
>
> Move irq_set_chained_handler_and_data() out of DT parse function.
>
> Signed-off-by: Hou Zhiqiang
> Reviewed-by: Minghuan Lian
> ---
> V3:
> - No change
>
> drivers/pci/controller/pcie-mobiveil.c | 4 ++--
> 1 file cha
On Tue, Jan 29, 2019 at 1:40 PM Z.q. Hou wrote:
>
> From: Hou Zhiqiang
>
> Change the "gpio_slave" and "apb_csr" to optional, the "gpio_slave"
> is not used in current code, and "apb_csr" is not used by some
> platforms.
>
> Signed-off-by: Hou Zhiqiang
> Acked-by: Subrahmanya Lingappa
> Acked-b
On Tue, Jan 29, 2019 at 1:40 PM Z.q. Hou wrote:
>
> From: Hou Zhiqiang
>
> The reset value is all zero, so set a workable value for Primary,
> Secondary and Subordinate bus numbers.
>
> Signed-off-by: Hou Zhiqiang
> Reviewed-by: Minghuan Lian
> ---
> V3:
> - No change
>
> drivers/pci/controll
On 29/01/2019 05:31, Ryder Lee wrote:
> This updates bindings for MT7629 SoC, which includes very basic items
> such as system timer, UART, sysirq and scpsys unit.
>
> Signed-off-by: Ryder Lee
> ---
> .../devicetree/bindings/interrupt-controller/mediatek,sysirq.txt | 5 +++--
> Documentatio
On 08/02/2019 12:21, Greg KH wrote:
On Fri, Feb 01, 2019 at 01:09:21PM +, Srinivas Kandagatla wrote:
The FastRPC driver implements an IPC (Inter-Processor Communication)
mechanism that allows for clients to transparently make remote method
invocations across DSP and APPS boundaries. This
On 07.02.2019 17:17, Srinath Mannam wrote:
Hi Mathias,
Thanks for review, please see my comments below inline.
On Thu, Feb 7, 2019 at 8:32 PM Mathias Nyman
wrote:
On 05.02.2019 08:18, Srinath Mannam wrote:
Add a quirk to reset xHCI port PHY on port disconnect event.
Stingray USB HS PHY has
On 08/02/19 5:57 PM, Bartosz Golaszewski wrote:
> pt., 8 lut 2019 o 12:43 Sekhar Nori napisał(a):
>>
>> On 05/02/19 9:41 PM, Bartosz Golaszewski wrote:
>>> pon., 4 lut 2019 o 22:49 David Lechner napisał(a):
On 1/31/19 7:38 AM, Bartosz Golaszewski wrote:
> From: Bartosz Golaszewski
On 29/01/2019 05:31, Ryder Lee wrote:
> This adds basic support for MT7629 reference board.
>
> Signed-off-by: Ryder Lee
> ---
> The I2C node depends on https://patchwork.kernel.org/patch/10772837/
> The PCIe node depends on https://patchwork.kernel.org/patch/10773637/
Not all of them are mer
Add DT bindings document for Milbeaut M10V pinctrl.
Signed-off-by: Sugaya Taichi
---
.../pinctrl/socionext,milbeaut-pinctrl.txt | 35 ++
1 file changed, 35 insertions(+)
create mode 100644
Documentation/devicetree/bindings/pinctrl/socionext,milbeaut-pinctrl.txt
dif
On 04/02/19 10:47 PM, Bartosz Golaszewski wrote:
> -/*
> - * T0_BOT: Timer 0, bottom: clockevent source for hrtimers
> - * T0_TOP: Timer 0, top : clocksource for generic timekeeping
> - * T1_BOT: Timer 1, bottom: (used by DSP in TI DSPLink code)
> - * T1_TOP: Timer 1, top :
Documenting th
pt., 8 lut 2019 o 13:06 Sekhar Nori napisał(a):
>
> On 04/02/19 10:47 PM, Bartosz Golaszewski wrote:
> > +static const struct davinci_timer_cfg da850_timer_cfg = {
> > + .reg = {
> > + .start = DA8XX_TIMER64P0_BASE,
> > + .end= DA8XX_TIMER64P0_BASE
On Tue, Jan 29, 2019 at 1:40 PM Z.q. Hou wrote:
>
> From: Hou Zhiqiang
>
> As the Mobiveil PCIe controller support RC&EP DAUL mode, and to
> make platforms which integrated the Mobiveil PCIe IP more easy
> to add their drivers, this patch moved the Mobiveil driver to
> a new directory 'drivers/pc
Hi Roger,
On 2019-02-06 11:17, Roger Quadros wrote:
> +Marek
>
> As Vivek's and Andrzej's Samsung IDs bounced back.
>
> On 06/02/19 11:38, Jochen Sprickerhof wrote:
>> * Roger Quadros [2019-02-06 10:41]:
>>> Hi,
>>>
>>> On 21/01/19 16:02, Jochen Sprickerhof wrote:
>> [..]
I'm not sure why th
On Fri, Feb 08, 2019 at 09:53:03AM +, David Laight wrote:
> From: 'Marcelo Ricardo Leitner'
> > Sent: 07 February 2019 17:47
> ...
> > > > Maybe what we want(ed) here then is explicit versioning, to have the 3
> > > > definitions available. Then the application is able to use, say struct
> > >
Validation of the IRQ type was added to spmi pmic-arb, however spmi-mpp
in device tree still uses IRQ_TYPE_NONE. This commit caused the
spmi-mpp probe to fail since platform_irq_count() would return 0.
Correct this by backing out the previous patch.
Signed-off-by: Brian Masney
Fixes: 135ef21ab064
On 08/02/19 6:04 PM, Bartosz Golaszewski wrote:
> pt., 8 lut 2019 o 13:06 Sekhar Nori napisał(a):
>>
>> On 04/02/19 10:47 PM, Bartosz Golaszewski wrote:
>>> +static const struct davinci_timer_cfg da850_timer_cfg = {
>>> + .reg = {
>>> + .start = DA8XX_TIMER64P0_BASE,
>>> +
ZQ,
On Tue, Jan 29, 2019 at 1:40 PM Z.q. Hou wrote:
>
> From: Hou Zhiqiang
>
> Avoid to issue CFG transactions to link partner when the PCIe
> link is not up. And allow CFG transactions to all functions of
> Endpoint implemented multiple functions.
>
> Fixes: 9af6bcb11e12 ("PCI: mobiveil: Add Mo
On Tue, Jan 29, 2019 at 1:40 PM Z.q. Hou wrote:
>
> From: Hou Zhiqiang
>
> Disabled all inbound and outbound windows before set up the windows
> in kernel, in case transactions match the window set by bootloader.
>
> Signed-off-by: Hou Zhiqiang
> Reviewed-by: Minghuan Lian
> ---
> V3:
> - No c
On Tue, Jan 29, 2019 at 1:40 PM Z.q. Hou wrote:
>
> From: Hou Zhiqiang
>
> Sometimes there is not a PCIe Endpoint in the PCIe slot, so do
> not exit when the PCIe link is not up. And degrade the print
> level of link up info.
>
> Signed-off-by: Hou Zhiqiang
> Reviewed-by: Minghuan Lian
> ---
>
Hello Lee,
On Fri, Feb 08, 2019 at 10:57:43AM +, Lee Jones wrote:
> >
> > This is needed by both RTC and WDT drivers as RTC driver must stop the
> > WDT when it sets RTC. WDT HW is using RTC counter and might trigger
> > timeout/reset when RTC is set. Options are to dublicate the
> > enable/d
On Tue, Jan 29, 2019 at 1:40 PM Z.q. Hou wrote:
>
> From: Hou Zhiqiang
>
> As there are some Byte and Half-Work width registers in PCIe
> configuration space, add Byte and Half-Word width register
> accessors.
>
> Signed-off-by: Hou Zhiqiang
> Reviewed-by: Minghuan Lian
> ---
> V3:
> - No chan
Signed-off-by: Axel Lin
---
drivers/regulator/rt5033-regulator.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/regulator/rt5033-regulator.c
b/drivers/regulator/rt5033-regulator.c
index 96d2c18e051a..639cbadc044a 100644
--- a/drivers/regulator/rt5033-regulator.c
On Tue, Jan 29, 2019 at 1:40 PM Z.q. Hou wrote:
>
> From: Hou Zhiqiang
>
> Make the mobiveil_host_init function can be used to re-init
> host controller's PAB and GPEX CSR register block, as NXP
> integrated Mobiveil IP has to reset and then re-init the PAB
> and GPEX CSR registers upon Hot-reset
ZQ,
On Tue, Jan 29, 2019 at 1:40 PM Z.q. Hou wrote:
>
> From: Hou Zhiqiang
>
> This PCIe controller is based on the Mobiveil GPEX IP, which is
> compatible with the PCI Express™ Base Specification, Revision 4.0.
>
> Signed-off-by: Hou Zhiqiang
> Reviewed-by: Minghuan Lian
> ---
> V3:
> - No
08.02.2019 1:25, Dmitry Osipenko пишет:
>> 08.02.2019 1:16, Sowjanya Komatineni пишет:>
This is wrong, 65535 = 64 * 1024 - 1.
Let's just use size-constants provided by kernel:
static const struct i2c_adapter_quirks tegra_i2c_quirks = {
.flags = I2C_AQ_NO_ZERO_LEN,
pt., 8 lut 2019 o 13:23 Sekhar Nori napisał(a):
>
> On 04/02/19 10:47 PM, Bartosz Golaszewski wrote:
> > -/*
> > - * T0_BOT: Timer 0, bottom : Used for clock_event & clocksource
> > - * T0_TOP: Timer 0, top : Used by DSP
> > - * T1_BOT, T1_TOP: Timer 1, bottom & top:
08.02.2019 0:47, Sowjanya Komatineni пишет:
> This patch adds DMA support for Tegra I2C.
>
> Tegra I2C TX and RX FIFO depth is 8 words. PIO mode is used for
> transfer size of the max FIFO depth and DMA mode is used for
> transfer size higher than max FIFO depth to save CPU overhead.
>
> PIO mode
pt., 8 lut 2019 o 13:37 Sekhar Nori napisał(a):
>
> On 08/02/19 6:04 PM, Bartosz Golaszewski wrote:
> > pt., 8 lut 2019 o 13:06 Sekhar Nori napisał(a):
> >>
> >> On 04/02/19 10:47 PM, Bartosz Golaszewski wrote:
> >>> +static const struct davinci_timer_cfg da850_timer_cfg = {
> >>> + .reg = {
ZQ,
On Tue, Jan 29, 2019 at 1:41 PM Z.q. Hou wrote:
>
> From: Hou Zhiqiang
>
> PCIe configuration access to non-existent function triggered
> SERROR interrupt exception.
>
> Workaround:
> Disable error reporting on AXI bus during the Vendor ID read
> transactions in enumeration.
>
> This ERRATA
ZQ,
On Tue, Jan 29, 2019 at 1:41 PM Z.q. Hou wrote:
>
> From: Hou Zhiqiang
>
> When LX2 PCIe controller is sending multiple split completions and
> ACK latency expires indicating that ACK should be send at priority.
> But because of large number of split completions and FC update DLLP,
> the con
On Fri 08-02-19 10:55:07, Jan Kara wrote:
> On Thu 07-02-19 21:37:27, Andrew Morton wrote:
> > On Thu, 7 Feb 2019 11:27:50 +0100 Jan Kara wrote:
> >
> > > On Fri 01-02-19 09:19:04, Dave Chinner wrote:
> > > > Maybe for memcgs, but that's exactly the oppose of what we want to
> > > > do for global
The purpose of this series is to implement a fast syscall entry
on ppc32.
Unlike all other exceptions which can happen at any time and
require to preserve all registers, the syscalls do not
require the preservation of volatile registers (except LR).
Syscall entries can then be optimised with ligh
syscalls are expected to be entered with MSR_EE set. Lets
make it inconditional by forcing MSR_EE on syscalls.
This patch adds EXC_XFER_SYS for that.
Suggested-by: Benjamin Herrenschmidt
[splited out from benh RFC patch]
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_32.S
SPEFloatingPointException() is the only exception handler which 'forgets' to
re-enable interrupts. This patch makes sure it does.
Suggested-by: Benjamin Herrenschmidt
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/traps.c | 8
1 file changed, 8 insertions(+)
diff --git a/arch
As syscalls are now handled via a fast entry path, syscall related
actions can be removed from the generic transfer_to_handler path.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/entry_32.S | 8
1 file changed, 8 insertions(+)
diff --git a/arch/powerpc/kernel/entry_32.S b/arc
syscalls are from user only, so we can account time without checking
whether returning to kernel or user as it will only be user.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/entry_32.S | 5 -
1 file changed, 5 deletions(-)
diff --git a/arch/powerpc/kernel/entry_32.S b/arch/power
Hi,
Marek Szyprowski writes:
On 21/01/19 16:02, Jochen Sprickerhof wrote:
>>> [..]
> I'm not sure why this it only works with the driver compiled into the
> kernel nor why it needs a hard reset or why it was the line was dropped
> when the patch was accepted. Would be great to g
6xx/8xx EXC_XFER_TEMPLATE() macro adds a i##n symbol which is
unused and can be removed.
40x and booke EXC_XFER_TEMPLATE() macros takes msr from the caller
while the 6xx/8xx version uses only MSR_KERNEL as msr value.
This patch modifies the 6xx/8xx version to make it similar to the
40x and booke v
EXC_XFER_TEMPLATE() is not called with COPY_EE anymore so
we can get rid of copyee parameters and related COPY_EE and NOCOPY
macros.
Suggested-by: Benjamin Herrenschmidt
[splited out from benh RFC patch]
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_32.h| 12
ar
This patch implements a fast entry for syscalls.
Syscalls don't have to preserve non volatile registers except LR.
This patch then implement a fast entry for syscalls, where
volatile registers get clobbered.
As this entry is dedicated to syscall it always sets MSR_EE
and warns in case MSR_EE was
[text mostly copied from benh's RFC/WIP]
ppc32 are still doing something rather gothic and wrong on 32-bit
which we stopped doing on 64-bit a while ago.
We have that thing where some handlers "copy" the EE value from the
original stack frame into the new MSR before transferring to the
handler.
T
All exceptions handler knows when to reenable interrupts, so
it is safer to enter all of them with MSR_EE unset, except
for syscalls.
Suggested-by: Benjamin Herrenschmidt
[splited out from benh RFC patch]
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_32.S| 68 +++
This patch adds STACK_FRAME_REGS_MARKER in the stack at exception entry
in order to see interrupts in call traces as below:
[0.013964] Call Trace:
[0.014014] [c0745db0] [c007a9d4] tick_periodic.constprop.5+0xd8/0x104
(unreliable)
[0.014086] [c0745dc0] [c007aa20] tick_handle_periodic+0
This patch splits NORMAL_EXCEPTION_PROLOG in the same way as in
head_8xx.S and head_32.S and renames it EXCEPTION_PROLOG() as well
to match head_32.h
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_40x.S | 26 --
1 file changed, 16 insertions(+), 10 deletions
Unlike said in the comment, r1 is not reused by the critical
exception handler, as it uses a dedicated critirq_ctx stack.
Decrementing r1 early is then unneeded.
Should the above be valid, the code is crap buggy anyway as
r1 gets some intermediate values that would jeopardise the
whole process (fo
This patch is a squashed version of the
CONFIG_THREAD_INFO_IN_TASK series to make building robots
happy until that serie appears in powerpc/next.
Signed-off-by: Christophe Leroy
---
arch/powerpc/Kconfig | 1 +
arch/powerpc/Makefile | 7 ++
a
As preparation for using head_32.h for head_40x.S, move
LOAD_MSR_KERNEL() there and use it to load r10 with MSR_KERNEL value.
In the mean time, this patch modifies it so that it takes into account
the size of the passed value to determine if 'li' can be used or if
'lis/ori' is needed instead of us
On Fri, Feb 08, 2019 at 09:39:39AM +0100, Takashi Iwai wrote:
> > Mark, could you apply it on your tree?
> And I already took back the API change from for-next branch for
> avoiding the bisection breakage.
> > Or let me pull your tree into mine.
> ... so Mark, please send a pull request to me f
08.02.2019 0:47, Sowjanya Komatineni пишет:
> This patch adds I2C interface timing registers support for
> proper bus rate configuration along with meeting the I2C spec
> setup and hold times based on the tuning performed on Tegra210,
> Tegra186 and Tegra194 platforms.
>
> I2C_INTERFACE_TIMING_0 r
From: Bo Yu
There is a warning if enable W=1 when compile kernel:
arch/x86/kernel/cpu/mtrr/cleanup.c:299:16: warning: variable ‘second_basek’ set
but not used [-Wunused-but-set-variable]
unsigned long second_basek, second_sizek;
Signed-off-by: Bo Yu
---
arch/x86/kernel/cpu/mtrr/cleanup.c |
Refactor exception entry macros by using the ones defined in head_32.h
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_32.h | 4 ++
arch/powerpc/kernel/head_40x.S | 88 +-
2 files changed, 6 insertions(+), 86 deletions(-)
diff --git a/arch/
EXCEPTION_PROLOG is similar in head_8xx.S and head_32.S
This patch creates head_32.h and moves EXCEPTION_PROLOG macro
into it. It also converts it from a GCC macro to a GAS macro
in order to ease refactorisation with 40x later, since
GAS macros allows the use of #ifdef/#else/#endif inside it.
And
Hi Beomho,
The code has below defines in include/linux/mfd/rt5033-private.h
#define RT5033_REGULATOR_BUCK_VOLTAGE_MAX 300U
#define RT5033_REGULATOR_LDO_VOLTAGE_MAX300U
However, according to current settings in rt5033 regulator driver:
For LDOs, it can support
On Fri, Feb 08, 2019 at 09:56:59AM +0100, Daniel Vetter wrote:
> On Fri, Feb 08, 2019 at 01:02:58AM -0500, Michael S. Tsirkin wrote:
> > Use linux/mman.h to make sure we get all mmap flags we need.
> >
> > Signed-off-by: Michael S. Tsirkin
>
> drmP.h is seriously deprecated (and a monster mess).
On Fri, Feb 01, 2019 at 03:08:17PM +, Lee Jones wrote:
> On Fri, 01 Feb 2019, Andy Shevchenko wrote:
> > On Fri, Feb 1, 2019 at 11:50 AM Lee Jones wrote:
> > > On Thu, 24 Jan 2019, Andy Shevchenko wrote:
> > >
> > > > We now using a common macro for PM operations in Intel LPSS driver,
> > > >
08.02.2019 15:53, Dmitry Osipenko пишет:
> 08.02.2019 0:47, Sowjanya Komatineni пишет:
>> This patch adds I2C interface timing registers support for
>> proper bus rate configuration along with meeting the I2C spec
>> setup and hold times based on the tuning performed on Tegra210,
>> Tegra186 and Te
On Thu, 2019-01-17 at 16:10:33 UTC, Sabyasachi Gupta wrote:
> Remove linux/printk.h which is included more than once.
>
> Signed-off-by: Sabyasachi Gupta
> Acked-by: Souptick Joarder
Applied to powerpc next, thanks.
https://git.kernel.org/powerpc/c/f069a062ecce7ccc17221c24097826e8
cheers
201 - 300 of 1100 matches
Mail list logo
