On 1/31/19 7:38 AM, Bartosz Golaszewski wrote:
From: Bartosz Golaszewski
In order to select SPARSE_IRQ we need to make the interrupt numbers
dynamic (at least at build-time for the top-level controller). The
interrupt numbers are used as array indexes for irq priorities.
Drop the defines and j
On Tue, Dec 25, 2018 at 12:14:57AM +0900, Masahiro Yamada wrote:
> The whole code of fallback_table.c is surrounded by #ifdef of
> CONFIG_FW_LOADER_USER_HELPER.
>
> Move the CONFIG_FW_LOADER_USER_HELPER switch to Makefile so that
> it is not compiled at all when this CONFIG is turned off.
>
> I a
On 2/2/19 12:56 PM, Matthew Wilcox wrote:
> On Fri, Feb 01, 2019 at 02:04:16PM -0800, frowand.l...@gmail.com wrote:
>>Include documentation for each *function* in *source*.
>> - If no *function* if specified, the documentaion for all functions
>> + If no *function* if specified, the documenta
On 1/31/19 7:39 AM, Bartosz Golaszewski wrote:
From: Bartosz Golaszewski
Modify the cp-intc driver to take all its configuration from the new
config structure. Stop referencing davinci_soc_info in any way.
Move the declaration for davinci_cp_intc_init() to
irq-davinci-cp-intc.h and make it take
Hi Jiada
> Currently "0xf << 36" is used to
> clear SSIU-9 internal buffer state, which overflows 32-bit value
> according to user reference manual, it is always bit4 ~ bit7
> of SSI_SYS_STATUS[1,3,5,7] registers indicate
> SSIU-9's buffer state, so "0xf << 4" should be used.
>
> This patch fix
On 1/31/19 7:39 AM, Bartosz Golaszewski wrote:
From: Bartosz Golaszewski
Drop tabs from variable initialization. Arrange variables in reverse
christmas-tree order.
I'm not sure this description is correct.
Add a newline before a return.
Signed-off-by: Bartosz Golaszewski
---
arch/arm/m
On 1/31/19 7:39 AM, Bartosz Golaszewski wrote:
From: Bartosz Golaszewski
Use WARN_ON() on eny error in cp-intc initialization and drop all
custom error messages.
Signed-off-by: Bartosz Golaszewski
---
Reviewed-by: David Lechner
On 1/31/19 7:39 AM, Bartosz Golaszewski wrote:
From: Bartosz Golaszewski
This header is no longer needed. Remove it.
Is there another patch in this series that causes it to no
longer be needed? If so, this patch could be squashed into
that patch.
Signed-off-by: Bartosz Golaszewski
---
a
Hi Lukasz,
On Fri, Feb 01, 2019 at 07:38:03PM +0100, Lukasz Luba wrote:
> This patch removes devfreq's custom workqueue and uses system one.
> It switches from queue_delayed_work() to schedule_delayed_work().
> It also changes deferred work to delayed work, which is now not missed
> when timer is
On 1/31/19 7:39 AM, Bartosz Golaszewski wrote:
From: Bartosz Golaszewski
Replace the GPLv2 license boilerplate with an SPDX identifier.
Should also mention that you are adding an author and copyright.
Signed-off-by: Bartosz Golaszewski
---
arch/arm/mach-davinci/cp_intc.c | 18 --
On 1/31/19 7:39 AM, Bartosz Golaszewski wrote:
From: Bartosz Golaszewski
We don't need comments explaining what functions with obvious names do.
Signed-off-by: Bartosz Golaszewski
---
Reviewed-by: David Lechner
On 1/31/19 7:39 AM, Bartosz Golaszewski wrote:
From: Bartosz Golaszewski
The cp-intc driver has now been cleaned up. Move it to drivers/irqchip
where it belongs.
Signed-off-by: Bartosz Golaszewski
---
Reviewed-by: David Lechner
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
On 1/31/19 7:39 AM, Bartosz Golaszewski wrote:
From: Bartosz Golaszewski
These are no longer used. Remove them.
Signed-off-by: Bartosz Golaszewski
---
Reviewed-by: David Lechner
With apps_smmu initializing the SMMU we must specify iommus property for
the sdhc controller.
Fixes: 4429e57567bb ("arm64: dts: sdm845: Add node for arm,mmu-500")
Signed-off-by: Bjorn Andersson
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm6
The USB controllers need to be associated with their respective IOMMU
bank, so define this on the dwc3 nodes.
Also add dma-ranges to the qcom-dwc3 nodes to make the bus' DMA mask
propagate to the dwc3 controller instances.
Fixes: 4429e57567bb ("arm64: dts: sdm845: Add node for arm,mmu-500")
Signe
On 1/31/19 7:39 AM, Bartosz Golaszewski wrote:
From: Bartosz Golaszewski
As the second step in preparation for mach/irqs.h removal - replace
all constants defined there with the DAVINCI_INTC_IRQ() macro which
takes the NR_IRQS offset into account.
Signed-off-by: Bartosz Golaszewski
---
Revi
On 1/31/19 7:39 AM, Bartosz Golaszewski wrote:
From: Bartosz Golaszewski
We can now remove mach/irqs.h as there are no more users.
Signed-off-by: Bartosz Golaszewski
---
Reviewed-by: David Lechner
On 2/4/19 3:57 PM, Jerry Hoemann wrote:
Document the sysfs attributes:
pretimeout
pretimeout_available_governors
pretimeout_governor
Signed-off-by: Jerry Hoemann
Reviewed-by: Guenter Roeck
---
Documentation/ABI/testing/sysfs-class-watchdog | 23 +++
On Sun, 2019-02-03 at 13:37 -0800, Andi Kleen wrote:
> On Sun, Feb 03, 2019 at 08:05:53PM +0100, Jiri Kosina wrote:
> > On Sun, 3 Feb 2019, Ben Hutchings wrote:
> >
> > > 3.16.63-rc1 review patch. If anyone has any objections, please let me
> > > know.
> > >
> > > --
> > >
> >
On 2/4/19 11:17 AM, Bartosz Golaszewski wrote:
From: Bartosz Golaszewski
The timer interrupts specified in commit 3652e2741f42 ("ARM: dts:
da850: Add clocks") are wrong but since the current timer code
hard-codes them, the bug was never spotted.
This patch must go into stable since, once we in
Booting up an arm64 server with CONFIG_VALIDATE_FS_PARSER=n triggers a
out-of-bounds error below, due to the commit 2284cf59cbce ("hugetlbfs:
Convert to fs_context") missed a terminator for hugetlb_param_specs[],
and causes this loop in fs_lookup_key(),
for (p = desc->specs; p->name; p++)
could n
This patch adds I2C interface timing registers support for
proper bus rate configuration along with meeting the i2c spec
setup and hold times based on the tuning performed on Tegra210,
Tegra186 and Tegra194 platforms.
I2C_INTERFACE_TIMING_0 register contains TLOW and THIGH field
and Tegra I2C cont
This patch sorts all the include headers alphabetically for the
I2C Tegra driver.
Signed-off-by: Sowjanya Komatineni
Acked-by: Thierry Reding
Reviewed-by: Dmitry Osipenko
---
[V9/V10] : Rebased to 5.0-rc4
[V3/V4/V5/V7/V8] : Removed unsued headers in tegra I2C
[V2] : Added this in V2 to sort
Tegra194 allows max of 64K bytes and Tegra186 and prior allows
max of 4K bytes of transfer per packet.
one sec timeout is not enough for transfers more than 10K bytes
at STD bus rate.
This patch updates I2C transfer timeout based on the transfer size
and I2C bus rate to allow enough time during m
Bus clear feature of Tegra I2C controller helps to recover from
bus hang when I2C master loses the bus arbitration due to the
slave device holding SDA LOW continuously for some unknown reasons.
Per I2C specification, the device that held the bus LOW should
release it within 9 clock pulses.
During
This patch adds DMA support for Tegra I2C.
Tegra I2C TX and RX FIFO depth is 8 words. PIO mode is used for
transfer size of the max FIFO depth and DMA mode is used for
transfer size higher than max FIFO depth to save CPU overhead.
PIO mode needs full intervention of CPU to fill or empty FIFO's
an
> I know that APB DMA driver enables flow control based on the channels spec,
> but still won't hurt to explicitly show that channels are flow-controlled.
> Ideally APB DMA driver should respect the device_fc field.
>
> dma_sconfig.device_fc = true;
Dmitry,
Thanks for all feedback
On Sat, 2 Feb 2019 at 10:20, Lyude Paul wrote:
>
> Atomic checks should never modify anything outside of the state that
> they're passed in. Unfortunately this appears to be exactly what we're
> doing in nv50_msto_atomic_check() where we update mstc->pbn every time
> the function is called. This h
On 2/4/19 3:42 PM, Hugh Dickins wrote:
> On Mon, 4 Feb 2019, Artem Savkov wrote:
>
>> Hi Hugh,
>>
>> Your recent patch 9a1ea439b16b "mm: put_and_wait_on_page_locked() while
>> page is migrated" seems to have introduced a race into page migration
>> process. I have a host that eagerly reproduces
> On Feb 4, 2019, at 4:16 PM, Alexander Duyck wrote:
>
> On Mon, Feb 4, 2019 at 4:03 PM Nadav Amit wrote:
>>> On Feb 4, 2019, at 3:37 PM, Alexander Duyck
>>> wrote:
>>>
>>> On Mon, 2019-02-04 at 15:00 -0800, Nadav Amit wrote:
> On Feb 4, 2019, at 10:15 AM, Alexander Duyck
> wrote:
>
The mm-of-the-moment snapshot 2019-02-04-17-47 has been uploaded to
http://www.ozlabs.org/~akpm/mmotm/
mmotm-readme.txt says
README for mm-of-the-moment:
http://www.ozlabs.org/~akpm/mmotm/
This is a snapshot of my -mm patch queue. Uploaded at random hopefully
more than once a week.
You wi
On 2/4/2019 12:21 AM, john.hubb...@gmail.com wrote:
From: John Hubbard
Performance: here is an fio run on an NVMe drive, using this for the fio
configuration file:
[reader]
direct=1
ioengine=libaio
blocksize=4096
size=1g
numjobs=1
rw=read
iodepth=64
re
Sorry this patch isn't working, it's not possible to set BT.709
encoding, working on a fix for v2.
Steve
On 2/3/19 11:47 AM, Steve Longerbeam wrote:
The IC now supports BT.709 Y'CbCr encoding, in addition to existing BT.601
encoding, so allow both, for pipelines that route through the IC.
Re
Hello,
syzbot found the following crash on:
HEAD commit:5eeb63359b1e Merge tag 'for-linus' of git://git.kernel.org..
git tree: upstream
console output: https://syzkaller.appspot.com/x/log.txt?x=17906f64c0
kernel config: https://syzkaller.appspot.com/x/.config?x=2e0064f906afee10
da
On 2/4/19 11:17 AM, Bartosz Golaszewski wrote:
From: Bartosz Golaszewski
Currently the clocksource and clockevent support for davinci platforms
lives in mach-davinci. It hard-codes many things, used global variables,
implements functionalities unused by any platform and has code fragments
scatt
On 2/4/19 11:17 AM, Bartosz Golaszewski wrote:
From: Bartosz Golaszewski
Switch all davinci boards using device tree to using the new
clocksource driver: remove the previous OF_TIMER_DECLARE() from
mach-davinci and select davinci-timer to be built for
davinci_all_defconfig.
I don't see how th
On 2/4/19 11:17 AM, Bartosz Golaszewski wrote:
From: Bartosz Golaszewski
Currently the timer code checks if the clock pointer passed to it is
good (!IS_ERR(clk)). The new clocksource driver expects the clock to
be functional and doesn't perform any checks so emit a warning if
clk_get() fails. A
Hi Dan,
On Tue, Jan 15, 2019 at 4:00 AM Dan Williams wrote:
>
> On Mon, Jan 14, 2019 at 12:59 AM Jan Kara wrote:
> >
> > On Sat 05-01-19 00:54:11, Souptick Joarder wrote:
> > > This code is converted to use vmf_error().
> > >
> > > Signed-off-by: Souptick Joarder
> >
> > Dan, you are merging DA
On 2/4/19 11:17 AM, Bartosz Golaszewski wrote:
From: Bartosz Golaszewski
We now have a proper clocksource driver for davinci. Switch the platform
to using it.
Signed-off-by: Bartosz Golaszewski
---
arch/arm/mach-davinci/da850.c | 56 ++-
1 file changed, 22 i
On 2/4/19 11:17 AM, Bartosz Golaszewski wrote:
From: Bartosz Golaszewski
We now have a proper clocksource driver for davinci. Switch the platform
to using it.
Signed-off-by: Bartosz Golaszewski
---
same comments as da850 patch
On 2/4/19 11:17 AM, Bartosz Golaszewski wrote:
From: Bartosz Golaszewski
Currently the clocksource and clockevent support for davinci platforms
lives in mach-davinci. It hard-codes many things, used global variables,
s/used/uses/
implements functionalities unused by any platform and has cod
Kees Cook writes:
> On Sun, Feb 3, 2019 at 12:39 AM Christian Brauner
> wrote:
>>
>> On Sat, Feb 02, 2019 at 09:49:38PM -1000, Jack Andersen wrote:
>> > The patch titled
>> > `signal: Never allocate siginfo for SIGKILL or SIGSTOP`
>> > created a regression for users of PTRACE_GETSIGINFO needing
On Mon, Feb 04, 2019 at 05:39:57PM -0600, Luis Chamberlain wrote:
> On Thu, Nov 29, 2018 at 8:31 PM Luis Chamberlain wrote:
> >
> > On Mon, Nov 26, 2018 at 09:12:16PM -0600, Dan Rue wrote:
> > > CONFIG_FW_LOADER_USER_HELPER_FALLBACK=y is required for fw_fallback.sh.
> > > Without it, fw_fallback.s
On Mon, Feb 4, 2019 at 6:33 PM Souptick Joarder wrote:
>
> Hi Dan,
>
> On Tue, Jan 15, 2019 at 4:00 AM Dan Williams wrote:
> >
> > On Mon, Jan 14, 2019 at 12:59 AM Jan Kara wrote:
> > >
> > > On Sat 05-01-19 00:54:11, Souptick Joarder wrote:
> > > > This code is converted to use vmf_error().
> >
Currently the only way to clear the mfc cache was to delete the entries
one by one using the MRT_DEL_MFC socket option or to destroy and
recreate the socket.
Create a new socket option which will clear the multicast forwarding
cache on the socket without destroying the socket.
Signed-off-by: Call
Created a way to clear the multicast forwarding cache on a socket
without having to either remove the entries manually using the delete
entry socket option or destroy and recreate the multicast socket.
Patch Set 2:
- Fix Compile Errors
Patch Set 3:
- Fix Style Errors
Callum Sinclair (1):
i
We were seeing unexplained segfaults in coreutils processes and other
basic utilities on systems with print-fatal-signals enabled:
[ 311.001986] potentially unexpected fatal signal 11.
[ 311.001993] CPU: 3 PID: 4565 Comm: tail Tainted: P O
4.9.100.Ar-8497547.eostrun
Thomas Gleixner writes:
> On Mon, 4 Feb 2019, Dmitry Vyukov wrote:
>
>> On Mon, Feb 4, 2019 at 10:27 AM Thomas Gleixner wrote:
>> >
>> > On Fri, 1 Feb 2019, Dmitry Vyukov wrote:
>> >
>> > > On Fri, Feb 1, 2019 at 5:48 PM Dmitry Vyukov wrote:
>> > > >
>> > > > Hello,
>> > > >
>> > > > The follow
Add documentation about how to probe the jz4740-codec driver from
devicetree.
Signed-off-by: Paul Cercueil
---
.../bindings/sound/ingenic,jz4740-codec.txt | 20
1 file changed, 20 insertions(+)
create mode 100644
Documentation/devicetree/bindings/sound/ingenic,jz4
Add support for probing the driver from devicetree.
Signed-off-by: Paul Cercueil
---
sound/soc/codecs/jz4740.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/sound/soc/codecs/jz4740.c b/sound/soc/codecs/jz4740.c
index af57a7d6ec12..b5a1323f0883 100644
--- a/sound/soc/codecs/jz4740.
Add documentation about how to probe the jz4725b-codec driver from
devicetree.
Signed-off-by: Paul Cercueil
---
.../bindings/sound/ingenic,jz4725b-codec.txt | 20
1 file changed, 20 insertions(+)
create mode 100644
Documentation/devicetree/bindings/sound/ingenic,jz
Add license information as a standard SPDX license notifier instead of
custom text.
Signed-off-by: Paul Cercueil
---
sound/soc/codecs/jz4740.c | 12 +++-
1 file changed, 3 insertions(+), 9 deletions(-)
diff --git a/sound/soc/codecs/jz4740.c b/sound/soc/codecs/jz4740.c
index 9395b583432c
Show the knob to enable or disable the jz4740-codec driver, add a
proper description, and add a dependency on MIPS || COMPILE_TEST, as
this driver is only useful on MIPS.
Signed-off-by: Paul Cercueil
---
sound/soc/codecs/Kconfig | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff
Add jz4725b-codec driver to support the internal CODEC found in the
JZ4725B SoC from Ingenic.
Signed-off-by: Paul Cercueil
---
sound/soc/codecs/Kconfig | 12 +
sound/soc/codecs/Makefile | 2 +
sound/soc/codecs/jz4725b.c | 599 +
3 files changed,
Colin,
> There are several issues with badly indented statements. Fix these and
> clean up the formatting.
Applied to 5.1/scsi-queue, thanks!
--
Martin K. Petersen Oracle Linux Engineering
Hi Greg,
After merging the staging tree, today's linux-next build (x86_64
allmodconfig) produced these warnings:
drivers/iio/chemical/sps30.c: In function 'sps30_read_raw':
drivers/iio/chemical/sps30.c:289:4: warning: this statement may fall through
[-Wimplicit-fallthrough=]
switch (chan->ch
On 2/4/19 5:22 PM, Qian Cai wrote:
> Booting up an arm64 server with CONFIG_VALIDATE_FS_PARSER=n triggers a
> out-of-bounds error below, due to the commit 2284cf59cbce ("hugetlbfs:
> Convert to fs_context") missed a terminator for hugetlb_param_specs[],
> and causes this loop in fs_lookup_key(),
>
On Sat, Dec 22, 2018 at 7:32 PM Colin King wrote:
>
> From: Colin Ian King
>
> Currently rdev is dereferenced when assigning desc before rdev is null
> checked, hence there is a potential null pointer dereference on rdev.
> Fix this by null checking rdev first.
>
> Detected by CoverityScan, CID#1
Joao,
> Currently I am managing the Synopsys drivers & tools team (full-time) and
> so I am passing the DWC UFS driver maintenance to Pedro Sousa.
Applied to 5.1/scsi-queue, thanks.
--
Martin K. Petersen Oracle Linux Engineering
> On Jan 31, 2019, at 5:00 AM, Peter Zijlstra wrote:
>
> On Wed, Jan 30, 2019 at 10:01:35PM -0500, Alex Kogan wrote:
>> Choose the next lock holder among spinning threads running on the same
>> socket with high probability rather than always. With small probability,
>> hand the lock to the firs
Suganath,
> Posting below patches to include new devices Ambrosia, Atlas.
Applied to 5.1/scsi-queue, thanks!
--
Martin K. Petersen Oracle Linux Engineering
Christoph,
> The only real user of the T10 OSD protocol, the pNFS object layout
> driver never went to the point of having shipping products, and we
> removed it 1.5 years ago. Exofs is just a simple example without real
> life users.
>
> The code has been mostly unmaintained for years and is g
On 04-Feb-19 11:04 PM, Thomas Gleixner wrote:
On Fri, 1 Feb 2019, Rajneesh Bhardwaj wrote:
Add CPUID of Icelake (ICL) mobile processors to Intel family list. The
Information related to ICL CPUID is referenced from below Coreboot
project link.
https://github.com/coreboot/coreboot/blob/5ebcea3
On Thursday, 31 January 2019 12:11:06 PM AEDT Andrea Arcangeli wrote:
> On Thu, Jan 31, 2019 at 06:30:22PM +0800, Peter Xu wrote:
> > The change_pte() notifier was designed to use as a quick path to
> > update secondary MMU PTEs on write permission changes or PFN changes.
> > For KVM, it could redu
Hi,
Since the V2 of my patchset I could test it on the JZ4740, and see
that the hardware is the exact same as on the JZ4725B.
As the JZ4740 is already fully upstream, and also older, I now add
support for the JZ4740 instead of the JZ4725B.
The only patches modified since v2 are the 1/4 and 4/4,
Add support for the JZ4740 SoC from Ingenic.
Signed-off-by: Paul Cercueil
Reviewed-by: Boris Brezillon
---
v2: No change
v3: Support the JZ4740 instead of the JZ4725B (exact same functionality
but JZ4740 is already fully upstream)
drivers/memory/jz4780-nemc.c | 24 +--
Depending on MACH_JZ4780 prevent us from creating a generic kernel that
works on more than one MIPS board. Instead, we just depend on MIPS being
set.
Signed-off-by: Paul Cercueil
Reviewed-by: Boris Brezillon
---
v2: No change
v3: No change
drivers/memory/Kconfig | 2 +-
1 file changed, 1 ins
Add a compatible string to support the memory controller built into the
JZ4740 SoC from Ingenic.
Signed-off-by: Paul Cercueil
Reviewed-by: Boris Brezillon
Reviewed-by: Rob Herring
---
v2: No change
v3: Change compatible string for jz4740 instead of j4725b
.../devicetree/bindings/memory-cont
The maximum value found in that array is 15, there's no need to store
these values as uint32_t, a uint8_t is enough.
Signed-off-by: Paul Cercueil
---
v2: Remove casts to uint32_t
v3: No change
drivers/memory/jz4780-nemc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/dri
Hi Bjorn,
Any comments?
Thanks,
Sundeep
On Wed, Jan 23, 2019 at 6:48 PM wrote:
>
> From: Subbaraya Sundeep
>
> As per the spec - ECN_Enhanced_Allocation_23_Oct_2014_Final
> and section 6.9.1.2, EA capability contains fixed secondary
> and subordinate bus numbers for type 1 functions.
> This pa
On Mon, Feb 04, 2019 at 03:04:10PM -0800, Andrew Morton wrote:
> On Mon, 4 Feb 2019 11:57:10 +1100 "Tobin C. Harding"
> wrote:
>
> > Here is v2 of the comments fixes [to single SLUB header file]
>
> Thanks. I think I'll put these into a single patch.
Awesome, thank you.
On Mon, Feb 04, 2019 at 03:18:48PM -0500, Nitesh Narayan Lal wrote:
> This patch includes the following:
> 1. Basic skeleton for the support
> 2. Enablement of x86 platform to use the same
>
> Signed-off-by: Nitesh Narayan Lal
> ---
> arch/x86/Kbuild | 2 +-
> arch/x86/kvm/Kconfig
On 2/4/19 5:48 PM, a...@linux-foundation.org wrote:
> The mm-of-the-moment snapshot 2019-02-04-17-47 has been uploaded to
>
>http://www.ozlabs.org/~akpm/mmotm/
>
> mmotm-readme.txt says
>
> README for mm-of-the-moment:
>
> http://www.ozlabs.org/~akpm/mmotm/
>
> This is a snapshot of my -mm
ebied...@xmission.com (Eric W. Biederman) writes:
> Thomas Gleixner writes:
>
>> On Mon, 4 Feb 2019, Dmitry Vyukov wrote:
>>
>>> On Mon, Feb 4, 2019 at 10:27 AM Thomas Gleixner wrote:
>>> >
>>> > On Fri, 1 Feb 2019, Dmitry Vyukov wrote:
>>> >
>>> > > On Fri, Feb 1, 2019 at 5:48 PM Dmitry Vyukov
Brian Norris writes:
> On Mon, Feb 4, 2019 at 8:43 AM Kalle Valo wrote:
>> Brian Norris wrote:
>>
>> > This reverts commit cfb353c0dc058bc1619cc226d3cbbda1f360bdd3.
>> >
>> > WCN3990 firmware does not yet implement this feature, and so it crashes
>> > like this:
>> >
>> > fatal error received
On 04-02-19, 11:09, Quentin Perret wrote:
> The Energy Model (EM) framework feeds interested subsystems (the
> scheduler/EAS as of now) with power costs provided by drivers. Yet, no
> driver is actually doing that upstream yet. This series updates a set of
> CPUFreq drivers in order to register pow
This patch set extends support of new IPROC PCIe host controller features
- Add CRS state check using controller register status flags
- Add 32bit outbound window mapping configuration
This patch set is based on Linux-5.0-rc2.
Changes from v1:
- Addressed Bjorn Helgaas comments.
- Removed s
Add configuration to support IPROC PCIe host controller outbound memory
window mapping with SOC address range inside 4GB boundary, which is 32 bit
AXI address.
Signed-off-by: Srinath Mannam
Signed-off-by: Abhishek Shah
Signed-off-by: Ray Jui
Reviewed-by: Scott Branden
Reviewed-by: Vikram Praka
This patch set extends support of new IPROC PCIe host controller features
- Add CRS check using controller register status flags
- Add 32bit outbound window mapping configuration
This patch set is based on Linux-5.0-rc2.
Changes from v1:
- Addressed Bjorn Helgaas comments.
- Removed set ord
In the current implementation, config read output data 0x0001 is
assumed as CRS completion. But sometimes 0x0001 can be a valid data.
IPROC PCIe host controller has a register to show config read request
status flags like SC, UR, CRS and CA. So that extra check is added to
confirm the CRS
On 04-02-19, 11:15, John Stultz wrote:
> On Mon, Feb 4, 2019 at 1:03 AM Vinod Koul wrote:
> >
> > On 24-01-19, 12:24, John Stultz wrote:
> > > This patch series is based on recent work by Tanglei Han, and
> > > adds support for hi3660 SoCs as found on the HiKey960 board,
> > > along with a few pat
On Tue, Nov 13, 2018 at 03:54:53PM +0200, Ville Syrjälä wrote:
> Hi Paul,
> After 4.20-rc1 some of my 32bit UP machines no longer reboot/shutdown.
> I bisected this down to commit 45975c7d21a1 ("rcu: Define RCU-sched
> API in terms of RCU for Tree RCU PREEMPT builds").
>
> I traced the hang into
>
Hi Marc,
On 04/02/19 11:12 PM, Marc Gonzalez wrote:
> This reverts commit 60f0187031c05e04cbadffb62f557d0ff3564490.
>
> Calling ufshcd_set_vccq_rail_unused hangs my system.
> It seems vccq is not *not* needed.
>
> Signed-off-by: Marc Gonzalez
> ---
AFAIK Samsung and Toshiba UFS devices does no
Hi all,
Today's linux-next merge of the akpm-current tree got a conflict in:
net/sctp/stream.c
between commit:
cfe4bd7a257f ("sctp: check and update stream->out_curr when allocating
stream_out")
from the net tree and commit:
2bd3fbb3ff23 ("sctp: convert to genradix")
from the akpm-cur
Reviewed-by: Subrahmanya Lingappa
On Tue, Jan 29, 2019 at 1:38 PM Z.q. Hou wrote:
>
> From: Hou Zhiqiang
>
> It's confused that R/W some registers by csr_readl()/csr_writel(),
> while others by read_paged_register()/write_paged_register().
> Actually the low 3KB of 4KB PCIe configure space ca
Zhiqiang,
On Tue, Jan 29, 2019 at 1:38 PM Z.q. Hou wrote:
>
> From: Hou Zhiqiang
>
> Just format the code without functionality change.
>
> Signed-off-by: Hou Zhiqiang
> Reviewed-by: Minghuan Lian
> ---
> V3:
> - No change
>
> drivers/pci/controller/pcie-mobiveil.c | 261 +---
Reviewed-by: Subrahmanya Lingappa
On Tue, Jan 29, 2019 at 1:38 PM Z.q. Hou wrote:
>
> From: Hou Zhiqiang
>
> This patch corrected the returned error number by convention,
> and removed a unnecessary error check.
>
> Signed-off-by: Hou Zhiqiang
> Reviewed-by: Minghuan Lian
> ---
> V3:
> - No
On 25-01-19, 15:45, Bjorn Andersson wrote:
> The Qualcomm PCIe2 PHY is a Synopsys based PCIe PHY found in a number of
> Qualcomm platforms, add a binding to describe this.
>
> Signed-off-by: Bjorn Andersson
> ---
> .../bindings/phy/qcom-pcie2-phy.txt | 40 +++
> 1 file
Hi all,
I am unable to execute make modules_install install.
I get the following error:
ln: target 'linux-00096-gd1aa1a8/source' is not a directory
Makefile:1281: recipe for target '_modinst_' failed
make[1]: *** [_modinst_] Error 1
Makefile:296: recipe for target '__build_one_by_one' failed
mak
Zhiqiang,
why are we removing multi-MSI support ?
what functionality this driver is not providing to support it ?
Thanks.
On Tue, Jan 29, 2019 at 1:38 PM Z.q. Hou wrote:
>
> From: Hou Zhiqiang
>
> The current code does not support multiple MSIs, so remove
> the corresponding flag from the msi_d
05.02.2019 4:29, Sowjanya Komatineni пишет:
> This patch adds DMA support for Tegra I2C.
>
> Tegra I2C TX and RX FIFO depth is 8 words. PIO mode is used for
> transfer size of the max FIFO depth and DMA mode is used for
> transfer size higher than max FIFO depth to save CPU overhead.
>
> PIO mode
On 25-01-19, 15:45, Bjorn Andersson wrote:
> The QCS404 has a PCIe2 PHY and a Qualcomm PCIe controller, add these to
> the platform dtsi and enable them for the EVB with the perst gpio
> and analog supplies defined.
>
> Signed-off-by: Bjorn Andersson
> ---
> arch/arm64/boot/dts/qcom/qcs404-evb.d
Reviewed-by: Subrahmanya Lingappa
On Tue, Jan 29, 2019 at 1:39 PM Z.q. Hou wrote:
>
> From: Hou Zhiqiang
>
> It should get PCI base address from the DT node property 'ranges'
> to setup MEM/IO outbound windows instead of always zero.
>
> Fixes: 9af6bcb11e12 ("PCI: mobiveil: Add Mobiveil PCIe Ho
05.02.2019 4:29, Sowjanya Komatineni пишет:
> This patch sorts all the include headers alphabetically for the
> I2C Tegra driver.
>
> Signed-off-by: Sowjanya Komatineni
Yours "Signed-off-by" should be that the last line of the commit message. Same
for the other patches.
> Acked-by: Thierry Re
Reviewed-by: Subrahmanya Lingappa
On Tue, Jan 29, 2019 at 1:39 PM Z.q. Hou wrote:
>
> From: Hou Zhiqiang
>
> As it won't delete any node in this iteration, replaced
> the function resource_list_for_each_entry_safe() with
> the resource_list_for_each_entry().
>
> Signed-off-by: Hou Zhiqiang
> R
Reviewed-by: Subrahmanya Lingappa
On Tue, Jan 29, 2019 at 1:39 PM Z.q. Hou wrote:
>
> From: Hou Zhiqiang
>
> As the .map_bus() use the WIN_NUM_0 for CFG transactions,
> it's better passing WIN_NUM_0 explicitly when initialize
> the CFG outbound window.
>
> Signed-off-by: Hou Zhiqiang
> Reviewe
Reviewed-by: Subrahmanya Lingappa
On Tue, Jan 29, 2019 at 1:39 PM Z.q. Hou wrote:
>
> From: Hou Zhiqiang
>
> The inbound windows have different register set with outbound windows.
> This patch change the MEM inbound window to the first one.
>
> Signed-off-by: Hou Zhiqiang
> Reviewed-by: Minghu
ZQ,
please correct the tab spacing of the macro definitions, otherwise its OK.
Reviewed-by: Subrahmanya Lingappa
On Tue, Jan 29, 2019 at 1:39 PM Z.q. Hou wrote:
>
> From: Hou Zhiqiang
>
> Outbound window routine:
> - Removed unused var definition and register read operations.
> - Added the u
ebied...@xmission.com (Eric W. Biederman) writes:
> ebied...@xmission.com (Eric W. Biederman) writes:
>
>> Thomas Gleixner writes:
>>
>>> On Mon, 4 Feb 2019, Dmitry Vyukov wrote:
>>>
On Mon, Feb 4, 2019 at 10:27 AM Thomas Gleixner wrote:
>
> On Fri, 1 Feb 2019, Dmitry Vyukov wrote
Reviewed-by: Subrahmanya Lingappa
On Tue, Jan 29, 2019 at 1:39 PM Z.q. Hou wrote:
>
> From: Hou Zhiqiang
>
> In the loop block, there is not code change the loop key,
> this patch updated the loop key by re-read the INTx status
> register.
>
> This patch also change to clear the handled INTx st
201 - 300 of 1302 matches
Mail list logo
