Hi Jonathan
On Sun, Jan 27, 2019 at 4:04 PM Jonathan Cameron wrote:
>
> On Sat, 26 Jan 2019 22:34:50 +0100
> Ricardo Ribalda Delgado wrote:
>
> > HI Jonathan
> >
> > Thanks for your review. I will make the changes and send it back to
> > you after testing it on Monday on real hardware.
> >
> > U
On Mon, Jan 28, 2019 at 03:22:09PM +0800, jckuo wrote:
> Hi Thierry,
>
> I think any non-zero return value of
> regulator_bulk_enable()/devm_regulator_bulk_get() means error.
>
> Thanks,
>
> JC
Theoretically I think only regulator_bulk_enable() could return a
positive value, but even so it neve
On Sat, Jan 26, 2019 at 08:36:14AM -0800, Guenter Roeck wrote:
> On 1/25/19 3:06 AM, Matti Vaittinen wrote:
> > +/* Max time we can set is 1 hour, 59 minutes and 59 seconds */
> > +#define WDT_MAX_MS ((2 * 60 * 60 - 1) * 1000)
> > +/* Minimum time is 1 second */
> > +#define WDT_MIN_MS 1000
> > +#d
On Fri, Jan 25, 2019 at 09:45:26AM +, Peng Fan wrote:
> Just have a question,
>
> Since vmalloc_to_page is ok for cma area, no need to take cma and per device
> cma into consideration right?
The CMA area itself it a physical memory region. If it is a non-highmem
region you can call virt_to
> On Wed, Jan 23, 2019 at 5:18 PM Andy Shevchenko
> wrote:
> >
> > On Mon, Jan 14, 2019 at 4:13 PM Guan Yung Tseng
> > wrote:
> > >
> > > Modified NI devices class to PCI_CLASS_COMMUNICATION_MULTISERIAL.
> > > The reason of doing this is because all NI multi port serial cards
> > > use PCI_CL
On 10.01.19 17:30, Greg Kroah-Hartman wrote:
On Thu, Jan 10, 2019 at 04:19:53PM +0100, Oleksij Rempel wrote:
My gut feel is that if somebody still cares deeply about serial line
latency, they should look at trying to see if they can do some of the
work directly without the bounce to the workq
>This way devfreq core ensures that all its devices will be set to safe
>operation points before reboot operation. There are board on which some
>aggressive power saving operation points are behind the capabilities of
>the bootloader to properly reset the hardware and boot the board. This
>way one
On Thu, Jan 24, 2019 at 10:51:51AM +0100, Joerg Roedel wrote:
> On Thu, Jan 24, 2019 at 09:42:21AM +0100, Christoph Hellwig wrote:
> > Yes. But more importantly it would fix the limit for all other block
> > drivers that set large segment sizes when running over swiotlb.
>
> True, so it would be
> > Some Posted-Interrupts from passthrough devices may be lost or
> > overwritten when the vCPU is in runnable state.
> >
> > The SN (Suppress Notification) of PID (Posted Interrupt Descriptor)
> > will be set when the vCPU is preempted (vCPU in KVM_MP_STATE_RUNNABLE
> > state but not running on p
> > The cursor must be set again after creating the primary surface.
> > Also drop the error message.
> > if (!bo->is_primary) {
> > - if (!same_shadow)
> > + if (!same_shadow) {
> > qxl_io_create_primary(qdev, 0, bo);
> > + qxl_primary
On Mon, Jan 28, 2019 at 10:00:35AM +0200, Matti Vaittinen wrote:
> On Sat, Jan 26, 2019 at 08:36:14AM -0800, Guenter Roeck wrote:
> > On 1/25/19 3:06 AM, Matti Vaittinen wrote:
> > > +/* Max time we can set is 1 hour, 59 minutes and 59 seconds */
> > > +#define WDT_MAX_MS ((2 * 60 * 60 - 1) * 1000)
On Mon, Jan 28, 2019 at 10:13:20AM +0300, Alexey Budankov wrote:
SNIP
> > ---
> > Alexey Budankov (4):
> > perf record: allocate affinity masks
> > perf record: bind the AIO user space buffers to nodes
> > perf record: apply affinity masks when reading mmap buffers
> > perf record: implem
On 27/01/2019 at 09:51, Axel Lin wrote:
> Fix below build error:
> drivers/regulator/mcp16502.c: In function ‘mcp16502_gpio_set_mode’:
> drivers/regulator/mcp16502.c:135:3: error: implicit declaration of function
> ‘gpiod_set_value’; did you mean ‘gpio_set_value’?
> [-Werror=implicit-function-dec
Masahiro Yamada writes:
> Currently, the Kbuild core manipulates header search paths in a crazy
> way [1].
>
> To fix this mess, I want all Makefiles to add explicit $(srctree)/ to
> the search paths in the srctree. Some Makefiles are already written in
> that way, but not all. The goal of this w
On Mon, Jan 28, 2019 at 09:05:30AM +0100, Oleksij Rempel wrote:
>
>
> On 10.01.19 17:30, Greg Kroah-Hartman wrote:
> > On Thu, Jan 10, 2019 at 04:19:53PM +0100, Oleksij Rempel wrote:
> > > > My gut feel is that if somebody still cares deeply about serial line
> > > > latency, they should look at
On Mon, 2019-01-28 at 10:21 +0200, Kalle Valo wrote:
> Masahiro Yamada writes:
>
> > Currently, the Kbuild core manipulates header search paths in a
> > crazy
> > way [1].
> >
> > To fix this mess, I want all Makefiles to add explicit $(srctree)/
> > to
> > the search paths in the srctree. Some
On Sun, 27 Jan 2019, Scott Bauer wrote:
On Tue, Jan 22, 2019 at 11:31:31PM +0100, David Kozub wrote:
David Kozub (8):
block: sed-opal: fix typos and formatting
block: sed-opal: close parameter list in cmd_finalize
block: sed-opal: unify cmd start
block: sed-opal: unify error handling of
On 2019/1/26 2:03, Thomas Gleixner wrote:
On Fri, 25 Jan 2019, Thomas Gleixner wrote:
On Wed, 23 Jan 2019, Thomas Gleixner wrote:
On Fri, 18 Jan 2019, Zhenzhong Duan wrote:
When a task is set for updating TIF_SPEC_IB throuth SECCOMP by others
and it's scheduled in the first time, a stale TIF
On Sun, Jan 27, 2019 at 10:34 PM Nikolay Aleksandrov
wrote:
>
> On 27/01/2019 22:26, syzbot wrote:
> > Hello,
> >
> > syzbot found the following crash on:
> >
> > HEAD commit:ba6069759381 Merge tag 'mmc-v5.0-rc2' of git://git.kernel...
> > git tree: upstream
> > console output: https://s
On 28/01/2019 07:41, Amit Kucheria wrote:
> All cpufreq drivers do similar things to register as a cooling device.
> Provide a cpufreq driver flag so drivers can just ask the cpufreq core
> to register the cooling device on their behalf. This allows us to get
> rid of duplicated code in the drivers
+Boris and Juergen who can also help getting it in
On 1/28/19 8:34 AM, Souptick Joarder wrote:
On Mon, Jan 14, 2019 at 4:08 PM Oleksandr Andrushchenko
wrote:
On 1/7/19 7:37 PM, Souptick Joarder wrote:
Remove duplicate header which is included twice.
Signed-off-by: Souptick Joarder
Reviewed
Hi everyone,
On Mon, Jan 28, 2019 at 01:20:37PM +0530, Jagan Teki wrote:
> On Fri, Jan 25, 2019 at 9:10 PM Maxime Ripard
> wrote:
> >
> > On Thu, Jan 24, 2019 at 11:28:01PM +0530, Jagan Teki wrote:
> > > The ov5640_try_frame_interval operation updates the FPS as per user
> > > input based on def
On 28/01/2019 07:41, Amit Kucheria wrote:
> All cpufreq drivers do similar things to register as a cooling device.
> Provide a cpufreq driver flag so drivers can just ask the cpufreq core
> to register the cooling device on their behalf. This allows us to get
> rid of duplicated code in the drivers
On 28/01/2019 07:41, Amit Kucheria wrote:
> Add the CPUFREQ_AUTO_REGISTER_COOLING_DEV flag to allow the cpufreq core
> to auto-register the driver as a cooling device.
>
> Signed-off-by: Amit Kucheria
> Reviewed-by: Matthias Kaehlcke
> Tested-by: Matthias Kaehlcke
> Reviewed-by: Stephen Boyd
Hi Malathi,
Bjorn has a patch adding all reserved memory
nodes from version 10 so you can probably drop
the venus_region node from the patch.
https://patchwork.kernel.org/patch/10774869/
On 2019-01-25 13:41, Malathi Gottam wrote:
This adds video nodes to sdm845 based on the examples
in the bin
On Sun, Jan 27, 2019 at 7:41 PM Reshetova, Elena
wrote:
>
> > On Mon, Jan 21, 2019 at 11:05:03AM -0500, Alan Stern wrote:
> > > On Mon, 21 Jan 2019, Peter Zijlstra wrote:
> >
> > > > Any additional ordering; like the one you have above; are not strictly
> > > > required for the proper functioning
On 28/01/2019 07:41, Amit Kucheria wrote:
> Use the CPUFREQ_AUTO_REGISTER_COOLING_DEV flag to allow cpufreq core to
> automatically register as a thermal cooling device.
>
> This allows removal of boiler plate code from the driver.
>
> Signed-off-by: Amit Kucheria
Reviewed-by: Daniel Lezcano
Hello Paul,
On 08/12/2015 17:42, Paul Moore wrote:
> To the best of our knowledge, everyone who enables audit at compile
> time also enables syscall auditing; this patch simplifies the Kconfig
> menus by removing the option to disable syscall auditing when audit
> is selected and the target arch s
Hi,
On 02/01/2019 13:55, Valentin Schneider wrote:
> The prototype of that function was already hoisted up in
>
> commit 3b1baa6496e6 ("sched/fair: Add 'group_misfit_task' load-balance
> type")
>
> but that seems to have been missed. Get rid of the extra prototype.
>
> Fixes: 2802bf3cd936 ("
On 28/01/2019 07:41, Amit Kucheria wrote:
> Use the CPUFREQ_AUTO_REGISTER_COOLING_DEV flag to allow cpufreq core to
> automatically register as a thermal cooling device.
>
> This allows removal of boiler plate code from the driver.
>
> Signed-off-by: Amit Kucheria
Reviewed-by: Daniel Lezcano
Hello Friend.
Please is this your personal email address? I have a confidential
matter to discuss with you.
Thanks,
Davies Douglas
On 28/01/2019 07:41, Amit Kucheria wrote:
> Use the CPUFREQ_AUTO_REGISTER_COOLING_DEV flag to allow cpufreq core to
> automatically register as a thermal cooling device.
>
> This allows removal of boiler plate code from the driver.
>
> Signed-off-by: Amit Kucheria
Reviewed-by: Daniel Lezcano
On Mon, 28 Jan 2019, Zhenzhong Duan wrote:
> On 2019/1/26 2:03, Thomas Gleixner wrote:
> > Bah, nonsense. Brain was clearly still out for lunch and I confused IBPB
> > and STIBP for a moment. cond_ibpb() is the thing issues in switch_mm() and
> > that is not leaving a stale MSR around because we on
On 28/01/2019 07:41, Amit Kucheria wrote:
> Use the CPUFREQ_AUTO_REGISTER_COOLING_DEV flag to allow cpufreq core to
> automatically register as a thermal cooling device.
>
> This allows removal of boiler plate code from the driver.
>
> Signed-off-by: Amit Kucheria
Reviewed-by: Daniel Lezcano
On 28/01/2019 07:41, Amit Kucheria wrote:
> Use the CPUFREQ_AUTO_REGISTER_COOLING_DEV flag to allow cpufreq core to
> automatically register as a thermal cooling device.
>
> This allows removal of boiler plate code from the driver.
>
> Signed-off-by: Amit Kucheria
> Acked-by: Sudeep Holla
Revi
On 28.01.2019 11:20, Jiri Olsa wrote:
> On Mon, Jan 28, 2019 at 10:13:20AM +0300, Alexey Budankov wrote:
>
> SNIP
>
>>> ---
>>> Alexey Budankov (4):
>>> perf record: allocate affinity masks
>>> perf record: bind the AIO user space buffers to nodes
>>> perf record: apply affinity masks when
On 28/01/2019 07:41, Amit Kucheria wrote:
> Use the CPUFREQ_AUTO_REGISTER_COOLING_DEV flag to allow cpufreq core to
> automatically register as a thermal cooling device.
>
> This allows removal of boiler plate code from the driver.
>
> Signed-off-by: Amit Kucheria
> Acked-by: Sudeep Holla
Revi
On Mon, Jan 28, 2019 at 09:55:23AM +0200, Oded Gabbay wrote:
> On Sun, Jan 27, 2019 at 8:49 AM Mike Rapoport wrote:
> >
> > On Fri, Jan 25, 2019 at 11:47:03PM +0200, Oded Gabbay wrote:
> > > On Wed, Jan 23, 2019 at 2:28 PM Mike Rapoport wrote:
> > > >
> > > > On Wed, Jan 23, 2019 at 02:00:47AM +0
On 2019/1/28 16:36, Thomas Gleixner wrote:
On Mon, 28 Jan 2019, Zhenzhong Duan wrote:
On 2019/1/26 2:03, Thomas Gleixner wrote:
Bah, nonsense. Brain was clearly still out for lunch and I confused IBPB
and STIBP for a moment. cond_ibpb() is the thing issues in switch_mm() and
that is not leaving
From: Martin Kepplinger
This adds myself as an author of the st1232 driver module as Tony's
email address doesn't seem to work anymore.
Signed-off-by: Martin Kepplinger
---
drivers/input/touchscreen/st1232.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/input/touchscreen/st1232.c
From: Martin Kepplinger
Add support for the Sitronix ST1633 touchscreen controller to the st1232
driver. A protocol spec can be found here:
www.ampdisplay.com/documents/pdf/AM-320480B6TZQW-TC0H.pdf
Signed-off-by: Martin Kepplinger
---
drivers/input/touchscreen/Kconfig | 6 +-
drivers/input/
From: Martin Kepplinger
The st1232 driver gains support for the ST1633 controller too; update
the bindings doc accordingly.
Signed-off-by: Martin Kepplinger
---
.../bindings/input/touchscreen/sitronix-st1232.txt | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git
Hi,
I have a new question concerning documentation.
https://www.kernel.org/doc/html/latest/driver-api/dmaengine/client.html
>From this document it is not really clear, at least to me, if clients can
consider valid the `struct dma_async_tx_descriptor` after submission to the
DMA engine.
Client
Hi Kai-Heng,
On 27/01/2019 05:56, Kai-Heng Feng wrote:
> Hi,
>
> We have a bug report [1] that the ipu3 doesn’t work.
> Does ipu3 need special userspace to work?
Yes, it will need further userspace support to configure the pipeline,
and to provide 3A algorithms for white balance, focus, and expo
Von: Martin Kepplinger [mart...@posteo.de]
Gesendet: Montag, 28. Jänner 2019 09:44
An: devicet...@vger.kernel.org; linux-in...@vger.kernel.org
Cc: dmitry.torok...@gmail.com; robh...@kernel.org; mark.rutl...@arm.com;
linux-kernel@vger.kernel.org; Kepplinger
Add a sysctl which asks the kernel to panic when any userspace process
receives a fatal signal which would trigger a core dump. This has
proven to be quite useful when debugging problems seen during testing of
embedded systems: When combined with kernel core dumps (saved due to
the panic), it all
On Fri, 2019-01-25 at 12:02 +0800, Wangyan Wang wrote:
> From: chunhui dai
>
> Due to a clerical error,there is one zero less for 1280.
> Fix it for 12800.
>
Reviewed-by: CK Hu
> Fixes: 0fc721b2968e ("drm/mediatek: add hdmi driver for MT2701 and MT7623")
> Signed-off-by: chunhui dai
Hello,
next-20190125
kcompactd0 is spinning on something, burning CPUs in the meantime:
%CPU TIME+ COMMAND
100.0 0.0 34:04.20 R [kcompactd0]
Not sure I know how to reproduce it; so am probably not going to
be a very helpful tester.
I tried to ftrace kcompactd0 PID, and I see
Hi,
On 26/01/2019 10:19, liwei (GF) wrote:
>
>
> On 2019/1/21 23:33, Julien Thierry wrote:
>> Implement NMI callbacks for GICv3 irqchip. Install NMI safe handlers
>> when setting up interrupt line as NMI.
>>
>> Only SPIs and PPIs are allowed to be set up as NMI.
>>
>> Signed-off-by: Julien Thier
Add CSI support for Allwinner A64. Here is previous series[1]
Changes for v8:
- update proper enable and disable sequnce for clk_mod
- fix warning for patch "media: sun6i: Add A64 CSI block support"
- collect Maxime Acked-by
Changes for v7:
- Drop quirk change, and add as suggusted by Maxime
- Use
Allwinner A64 CSI is a single channel time-multiplexed BT.656
protocol interface.
Add separate compatible string for A64 since it require explicit
change in sun6i_csi driver to update default CSI_SCLK rate.
Signed-off-by: Jagan Teki
Reviewed-by: Rob Herring
Acked-by: Maxime Ripard
---
Documen
Hi Rob,
On Sun, Jan 27, 2019 at 4:00 AM Rob Herring wrote:
> On Wed, Jan 23, 2019 at 9:33 AM Geert Uytterhoeven
> wrote:
> > On Tue, Dec 11, 2018 at 9:24 PM Rob Herring wrote:
> > > This adds the build infrastructure for checking DT binding schema
> > > documents and validating dts files using
Add dts node details for Allwinner A64 CSI controller.
A64 CSI has similar features as like in H3, but the CSI_SCLK
need to update it to 300MHz than default clock rate.
Signed-off-by: Jagan Teki
Acked-by: Maxime Ripard
---
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 20 +++
CSI block in Allwinner A64 has similar features as like in H3,
but the default CSI_SCLK rate cannot work properly to drive the
connected sensor interface.
The tested mod cock rate is 300 MHz and BSP vfe media driver is also
using the same rate. Unfortunately there is no valid information about
clo
On Fri, Jan 25, 2019 at 06:25:27PM +0100, Noralf Trønnes wrote:
>
>
> Den 18.01.2019 13.20, skrev Gerd Hoffmann:
> > Switch qxl over to the new generic fbdev emulation.
> >
> > Signed-off-by: Gerd Hoffmann
> > ---
> > drivers/gpu/drm/qxl/qxl_display.c | 7 ---
> > drivers/gpu/drm/qxl/qxl_d
Some camera modules have the SoC feeding a master clock to the sensor
instead of having a standalone crystal. This clock signal is generated
from the clock control unit and output from the CSI MCLK function of
pin PE1.
Add a pinmux setting for it for camera sensors to reference.
Signed-off-by: Ja
Bananapi M64 comes with an optional sensor based on the ov5640,
add support for it with below pin information.
- PE13, PE12 via i2c-gpio bitbanging
- CLK_CSI_MCLK as external clock
- PE1 as external clock pin muxing
- DLDO3 as AVDD supply
- ALDO1 as DOVDD supply
- ELDO3 as DVDD supply
- PE16 gpio
On Mon, Jan 28, 2019 at 7:44 AM Amit Kucheria wrote:
>
> All cpufreq drivers do similar things to register as a cooling device.
> Provide a cpufreq driver flag so drivers can just ask the cpufreq core
> to register the cooling device on their behalf. This allows us to get
> rid of duplicated code
On Mon, Jan 21, 2019 at 3:38 PM Ramon Fried wrote:
> Returning -EAGAIN is no longer supported by pin_config_group_set()
> since ad42fc6c8479 ("pinctrl: rip out the direct pinconf API")
>
> Remove the relevant section from the documentation.
>
> Signed-off-by: Ramon Fried
Patch applied!
Yours,
> -Original Message-
> From: Robin Murphy [mailto:robin.mur...@arm.com]
> Sent: 25 January 2019 15:14
> To: Shameerali Kolothum Thodi ;
> lorenzo.pieral...@arm.com
> Cc: jean-philippe.bruc...@arm.com; will.dea...@arm.com;
> mark.rutl...@arm.com; Guohanjun (Hanjun Guo) ;
> John Garry ; pa.
On Fri, Jan 25, 2019 at 8:54 AM Chen-Yu Tsai wrote:
>
> The PLL-MIPI clock is somewhat special as it has its own LDOs which
> need to be turned on for this PLL to actually work and output a clock
> signal.
>
> Add the 2 LDO enable bits to the gate bits.
>
> Fixes: 5690879d93e8 ("clk: sunxi-ng: Add
Hi Boris,
Boris Brezillon wrote on Sat, 26 Jan 2019
17:54:29 +0100:
> On Sat, 26 Jan 2019 07:48:50 -0600
> "Gustavo A. R. Silva" wrote:
>
> > Hey Boris,
> >
> > On 1/26/19 3:52 AM, Boris Brezillon wrote:
> > > On Fri, 25 Jan 2019 15:09:50 -0600
> > > "Gustavo A. R. Silva" wrote:
> > >
On Sat, Jan 26, 2019 at 6:07 PM Vladis Dronov wrote:
>
> Ring buffer implementation in hid_debug_event() and hid_debug_events_read()
> is strange allowing lost or corrupted data. After commit 717adfdaf147
> ("HID: debug: check length before copy_to_user()") it is possible to enter
> an infinite lo
On Tue, 08 Jan 2019 14:07:19 +,
Julien Thierry wrote:
>
> When using VHE, the host needs to clear HCR_EL2.TGE bit in order
> to interract with guest TLBs, switching from EL2&0 translation regime
> to EL1&0.
>
> However, some non-maskable asynchronous event could happen while TGE is
> cleared
On 26/01/19 18:49, Pavel Tatashin wrote:
> VMs may show incorrect uptime and dmesg printk offsets on hypervisors with
> unstable clock. The problem is produced when VM is rebooted without exiting
> from qemu.
>
> The fix is to calculate clock offset not only for stable clock but for
> unstable clo
On Sun 27-01-19 16:36:34, valdis.kletni...@vt.edu wrote:
> On Sun, 27 Jan 2019 17:00:27 +0100, Pavel Machek said:
> > > > I've noticed this as well on earlier kernels (next-20181224 to 20190115)
> > > > Some more info:
> > > > 1) echo 3 > /proc/sys/vm/drop_caches unwedges kcompactd in 1-3 seconds.
On 28/01/19 09:08, Kang, Luwei wrote:
>> However, you should at least change the comment in vcpu_enter_guest to
>> mention "before reading PIR" instead of "before reading
>> PIR.ON".
>
> Will do that. I think the "checking PIR.ON" should be PID.ON. I will fix it.
Yes.
>> Alternatively, would it
Add support for the Tegra210 timer that runs at oscillator clock
(TMR10-TMR13). We need these timers to work as clock event device and to
replace the ARMv8 architected timer due to it can't survive across the
power cycle of the CPU core or CPUPORESET signal. So it can't be a wake-up
source when CPU
On 1/28/19 9:57 AM, Sergey Senozhatsky wrote:
> Hello,
>
> next-20190125
>
> kcompactd0 is spinning on something, burning CPUs in the meantime:
Hi, could you check/add this to the earlier thread? Thanks.
https://lore.kernel.org/lkml/2019012625.GB27513@amd/T/#u
>
> %CPU TIME+
The Tegra210 timer provides fourteen 29-bit timer counters and one 32-bit
timestamp counter. The TMRs run at either a fixed 1 MHz clock rate derived
from the oscillator clock (TMR0-TMR9) or directly at the oscillator clock
(TMR10-TMR13). Each TMR can be programmed to generate one-shot periodic,
or
On 26/01/19 14:53, Greg Kroah-Hartman wrote:
> Ah, yes, sorry, I missed that. I'll respin the patch with this change
> in it in a few days.
Just drop this patch. I'll post the kvm_vm_ioctl_create_vcpu patch as a
replacement for this one and your other debugfs_create patch for virt/kvm.
Thanks,
On Mon, 21 Jan 2019 15:33:21 +,
Julien Thierry wrote:
>
> There are some helpers to modify PSR.[DAIF] bits that are not referenced
> anywhere. The less these bits are available outside of local_irq_*
> functions the better.
>
> Get rid of those unused helpers.
>
> Signed-off-by: Julien Thie
Add Ingenic X1000 serial support.
On 28.01.19 09:23, Greg Kroah-Hartman wrote:
On Mon, Jan 28, 2019 at 09:05:30AM +0100, Oleksij Rempel wrote:
On 10.01.19 17:30, Greg Kroah-Hartman wrote:
On Thu, Jan 10, 2019 at 04:19:53PM +0100, Oleksij Rempel wrote:
My gut feel is that if somebody still cares deeply about serial line
la
On Mon, 21 Jan 2019 15:33:22 +,
Julien Thierry wrote:
>
> It is not supported to have some CPUs using GICv3 sysreg CPU interface
> while some others do not.
>
> Once ICC_SRE_EL1.SRE is set on a CPU, the bit cannot be cleared. Since
> matching this feature require setting ICC_SRE_EL1.SRE, it
Add support for probing the 8250_ingenic driver on the
X1000 Soc from Ingenic.
Signed-off-by: Zhou Yanjie
---
Documentation/devicetree/bindings/serial/ingenic,uart.txt | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/serial/ingenic,uart.txt
Add support for probing the 8250_ingenic driver on the
X1000 Soc from Ingenic.
Signed-off-by: Zhou Yanjie
---
drivers/tty/serial/8250/8250_ingenic.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/tty/serial/8250/8250_ingenic.c
b/drivers/tty/serial/8250/8250_ingenic.c
in
On Mon, 21 Jan 2019 15:33:23 +,
Julien Thierry wrote:
>
> Add a cpufeature indicating whether a cpu supports masking interrupts
> by priority.
>
> The feature will be properly enabled in a later patch.
>
> Signed-off-by: Julien Thierry
> Reviewed-by: Suzuki K Poulose
> Reviewed-by: Mark R
> -Original Message-
> From: Robin Murphy [mailto:robin.mur...@arm.com]
> Sent: 25 January 2019 18:33
> To: Shameerali Kolothum Thodi ;
> lorenzo.pieral...@arm.com
> Cc: jean-philippe.bruc...@arm.com; will.dea...@arm.com;
> mark.rutl...@arm.com; Guohanjun (Hanjun Guo) ;
> John Garry ; pa.
On Mon, 21 Jan 2019 15:33:24 +,
Julien Thierry wrote:
>
> Add helper functions to access system registers related to interrupt
> priorities: PMR and RPR.
>
> Signed-off-by: Julien Thierry
> Reviewed-by: Mark Rutland
> Acked-by: Catalin Marinas
> Cc: Russell King
> Cc: Catalin Marinas
>
On Fri 25-01-19 11:15:08, Dan Williams wrote:
[...]
> However, we should consider this along with the userspace enabling to
> control which device-dax instances are set aside for hotplug. It would
> make sense to have a "clear errors before hotplug" configuration
> option.
I am not sure I understa
Hi Naga,
Naga Sureshkumar Relli wrote on Mon, 28 Jan 2019
06:04:53 +:
> Hi Boris & Miquel,
>
> Could you please provide your thoughts on this driver to support HW-ECC?
> As I said previously, there is no way to detect errors beyond N bit.
> I am ok to update the driver based on your inputs.
Hi, Wangyan:
How do you prove that this series would make mt7623 HDMI clock more
stable? By experience result? I would like to prove it by the source
code.
Does 'stable' means that hardware could generate the frequency most
close to the target frequency? If it does, I think you could compare the
On Sun, Jan 27, 2019 at 06:41:38PM +, Reshetova, Elena wrote:
> > On Mon, Jan 21, 2019 at 11:05:03AM -0500, Alan Stern wrote:
> > > On Mon, 21 Jan 2019, Peter Zijlstra wrote:
> > Yes, that's a very good suggestion.
> >
> > I suppose we can add smp_acquire__after_ctrl_dep() on the true branch.
Am Sonntag, den 27.01.2019, 23:08 -0700 schrieb Angus Ainslie (Purism):
> On i.mx8 mscale B0 chip, AHB/SDMA clock ratio 2:1 can't be supportted,
> since SDMA clock ratio has to be increased to 250Mhz, AHB can't reach
> to 500Mhz, so use 1:1 instead.
>
> Based on NXP commit MLK-16841-1 by Robin Gon
On Mon, Jan 28, 2019 at 05:19:35PM +0800, Zhou Yanjie wrote:
> Add support for probing the 8250_ingenic driver on the
> X1000 Soc from Ingenic.
>
> Signed-off-by: Zhou Yanjie
> ---
> drivers/tty/serial/8250/8250_ingenic.c | 10 ++
> 1 file changed, 10 insertions(+)
You sent two differen
On Mon, 21 Jan 2019 15:33:25 +,
Julien Thierry wrote:
>
> Mask the IRQ priority through PMR and re-enable IRQs at CPU level,
> allowing only higher priority interrupts to be received during interrupt
> handling.
>
> Signed-off-by: Julien Thierry
> Acked-by: Catalin Marinas
> Cc: Catalin Ma
Am Sonntag, den 27.01.2019, 23:08 -0700 schrieb Angus Ainslie (Purism):
> This is identical to the imx7d.
So it can be dropped and the i.MX8M DT should just specify the
"fsl,imx7d-sdma" as a fallback compatible for the SDMA codes.
If both the imx8m and imx7d compatible are present in the DT, we c
Am Sonntag, den 27.01.2019, 23:08 -0700 schrieb Angus Ainslie (Purism):
> On i.mx8mq, there are two sdma instances, and the common dma framework
> will get a channel dynamically from any available sdma instance whether
> it's the first sdma device or the second sdma device. Some IPs like
> SAI only
From: Wanpeng Li
Last year guys from huawei reported that the call of
memory_global_dirty_log_start/stop()
takes 13s for 4T memory and cause guest freeze too long which increases the
unacceptable
migration downtime. [1] [2]
Guangrong pointed out:
| collapsible_sptes zaps 4k mappings to make
Hi Miquel,
> -Original Message-
> From: Miquel Raynal [mailto:miquel.ray...@bootlin.com]
> Sent: Monday, January 28, 2019 2:58 PM
> To: Naga Sureshkumar Relli
> Cc: r...@kernel.org; marek.va...@gmail.com; rich...@nod.at;
> martin.lund@keep-it-
> simple.com; linux-kernel@vger.kernel.org;
On Wed, 2019-01-23 at 06:58:27 UTC, YueHaibing wrote:
> Fix a static code checker warning:
> drivers/mtd/devices/docg3.c:1875
> doc_probe_device() warn: passing zero to 'ERR_PTR'
>
> Fixes: ae9d4934b2d7 ("mtd: docg3: add multiple floor support")
> Signed-off-by: YueHaibing
> Acked-by: Robert Jar
On Sat, Jan 26, 2019 at 2:54 AM Maxime Ripard wrote:
>
> On Fri, Jan 25, 2019 at 01:28:49AM +0530, Jagan Teki wrote:
> > Minimum PLL used for MIPI is 500MHz, as per manual, but
> > lowering the min rate by 300MHz can result proper working
> > nkms divider with the help of desired dclock rate from
On Fri, 2019-01-25 at 02:12:42 UTC, YueHaibing wrote:
> In case DOC_CHIPID_G3, mtd->name is not freed in err handling path,
> which is alloced by kasprintf(). Fix this by using devm_kasprintf().
>
> Fixes: ae9d4934b2d7 ("mtd: docg3: add multiple floor support")
> Signed-off-by: YueHaibing
Applie
On Mon, 21 Jan 2019 15:33:26 +,
Julien Thierry wrote:
>
> Introduce fixed values for PMR that are going to be used to mask and
> unmask interrupts by priority.
>
> The current priority given to GIC interrupts is 0xa0, so clearing PMR's
> most significant bit is enough to mask interrupts.
>
On Mon, 21 Jan 2019 15:33:27 +,
Julien Thierry wrote:
>
> In order to replace PSR.I interrupt disabling/enabling with ICC_PMR_EL1
> interrupt masking, ICC_PMR_EL1 needs to be saved/restored when
> taking/returning from an exception. This mimics the way hardware saves
> and restores PSR.I bit
L1 tables are allocated with __get_dma_pages, and therefore already
ignored by kmemleak.
Without this, the kernel would print this error message on boot,
when the first L1 table is allocated:
[2.810533] kmemleak: Trying to color unknown object at 0xffd652388000
as Black
[2.818190] CP
On Sun, 27 Jan 2019 18:21:42 -0800
Randy Dunlap wrote:
> From: Randy Dunlap
>
> Fix kernel-doc warnings in drivers/mtd/nand/raw:
>
> ../drivers/mtd/nand/raw/nand_base.c:420: warning: Function parameter or
> member 'chip' not described in 'nand_fill_oob'
> ../drivers/mtd/nand/raw/nand_bbt.c:17
Hi Rob,
On Tue, Dec 11, 2018 at 9:24 PM Rob Herring wrote:
> This adds the build infrastructure for checking DT binding schema
> documents and validating dts files using the binding schema.
>
> Check DT binding schema documents:
> make dt_binding_check
>
> Build dts files and check using DT bindi
On Mon, 21 Jan 2019 15:33:28 +,
Julien Thierry wrote:
>
> CPU does not received signals for interrupts with a priority masked by
> ICC_PMR_EL1. This means the CPU might not come back from a WFI
> instruction.
>
> Make sure ICC_PMR_EL1 does not mask interrupts when doing a WFI.
>
> Since the
1 - 100 of 2154 matches
Mail list logo
