Dan
Thanks for the insights!
Can I say, the UCE is delivered from h/w to OS in a single way in case of
machine
check, only PMEM/DAX stuff filter out UC address and managed in its own way by
badblocks, if PMEM/DAX doesn't do so, then common RAS workflow will kick in,
right?
And how about when AR
Paul,
On Thu, Jan 24, 2019 at 10:41 PM Paul Cercueil wrote:
>
> Hi Mathieu,
>
> Le jeu. 24 janv. 2019 à 18:26, Mathieu Malaterre a
> écrit :
> > Paul,
> >
> > On Wed, Dec 12, 2018 at 11:09 PM Paul Cercueil
> > wrote:
> >>
> >> Hi,
> >>
> >> Here's the version 8 and hopefully final version of
Hi Max,
On Fri, Jan 25, 2019 at 3:58 AM Max Filippov wrote:
> CONFIG_HAVE_FUTEX_CMPXCHG is currently used to determine if
> atomic_inatomic is always working or must be probed. For most
> architectures it is either selected, or it is known that they always
> have futex_atomic_cmpxchg_inatomic wor
On Thu, Jan 24, 2019 at 11:33 PM Ricardo Ribalda Delgado
wrote:
>
> Add support for ADS7866, ADS7867 and ADS7868 8/10/12 bit Single channel
> ADC.
>
> Datasheet: http://www.ti.com/product/ADS7866
> Datasheet: http://www.ti.com/product/ADS7867
> Datasheet: http://www.ti.com/product/ADS7868
>
> Sign
This patch adds posix acl (Access Control Lists) support to squashfs-tools.
Signed-off-by: Geliang Tang
---
squashfs-tools/read_xattrs.c | 2 ++
squashfs-tools/squashfs_fs.h | 12 +++-
2 files changed, 9 insertions(+), 5 deletions(-)
diff --git a/squashfs-tools/read_xattrs.c b/squashfs
Add posix acl (Access Control Lists) support for squashfs, which is
marked as a todo item in squashfs documentation. This patch implements
a squashfs_get_acl function to read the file's acl information from its
xattr lists.
Signed-off-by: Geliang Tang
---
Documentation/filesystems/squashfs.txt
When we use mksquashfs tool to create a squashfs image from the files which
have POSIX ACLs(Access Control Lists), we get these errors:
Unrecognised xattr prefix system.posix_acl_access
Unrecognised xattr prefix system.posix_acl_default
This patcheset adds posix acl support to squashfs to fix thi
On Fri 25-01-19 09:19:24, Michal Hocko wrote:
> On Fri 25-01-19 08:37:04, Michal Hocko wrote:
> > On Fri 25-01-19 17:48:32, Linus Torvalds wrote:
> > > [ Just adding a lot of other people to the cc ]
> > >
> > > Robert, could you add a dmesg of a successful boot to that bugzilla,
> > > or just as
Hi Alex,
On 1/25/19 9:46 AM, Alexandre Courbot wrote:
> On Thu, Jan 17, 2019 at 8:58 PM Stanimir Varbanov
> wrote:
>>
>> Hi Malathi,
>>
>> On 12/20/18 9:47 AM, Malathi Gottam wrote:
>>> This adds video nodes to sdm845 based on the examples
>>> in the bindings.
>>>
>>> Signed-off-by: Malathi Gotta
Hi,
On Thu, Jan 24, 2019 at 04:07:41PM +, Russell King - ARM Linux admin wrote:
> On Thu, Jan 24, 2019 at 04:51:37PM +0100, Andrew Lunn wrote:
> > On Thu, Jan 24, 2019 at 02:18:03PM +0100, Thomas Bogendoerfer wrote:
> > >
> > > Fixes: 4bb043262878 ("net: mvpp2: phylink support")
> > > Signed-
Hi Jean-Philippe,
On 1/11/19 7:16 PM, Jean-Philippe Brucker wrote:
> On 08/01/2019 10:26, Eric Auger wrote:
>> From: Jacob Pan
>>
>> In virtualization use case, when a guest is assigned
>> a PCI host device, protected by a virtual IOMMU on a guest,
>> the physical IOMMU must be programmed to be c
On Fri, Jan 25, 2019 at 04:27:47PM +0800, Geliang Tang wrote:
> --- /dev/null
> +++ b/fs/squashfs/acl.c
> @@ -0,0 +1,69 @@
> +/*
> + * Squashfs - a compressed read only filesystem for Linux
No SPDX line?
> + *
> + * Copyright (c) 2018
> + * Phillip Lougher
Did Phillip write this file, or did yo
On Thu, Jan 24, 2019 at 11:22:54PM +0530, Jagan Teki wrote:
> Amarula A64 Relic has STLM75 sensor for digital temperature
> and thermal watchdog.
>
> Add support for it.
>
> Signed-off-by: Jagan Teki
> ---
> Note: the respective driver change is already in mainline
> https://git.kernel.org/pub/s
On Thu 24-01-19 13:23:28, Johannes Weiner wrote:
> On Thu, Jan 24, 2019 at 06:01:17PM +0100, Michal Hocko wrote:
> > On Thu 24-01-19 11:00:10, Johannes Weiner wrote:
> > [...]
> > > We cannot fully eliminate a risk for regression, but it strikes me as
> > > highly unlikely, given the extremely youn
On Thu, 24 Jan 2019 at 15:01, Alex Deucher wrote:
>
> On Thu, Jan 24, 2019 at 9:00 AM Ard Biesheuvel
> wrote:
> >
> > On Thu, 24 Jan 2019 at 13:31, Koenig, Christian
> > wrote:
> > >
> > > Am 24.01.19 um 13:06 schrieb Ard Biesheuvel:
> > > > The DRM driver stack is designed to work with cache co
On Tue, Jan 22, 2019 at 04:21:00PM +0100, Greg Kroah-Hartman wrote:
> When calling debugfs functions, there is no need to ever check the
> return value. The function can work or not, but the code logic should
> never do something different based on this.
>
> Cc: Martin Schwidefsky
> Cc: Heiko Ca
On Tue, Jan 22, 2019 at 04:21:02PM +0100, Greg Kroah-Hartman wrote:
> When calling debugfs functions, there is no need to ever check the
> return value. The function can work or not, but the code logic should
> never do something different based on this.
>
> Cc: Martin Schwidefsky
> Cc: Heiko Ca
On 22.01.19 11:37, Oscar Salvador wrote:
> Hi,
>
> this is the v2 of the first RFC I sent back then in October [1].
> In this new version I tried to reduce the complexity as much as possible,
> plus some clean ups.
>
> [Testing]
>
> I have tested it on "x86_64" (small/big memblocks) and on "powe
Hi Jean-Philippe,
On 1/25/19 9:39 AM, Auger Eric wrote:
> Hi Jean-Philippe,
>
> On 1/11/19 7:16 PM, Jean-Philippe Brucker wrote:
>> On 08/01/2019 10:26, Eric Auger wrote:
>>> From: Jacob Pan
>>>
>>> In virtualization use case, when a guest is assigned
>>> a PCI host device, protected by a virtua
On 1/25/19 12:17 AM, Jisheng Zhang wrote:
Hi,
On Fri, 25 Jan 2019 00:04:25 -0800 Guenter Roeck wrote:
Hi,
On 1/24/19 11:52 PM, Jisheng Zhang wrote:
Use devm_watchdog_register_device() to simplify the code.
Signed-off-by: Jisheng Zhang
---
drivers/watchdog/dw_wdt.c | 3 +--
1 file chan
On 1/24/19 11:57 PM, Jisheng Zhang wrote:
When switch to watchdog infrastructure, pr_* usage is removed, so
there's no any users of the pr_fmt, remove it.
Signed-off-by: Jisheng Zhang
Reviewed-by: Guenter Roeck
---
drivers/watchdog/dw_wdt.c | 2 --
1 file changed, 2 deletions(-)
diff -
> > I suppose we can add smp_acquire__after_ctrl_dep() on the true branch.
> > Then it reall does become rel_acq.
> >
> > A wee something like so (I couldn't find an arm64 refcount, even though
> > I have distinct memories of talk about it).
>
> In the end, arm and arm64 chose to use REFCOUNT_FULL
On Tue, Jan 22, 2019 at 04:26:12PM +0100, Jiri Slaby wrote:
> On 22. 01. 19, 16:23, Greg KH wrote:
> > On Tue, Jan 22, 2019 at 04:11:59PM +0100, Jiri Slaby wrote:
> >> Convert SISUSB_VADDR and SISUSB_HADDR to inline functions. Now, there
> >> are no more hidden accesses to local variables (vc_data
On Thu, Jan 17, 2019 at 05:54:32PM +0100, Loys Ollivier wrote:
> Add binding for Mediatek-based GNSS receivers.
>
> Signed-off-by: Loys Ollivier
> ---
>
> v2:
> Renamed bindings from Globaltop/gtop to Mediatek/mtk.
> Moved current-speed as an optional propertie.
> Removed the status line in the
On Thu, Jan 17, 2019 at 05:54:33PM +0100, Loys Ollivier wrote:
> Add an MTK (Mediatek) type to the "GNSS_TYPE" attribute.
>
> Note that MTK receivers support a subset of NMEA 0183 with vendor
> extensions (e.g. to allow switching to the vendor protocol).
Copy paste error? AFAICT there is no Media
Add posix acl (Access Control Lists) support for squashfs, which is
marked as a todo item in squashfs documentation. This patch implements
a squashfs_get_acl function to read the file's acl information from its
xattr lists.
Signed-off-by: Geliang Tang
---
Changes in v5:
- add SPDX lines.
---
When we use mksquashfs tool to create a squashfs image from the files which
have POSIX ACLs(Access Control Lists), we get these errors:
Unrecognised xattr prefix system.posix_acl_access
Unrecognised xattr prefix system.posix_acl_default
This patcheset adds posix acl support to squashfs to fix thi
This patch adds posix acl (Access Control Lists) support to squashfs-tools.
Signed-off-by: Geliang Tang
---
squashfs-tools/read_xattrs.c | 2 ++
squashfs-tools/squashfs_fs.h | 12 +++-
2 files changed, 9 insertions(+), 5 deletions(-)
diff --git a/squashfs-tools/read_xattrs.c b/squashfs
On Thu, Jan 24, 2019 at 2:19 PM Javier González wrote:
>
> > On 22 Jan 2019, at 11.15, h...@owltronix.com wrote:
> >
> > From: Hans Holmberg
> >
> > pblk_line_meta_free might sleep (it can end up calling vfree, depending
> > on how we allocate lba lists), and this can lead to a BUG()
> > if we wa
Hi David,
On 16/01/2019 at 10:57, Nicolas Ferre wrote:
> Add a new compatibility string for this product. It's using
> at91sam9260-macb layout but has a newer hardware revision: it's safer
> to use its own string.
>
> Signed-off-by: Nicolas Ferre
I'm thinking of pushing this patch with the othe
On 2019/1/25 上午11:00, Michael S. Tsirkin wrote:
On Thu, Jan 24, 2019 at 12:07:54PM +0800, Jason Wang wrote:
Meanwhile, could you pls post data comparing this last patch with the
below? This removes the speculation barrier replacing it with a
(useless but at least more lightweight) data depend
Hi Alex,
On 1/11/19 7:43 PM, Alex Williamson wrote:
> On Tue, 8 Jan 2019 11:26:13 +0100
> Eric Auger wrote:
>
>> From: Jacob Pan
>>
>> In virtualization use case, when a guest is assigned
>> a PCI host device, protected by a virtual IOMMU on a guest,
>> the physical IOMMU must be programmed to
Hi Wolfram,
> -Original Message-
> From: Wolfram Sang [mailto:w...@the-dreams.de]
> Sent: Wednesday, January 23, 2019 12:52 AM
>
> On Wed, Jan 16, 2019 at 01:28:54PM +0200, Laurentiu Tudor wrote:
> > Use the correct error pointer when extracting the error code.
> >
> > Fixes: ea1e5f176e97
According to the Schematic, the hardware of ci20 leads to uart3,
but not to uart2. Uart2 is miswritten in the original code.
Signed-off-by: Zhou Yanjie
---
arch/mips/boot/dts/ingenic/ci20.dts | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/mips/boot/dts/ingenic/c
On 2019/1/25 上午11:03, Michael S. Tsirkin wrote:
On Wed, Jan 23, 2019 at 05:55:57PM +0800, Jason Wang wrote:
It was noticed that the copy_user() friends that was used to access
virtqueue metdata tends to be very expensive for dataplane
implementation like vhost since it involves lots of softwar
> -Original Message-
> From: Robin Murphy [mailto:robin.mur...@arm.com]
> Sent: 24 January 2019 18:25
> To: Andrew Murray ; Shameerali Kolothum Thodi
>
> Cc: lorenzo.pieral...@arm.com; mark.rutl...@arm.com;
> vkil...@codeaurora.org; neil.m.lee...@gmail.com;
> jean-philippe.bruc...@arm.co
On 2019/1/25 上午11:03, Michael S. Tsirkin wrote:
+/* Suppress the vma that needs writeback since we can not track dirty
+ * pages now.
+ */
+static bool vma_can_vmap(struct vm_area_struct *vma)
+{
+ return vma_is_anonymous(vma) || is_vm_hugetlb_page(vma) ||
+ vma_is_shmem(vma)
Hi Jaroslav,
On Thu, 24 Jan 2019 at 21:43, Jaroslav Kysela wrote:
>
> Dne 23.1.2019 v 13:46 Leo Yan napsal(a):
> > Hi all,
> >
> > On Wed, Jan 23, 2019 at 12:58:51PM +0100, Takashi Iwai wrote:
> >> On Tue, 22 Jan 2019 21:25:35 +0100,
> >> Mark Brown wrote:
> >>>
> >>> On Mon, Jan 21, 2019 at 03:15
On Thu, Jan 17, 2019 at 05:54:34PM +0100, Loys Ollivier wrote:
> Add driver for serial-connected Mediatek-based GNSS receivers.
>
> These devices typically boot transmitting vendor specific NMEA output
> sequences. The serial port bit rate is read from the device tree
> "current-speed".
>
> Note
On Wed, Jan 16, 2019 at 04:32:43PM -0800, Rick Edgecombe wrote:
> From: Nadav Amit
>
> text_mutex is currently expected to be held before text_poke() is
> called, but we kgdb does not take the mutex, and instead *supposedly*
> ensures the lock is not taken and will not be acquired by any other co
Am Donnerstag, den 24.01.2019, 19:55 -0700 schrieb Angus Ainslie (Purism):
> On i.mx8mq, there are two sdma instances, and the common dma framework
> will get a channel dynamically from any available sdma instance whether
> it's the first sdma device or the second sdma device. Some IPs like
> SAI o
Am Donnerstag, den 24.01.2019, 19:55 -0700 schrieb Angus Ainslie (Purism):
> This is identical to the imx7d data structures but we need to
> be able to differentiate that the imx8mq has 2 sdma controllers.
No, we don't, see comment on patch 4/5. This can reuse the imx7d data.
Regards,
Lucas
> Si
> On 25 Jan 2019, at 10.15, Hans Holmberg
> wrote:
>
> On Thu, Jan 24, 2019 at 2:19 PM Javier González wrote:
>>> On 22 Jan 2019, at 11.15, h...@owltronix.com wrote:
>>>
>>> From: Hans Holmberg
>>>
>>> pblk_line_meta_free might sleep (it can end up calling vfree, depending
>>> on how we all
Am Donnerstag, den 24.01.2019, 19:55 -0700 schrieb Angus Ainslie (Purism):
> Add the sdma nodes to the base devicetree for the imx8mq
>
> Signed-off-by: Angus Ainslie (Purism)
One nit below, with that fixed:
Reviewed-by: Lucas Stach
You might need to split this patch out from the series and s
Am Donnerstag, den 24.01.2019, 19:55 -0700 schrieb Angus Ainslie (Purism):
> The imx8mq is a slightly different variant on the imx7d
Not really AFAICS, but it's good to document the used compatibles
anyways, so:
Reviewed-by: Lucas Stach
> Signed-off-by: Angus Ainslie (Purism)
> ---
> Document
Hello.
syzbot is hitting use-after-free bug in uinput module. It seems that
syzbot is hitting this bug from cdev_put() path when closing a character
file. But since I can't reproduce the problem, I used a debug patch which
raises the refcount as if the character device file is open()ed before
uinp
Am Donnerstag, den 24.01.2019, 19:55 -0700 schrieb Angus Ainslie (Purism):
> On i.mx8 mscale B0 chip, AHB/SDMA clock ratio 2:1 can't be supportted,
> since SDMA clock ratio has to be increased to 250Mhz, AHB can't reach
> to 500Mhz, so use 1:1 instead.
>
> > Based on NXP commit MLK-16841-1 by Robi
Hi Bjorn,
Thank you, Please see my comments below inline.
On Fri, Jan 25, 2019 at 1:01 AM Bjorn Helgaas wrote:
>
> On Thu, Jan 24, 2019 at 02:10:18PM +0530, Srinath Mannam wrote:
> > On Fri, Jan 18, 2019 at 8:37 PM Bjorn Helgaas wrote:
> > > On Fri, Jan 18, 2019 at 09:53:21AM +0530, Srinath Man
On Fri, Jan 25, 2019 at 11:23:03AM +0800, Chen-Yu Tsai wrote:
> Hi everyone,
>
> This series enables the display pipeline on the Allwinner A23 SoC.
> A few fixes are included for corner cases when the frontend isn't
> enabled.
>
> The A23 display pipeline is very much the same as the A33, except
Hi,
> -Original Message-
> From: h...@infradead.org [mailto:h...@infradead.org]
> Sent: 2019年1月24日 5:14
> To: Stefano Stabellini
> Cc: h...@infradead.org; Peng Fan ; m...@redhat.com;
> jasow...@redhat.com; xen-de...@lists.xenproject.org;
> linux-remotep...@vger.kernel.org; linux-kernel@vg
Web de correo electrónico de administración de notificaciones
Este mensaje es de nuestro centro de mensajería Web Admin a todos nuestros
propietarios de cuentas de correo electrónico. Estamos eliminando el acceso a
todos nuestros clientes de correo web. Su cuenta de correo electrónico se
actual
Web de correo electrónico de administración de notificaciones
Este mensaje es de nuestro centro de mensajería Web Admin a todos nuestros
propietarios de cuentas de correo electrónico. Estamos eliminando el acceso a
todos nuestros clientes de correo web. Su cuenta de correo electrónico se
actual
On Thu, Jan 24, 2019 at 01:48:39PM +, Mans Rullgard wrote:
> The QFN28 package version of the CP2102N has three additional gpio pins.
> Add support for these.
>
> Signed-off-by: Mans Rullgard
Thanks for investigating and enabling support for the remaining pins.
Now applied.
Johan
This patch introduces callback of .setup_affinity into 'struct
irq_affinity', so that:
1) allow drivers to customize the affinity for managed IRQ, for
example, now NVMe has special requirement for read queues & poll
queues
2) 6da4b3ab9a6e9 ("genirq/affinity: Add support for allocating interrupt s
Hi,
The current support for allocating interrupt sets requires that same 'max_vec'
and 'min_vec' is passed to pci_alloc_irq_vectors_affinity(), then driver has to
try to allocate again and again until it succeeds.
This patch introduces .setup_affinity callback, and we can use it to
re-caculate in
Now allocating interrupt sets can be done via .setup_affinity()
easily, so remove the support for allocating interrupt sets.
With this change, we don't need the limit of 'minvec == maxvec'
any more in pci_alloc_irq_vectors_affinity().
Meantime irq_create_affinity_masks() gets simplified a lot.
S
'node_to_cpumask' is just one temparay variable for irq_build_affinity_masks(),
so move it into irq_build_affinity_masks().
No functioanl change.
Signed-off-by: Ming Lei
---
kernel/irq/affinity.c | 27 +--
1 file changed, 13 insertions(+), 14 deletions(-)
diff --git a/k
Use the callback of .setup_affinity() to re-caculate number
of queues, and build irqs affinity with help of irq_build_affinity().
Then nvme_setup_irqs() gets simplified a lot.
Signed-off-by: Ming Lei
---
drivers/nvme/host/pci.c | 97 -
1 file chan
Drivers may use this API to build customized irq affinity, one example
is NVMe, which needs to build multiple irq sets, on each of which all
CPUs are spread.
Signed-off-by: Ming Lei
---
include/linux/interrupt.h | 12
kernel/irq/affinity.c | 27 +++
2 fil
The user might apply a specific switch configuration, with specific
forwarding rules, VLAN, bridges, etc.
During suspend to RAM the switch power will be turned off and the
switch will lost its configuration. In an attempt to bring S2RAM
support to the mv88e6xxx DSA, let's first save these rules in
After a first attempt of bringing S2RAM support to the DSA switch, it
has been reported that a part of the configuration was lost during the
cycle. This second version adds a first patch that saves the rules in
a per-chip list when they are applied, so that in the second patch we
bring S2RAM suppor
Bring S2RAM support to the mv88e6xxx DSA driver.
The content of the *_irq_poll() helper is moved in *_do_irq_poll() so
that that the function can be called from the ->resume() callback
without using the *work pointer.
Signed-off-by: Miquel Raynal
---
Changes since v1:
=
* Added
On Fri, Jan 25, 2019 at 05:53:42PM +0800, Ming Lei wrote:
> Hi,
>
> The current support for allocating interrupt sets requires that same 'max_vec'
> and 'min_vec' is passed to pci_alloc_irq_vectors_affinity(), then driver has
> to
> try to allocate again and again until it succeeds.
>
> This pat
On 01/24/2019 10:07 PM, Catalin Marinas wrote:
> Hi Shijith,
>
> On Thu, Jan 24, 2019 at 07:00:42AM +, Shijith Thotton wrote:
>> On 01/23/2019 11:45 PM, Catalin Marinas wrote:
>>> diff --git a/arch/arm64/mm/flush.c b/arch/arm64/mm/flush.c
>>> index 30695a868107..5c9073bace83 100644
>>> --- a/
Hi Alexandru
On Fri, Jan 25, 2019 at 9:29 AM Alexandru Ardelean
wrote:
>
> On Thu, Jan 24, 2019 at 11:33 PM Ricardo Ribalda Delgado
> wrote:
> >
> > Add support for ADS7866, ADS7867 and ADS7868 8/10/12 bit Single channel
> > ADC.
> >
> > Datasheet: http://www.ti.com/product/ADS7866
> > Datasheet
Ring buffer implementation in hid_debug_event() and hid_debug_events_read()
is strange allowing lost or corrupted data. After commit 717adfdaf147
("HID: debug: check length before copy_to_user()") it is possible to enter
an infinite loop in hid_debug_events_read() by providing 0 as count, this
lock
On Fri, Jan 18, 2019 at 11:41:00PM +0300, Vitaly Chikunov wrote:
>
> a) RSA verify works differently (is it just disguised encrypt),
> b) We have separate wrapper module for it (pkcs1pad). Thus:
>
> Old API can not be removed. In other words, we can not replace
> .verify_rsa with .verify in these
It is a driver for Texas Instruments Dual, 12-Bit Serial Input
Digital-to-Analog Converter.
Datasheet of this chip:
http://www.ti.com/lit/ds/sbas106/sbas106.pdf
Signed-off-by: Ricardo Ribalda Delgado
---
v2: Fix range
MAINTAINERS | 6 ++
drivers/iio/dac/Kconfig | 10 ++
Add support for ADS7866, ADS7867 and ADS7868 8/10/12 bit Single channel
ADC.
Datasheet: http://www.ti.com/lit/ds/symlink/ads7868.pdf
Signed-off-by: Ricardo Ribalda Delgado
---
v2: I have missnamed the devices
drivers/iio/adc/Kconfig | 3 ++-
drivers/iio/adc/ad7476.c | 20
Resend because previous mail is blocked by server.
In the original code, some function names begin with "ingenic_gpio_",
and some with "gpio_ingenic_". For the sake of uniform style,
all of them are changed to the beginning of "ingenic_gpio_".
Signed-off-by: Zhou Yanjie
---
drivers/pinctrl/pinctrl-ingenic.c | 46 +++--
Add support for ADS7866, ADS7867 and ADS7868 8/10/12 bit Single channel
ADC.
Datasheet: http://www.ti.com/lit/ds/symlink/ads7868.pdf
Signed-off-by: Ricardo Ribalda Delgado
---
v2: I have missnamed the devices
drivers/iio/adc/Kconfig | 3 ++-
drivers/iio/adc/ad7476.c | 20
Delete uart4 and i2c3/4 from JZ4770:
According to the datasheet, only JZ4780 have uart4 and i2c3/4. So we
remove it from the JZ4770 code and add a section corresponding the JZ4780.
Fix bugs in i2c0/1:
The pin number was wrong in the original code.
Fix bugs in uart2:
JZ4770 and JZ4780 have differe
Add mmc2 for JZ4770 and JZ4780:
According to the datasheet, both JZ4770 and JZ4780 have mmc2. But this
part of the original code is missing. It is worth noting that JZ4770's
mmc2 supports 8bit mode while JZ4780's does not, so we added the
corresponding code for both models.
Add nemc-wait for JZ477
Warning is reported when checkpatch indicates that
"static const char * array" should be changed to
"static const char * const".
Signed-off-by: Zhou Yanjie
---
drivers/pinctrl/pinctrl-ingenic.c | 136 +-
1 file changed, 76 insertions(+), 60 deletions(-)
diff
Sorry, for the last two mails with the wrong [PATCH], instead of
[PATCH v2]. I thought I was "dry-running" my script.
On Fri, Jan 25, 2019 at 11:01 AM Ricardo Ribalda Delgado
wrote:
>
> Add support for ADS7866, ADS7867 and ADS7868 8/10/12 bit Single channel
> ADC.
>
> Datasheet: http://www.ti.com
Add support for ADS7866, ADS7867 and ADS7868 8/10/12 bit Single channel
ADC.
Datasheet: http://www.ti.com/lit/ds/symlink/ads7868.pdf
Signed-off-by: Ricardo Ribalda Delgado
---
v2: I have missnamed the devices
drivers/iio/adc/Kconfig | 3 ++-
drivers/iio/adc/ad7476.c | 20
[...]
> > > > > +/**
> > > > > + * tick_nohz_get_next_wakeup - return the next wake up of the CPU
> > > > > + * @cpu: the particular CPU to get next wake up for
> > > > > + *
> > > > > + * Called for idle CPUs only.
> > > > > + */
> > > > > +ktime_t tick_nohz_get_next_wakeup(int cpu)
> > > > > +{
Hi Lorenzo,
Lorenzo Pieralisi wrote on Wed, 23 Jan 2019
17:05:09 +:
> On Tue, Jan 08, 2019 at 05:24:25PM +0100, Miquel Raynal wrote:
> > Hello,
> >
> > As part of an effort to bring suspend to RAM support to Armada 3700
> > SoCs (main target: ESPRESSObin), this series handles the work aroun
Hi,
On Thu, Jan 24, 2019 at 02:10:25PM +0100, Paul Kocialkowski wrote:
> On Tue, 2018-11-27 at 09:21 +0100, Maxime Ripard wrote:
> > Hi!
> >
> > On Fri, Nov 23, 2018 at 02:02:09PM +0100, Paul Kocialkowski wrote:
> > > This introduces support for HEVC/H.265 to the Cedrus VPU driver, with
> > > bot
On Fri, 25 Jan 2019 10:25:37 +0100,
Baolin Wang wrote:
>
> Hi Jaroslav,
> On Thu, 24 Jan 2019 at 21:43, Jaroslav Kysela wrote:
> >
> > Dne 23.1.2019 v 13:46 Leo Yan napsal(a):
> > > Hi all,
> > >
> > > On Wed, Jan 23, 2019 at 12:58:51PM +0100, Takashi Iwai wrote:
> > >> On Tue, 22 Jan 2019 21:25:
In order to respect mw_cuinits, pblk's write buffer maintains a
backpointer to protect data not yet persisted; when writing to the write
buffer, this backpointer defines a threshold that pblk's rate-limiter
enforces.
On small PU configurations, the following scenarios might take place: (i)
the thr
On Fri, Jan 18, 2019 at 11:58:46PM +0300, Vitaly Chikunov wrote:
> Previous akcipher .verify() just `decrypts' (using RSA encrypt which is
> using public key) signature to uncover message hash, which was then
> compared in upper level public_key_verify_signature() with the expected
> hash value, wh
On Fri, Jan 25, 2019 at 09:54:53AM +0200, Mike Rapoport wrote:
> On Thu, Jan 24, 2019 at 05:28:48PM +0800, Peter Xu wrote:
> > On Thu, Jan 24, 2019 at 09:27:07AM +0200, Mike Rapoport wrote:
> > > On Thu, Jan 24, 2019 at 12:56:15PM +0800, Peter Xu wrote:
> > > > On Mon, Jan 21, 2019 at 12:42:33PM +0
On Thu, 24 Jan 2019 at 16:44, Miguel Ojeda
wrote:
>
> The upcoming GCC 9 release extends the -Wmissing-attributes warnings
> (enabled by -Wall) to C and aliases: it warns when particular function
> attributes are missing in the aliases but not in their target.
>
> In particular, it triggers here b
IPROC host has the limitation that it can use only those address ranges
given by dma-ranges property as inbound address. So that the memory
address holes in dma-ranges should be reserved to allocate as DMA address.
Inbound address of host accessed by PCIe devices will not be translated
before it c
PCI host bridge has list of resource entries contain address ranges for
which IOVA address mapping has to be reserve. These address ranges are
the address holes in dma-ranges DT property.
It is similar to PCI IO resources address ranges reserving in IOMMU for
each EP connected to host bridge.
Sig
Few SOCs have limitation that their PCIe host can't allow few inbound
address ranges. Allowed inbound address ranges are listed in dma-ranges
DT property and this address ranges are required to do IOVA mapping.
Remaining address ranges have to be reserved in IOVA mapping.
PCIe Host driver of those
Add a dma_resv parameter in PCI host bridge structure to hold resource
entries list of memory regions for which IOVAs have to reserve.
PCIe host driver will add resource entries to this list based on its
requirements. Few inbound address ranges can't be allowed by few PCIe host,
so those address r
From: Thierry Reding
When requesting a reset control for exclusive use that's already in use,
an -EBUSY error code is returned. Users can react accordingly when they
receive that error code, so there is no need to loudly complain.
Signed-off-by: Thierry Reding
---
drivers/reset/core.c | 2 +-
From: Thierry Reding
If the system was booted using a device tree and if the device tree
contains a MAC address, use it instead of reading one from the EEPROM.
This is useful in situations where the EEPROM isn't properly programmed
or where the firmware wants to override the existing MAC address.
On Fri, Jan 25, 2019 at 11:04 AM Ulf Hansson wrote:
>
> [...]
>
> > > > > > +/**
> > > > > > + * tick_nohz_get_next_wakeup - return the next wake up of the CPU
> > > > > > + * @cpu: the particular CPU to get next wake up for
> > > > > > + *
> > > > > > + * Called for idle CPUs only.
> > > > > > +
On Fri, 25 Jan 2019 11:10:25 +0100,
Takashi Iwai wrote:
>
> On Fri, 25 Jan 2019 10:25:37 +0100,
> Baolin Wang wrote:
> >
> > Hi Jaroslav,
> > On Thu, 24 Jan 2019 at 21:43, Jaroslav Kysela wrote:
> > >
> > > Dne 23.1.2019 v 13:46 Leo Yan napsal(a):
> > > > Hi all,
> > > >
> > > > On Wed, Jan 23,
Hi,
Trying to get BTF to beautify some maps in augmented_raw_syscalls.o,
something is not working, these are the steps, maybe writing them down
will help me to find the problem :-)
So in tools/perf/examples/bpf/augmented_raw_syscalls.c I have
the "syscalls" map, where I'll store d
Hi Tomasz,
Thanks for the comments!
On 1/25/19 9:59 AM, Tomasz Figa wrote:
> .Hi Stan,
>
> On Fri, Jan 18, 2019 at 1:21 AM Stanimir Varbanov
> wrote:
>>
>> This refactored code for start/stop streaming vb2 operations and
>> adds a state machine handling similar to the one in stateful codec
>> A
On 1/24/2019 5:16 PM, Georgi Djakov wrote:
Hi Asutosh,
Thanks for the patch!
On 1/24/19 09:01, Asutosh Das wrote:
Adapt to the new ICB framework for bus bandwidth voting.
It's actually called interconnect API or interconnect framework.
Thanks! will change it.
This requires the source/des
On 24/01/2019 at 14:38, Harini Katakam wrote:
> The interrupt handler contains a workaround for RX hang applicable
> to Zynq and AT91 only. Subsequent versions do not need this
AT91RM9200 only. It's not the case for other AT91 SoCs (reading errata
list for them).
That being said I have to add a
On 1/24/2019 10:22 PM, Evan Green wrote:
On Wed, Jan 23, 2019 at 11:02 PM Asutosh Das wrote:
Adapt to the new ICB framework for bus bandwidth voting.
This requires the source/destination port ids.
Also this requires a tuple of values.
The tuple is for two different paths - from UFS master
to
On Fri, Jan 25, 2019 at 5:32 PM Stanimir Varbanov
wrote:
>
> Hi Alex,
>
> On 1/25/19 9:46 AM, Alexandre Courbot wrote:
> > On Thu, Jan 17, 2019 at 8:58 PM Stanimir Varbanov
> > wrote:
> >>
> >> Hi Malathi,
> >>
> >> On 12/20/18 9:47 AM, Malathi Gottam wrote:
> >>> This adds video nodes to sdm845
On Fri, Jan 25, 2019 at 09:02:42AM +, Reshetova, Elena wrote:
> > > I suppose we can add smp_acquire__after_ctrl_dep() on the true branch.
> > > Then it reall does become rel_acq.
> > >
> > > A wee something like so (I couldn't find an arm64 refcount, even though
> > > I have distinct memories
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