On Fri, Jan 25, 2019 at 06:09:29PM +0800, Herbert Xu wrote:
> On Fri, Jan 18, 2019 at 11:58:46PM +0300, Vitaly Chikunov wrote:
> > Previous akcipher .verify() just `decrypts' (using RSA encrypt which is
> > using public key) signature to uncover message hash, which was then
> > compared in upper le
Be more consistent with genuine Hyper-V: don't recommend using Enlightened
VMCS when it wasn't enabled, don't advertise reset via synthetic MSR.
Vitaly Kuznetsov (2):
x86/kvm/hyper-v: don't recommend doing reset via synthetic MSR
x86/kvm/hyper-v: recommend using eVMCS only when it is enabled
System reset through synthetic MSR is not recommended neither by genuine
Hyper-V nor my QEMU.
Fixes: 2bc39970e932 ("x86/kvm/hyper-v: Introduce KVM_GET_SUPPORTED_HV_CPUID")
Signed-off-by: Vitaly Kuznetsov
Reviewed-by: Liran Alon
---
arch/x86/kvm/hyperv.c | 1 -
1 file changed, 1 deletion(-)
dif
From: Rafael J. Wysocki
After commit ead18c23c263 ("driver core: Introduce device links
reference counting"), if if there is a link between the given supplier
and the given consumer already, device_link_add() will refcount it
and return it unconditionally without updating its flags. It is
possib
We shouldn't probably be suggesting using Enlightened VMCS when it's not
enabled (not supported from guest's point of view). Hyper-V on KVM seems
to be fine either way but let's be consistent.
Reviewed-by: Liran Alon
Signed-off-by: Vitaly Kuznetsov
---
arch/x86/kvm/hyperv.c | 3 ++-
1 file chan
From: Thierry Reding
Support enabling various supplies needed to provide power to the PLLs
and logic used to drive the USB, PCI and SATA pads.
Signed-off-by: Thierry Reding
---
drivers/phy/tegra/xusb.c | 34 +-
drivers/phy/tegra/xusb.h | 5 +
2 files change
From: Thierry Reding
Extend the bindings to cover the set of features found in Tegra186. Note
that, technically, there are four more supplies connected to the XUSB
pad controller (DVDD_PEX, DVDD_PEX_PLL, HVDD_PEX and HVDD_PEX_PLL), but
the power sequencing requirements of Tegra186 require these t
From: JC Kuo
Tegra186 USB2 pads and USB3 pads do not have hardware mux for changing
the pad function. For such "lanes", we can skip the lane mux register
programming.
Signed-off-by: JC Kuo
Signed-off-by: Thierry Reding
---
drivers/phy/tegra/xusb.c | 6 +-
1 file changed, 5 insertions(+),
On Fri, 25 Jan 2019 at 18:20, Takashi Iwai wrote:
>
> On Fri, 25 Jan 2019 11:10:25 +0100,
> Takashi Iwai wrote:
> >
> > On Fri, 25 Jan 2019 10:25:37 +0100,
> > Baolin Wang wrote:
> > >
> > > Hi Jaroslav,
> > > On Thu, 24 Jan 2019 at 21:43, Jaroslav Kysela wrote:
> > > >
> > > > Dne 23.1.2019 v 13
From: JC Kuo
Add support for the XUSB pad controller found on Tegra186 SoCs. It is
mostly similar to the same IP found on earlier chips, but the number of
pads exposed differs, as do the programming sequences.
Note that the DVDD_PEX, DVDD_PEX_PLL, HVDD_PEX and HVDD_PEX_PLL power
supplies of the
From: Thierry Reding
The device tree bindings document the "mode" property of "ports"
subnodes, but the driver was not parsing the property. In preparation
for adding role switching, parse the property at probe time.
Based on work by JC Kuo .
Signed-off-by: Thierry Reding
---
drivers/phy/tegr
From: Thierry Reding
Extend the bindings to cover the set of features found in Tegra186.
Signed-off-by: Thierry Reding
---
.../devicetree/bindings/usb/nvidia,tegra124-xusb.txt | 4
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/usb/nvidia,tegra124
From: Thierry Reding
Adds the XUSB pad and XUSB controllers on Tegra186.
Signed-off-by: Thierry Reding
---
arch/arm64/boot/dts/nvidia/tegra186.dtsi | 135 +++
1 file changed, 135 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
b/arch/arm64/boot/dts/nvi
Am 25.01.19 um 09:43 schrieb Ard Biesheuvel:
On Thu, 24 Jan 2019 at 15:01, Alex Deucher wrote:
On Thu, Jan 24, 2019 at 9:00 AM Ard Biesheuvel
wrote:
On Thu, 24 Jan 2019 at 13:31, Koenig, Christian
wrote:
Am 24.01.19 um 13:06 schrieb Ard Biesheuvel:
The DRM driver stack is designed to work
From: Thierry Reding
Enable the relevant pads for XUSB support on P2771- and hook up the
USB supply voltage regulators to the ports.
Signed-off-by: Thierry Reding
---
.../boot/dts/nvidia/tegra186-p2771-.dts | 115 ++
.../arm64/boot/dts/nvidia/tegra186-p3310.dtsi | 19
From: JC Kuo
Starting with Tegra186, the XUSB controller no longer has the IPFS
wrapper. This commit adds a "has_ipfs" field to struct tegra_xusb_soc
that can be used to declare the existence of the IPFS wrapper.
For the existing chips (i.e. Tegra124 and Tegra210), the new field is
set to true.
From: JC Kuo
This commit adds Tegra186 XUSB host mode controller support. This is
very similar to the existing support for Tegra124 and Tegra210, except
that the number of ports and PHYs differs and the IPFS wrapper being
gone.
Signed-off-by: JC Kuo
Signed-off-by: Thierry Reding
---
drivers/u
From: Thierry Reding
Various regulators were marked as always-on for Jetson TX2. At this
point, all of the regulators are properly hooked up, so this workaround
is no longer required.
Signed-off-by: Thierry Reding
---
.../arm64/boot/dts/nvidia/tegra186-p3310.dtsi | 23 ---
1 fi
From: Martin Kepplinger
This adds support for explicitly switching the mmc's power on and off.
Signed-off-by: Martin Kepplinger
---
This is not my patch. It's taken from
https://patchwork.kernel.org/patch/4365751/
rebased and minimally changed; but we use this.
Are there any objections to th
On Fri, 25 Jan 2019 at 12:30, Christian König
wrote:
>
> Am 25.01.19 um 09:43 schrieb Ard Biesheuvel:
> > On Thu, 24 Jan 2019 at 15:01, Alex Deucher wrote:
> >> On Thu, Jan 24, 2019 at 9:00 AM Ard Biesheuvel
> >> wrote:
> >>> On Thu, 24 Jan 2019 at 13:31, Koenig, Christian
> >>> wrote:
> A
On 24/01/2019 19:08, Takashi Iwai wrote:
> On Thu, 24 Jan 2019 18:36:43 +0100,
> Sameer Pujar wrote:
>>
>> If CONFIG_PM is disabled or runtime PM calls are forbidden, the clocks
>> will not be ON. This could cause issue during probe, where hda init
>> setup is done. This patch checks whether runt
On Fri, Jan 25, 2019 at 11:58 AM Arnd Bergmann wrote:
>
> On Fri, Jan 25, 2019 at 11:43 AM Laura Abbott wrote:
> >
> > Commit bee20031772a ("disable -Wattribute-alias warning for
> > SYSCALL_DEFINEx()") disabled -Wattribute-alias with gcc8.
> > gcc9 changed the format of -Wattribute-alias to take
On Fri, Jan 25, 2019 at 04:23:13PM +0530, Himanshu Jha wrote:
> On Fri, Jan 25, 2019 at 08:55:27AM +0200, Alexandru Ardelean wrote:
> > On Thu, Jan 24, 2019 at 4:28 PM Bharath Vedartham
> > wrote:
> > >
> > > add code to handle the case when kzalloc fails to allocate memory to dev
> > >
> > > Sig
On 25/01/2019 11:06, Sameer Pujar wrote:
> If CONFIG_PM is disabled or runtime PM calls are forbidden, the clocks
> will not be ON. This could cause issue during probe, where hda init
> setup is done. This patch enables clocks unconditionally during probe.
>
> Along with above, follwoing changes
Vitaly Kuznetsov writes:
> We shouldn't probably be suggesting using Enlightened VMCS when it's not
> enabled (not supported from guest's point of view). Hyper-V on KVM seems
> to be fine either way but let's be consistent.
>
Fixes: 2bc39970e932 ("x86/kvm/hyper-v: Introduce KVM_GET_SUPPORTED_HV_
This short series adds support for SPI inter-word delays and configures
the spi-atmel driver to honour the setting.
Some SPI slaves are so slow that they are unable to keep up even at the
SPI controller's lowest available clock frequency. I have such a
configuration where an AVR-based SPI slave i
If the SPI slave requires an inter-word delay, configure the DLYBCT
register accordingly.
Tested on a SAMA5D2 board (derived from SAMA5D2-Xplained reference
board).
Signed-off-by: Jonas Bonn
CC: Nicolas Ferre
CC: Mark Brown
CC: Alexandre Belloni
CC: Ludovic Desroches
CC: linux-...@vger.kerne
Some devices are slow and cannot keep up with the SPI bus and therefore
require a short delay between words of the SPI transfer.
The example of this that I'm looking at is a SAMA5D2 with a minimum SPI
clock of 400kHz talking to an AVR-based SPI slave. The AVR cannot put
bytes on the bus fast enou
On Fri, Jan 25, 2019 at 11:32 AM Viresh Kumar wrote:
>
> On 25-01-19, 12:32, Amit Kucheria wrote:
> > All cpufreq drivers do similar things to register as a cooling device.
> > Provide a cpufreq driver flag so drivers can just ask the cpufreq core
> > to register the cooling device on their behalf
On 25/01/2019 12:44, Jonas Bonn wrote:
If the SPI slave requires an inter-word delay, configure the DLYBCT
register accordingly.
Tested on a SAMA5D2 board (derived from SAMA5D2-Xplained reference
board).
Signed-off-by: Jonas Bonn
CC: Nicolas Ferre
CC: Mark Brown
CC: Alexandre Belloni
CC:
Let's use xattr_prefix instead of open code.
No logic changes.
Signed-off-by: Gao Xiang
---
drivers/staging/erofs/xattr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/staging/erofs/xattr.c b/drivers/staging/erofs/xattr.c
index 1c9498e38f0e..eca65df46133 100644
---
Hi,
On Fri, 25 Jan 2019 at 19:44, Jonas Bonn wrote:
>
> Some devices are slow and cannot keep up with the SPI bus and therefore
> require a short delay between words of the SPI transfer.
>
> The example of this that I'm looking at is a SAMA5D2 with a minimum SPI
> clock of 400kHz talking to an AVR
Hi Jisheng,
Thanks for your report.
On 25/01/19 07:29, Jisheng Zhang wrote:
> In dw_i3c_master_irq_handler(), we already have gotten
> &master->xferqueue.lock, if we try to get the same lock again in
> dw_i3c_master_dequeue_xfer(), deadlock happens.
>
> We fix this issue by introduing dw_i3c_mast
在 2018年12月05日 05:33, Lendacky, Thomas 写道:
> On 11/29/2018 09:37 PM, Dave Young wrote:
>> + more people
>>
>> On 11/29/18 at 04:09pm, Lianbo Jiang wrote:
>>> When doing kexec_file_load, the first kernel needs to pass the e820
>>> reserved ranges to the second kernel. But kernel can not exactly
>>> m
On 25/01/2019 03:23, Joseph Lo wrote:
> Hi Jon,
>
> Thanks for reviewing.
>
> On 1/24/19 6:30 PM, Jon Hunter wrote:
>>
>> On 07/01/2019 03:28, Joseph Lo wrote:
>>> The Tegra210 timer provides fourteen 29-bit timer counters and one
>>> 32-bit
>>> timestamp counter. The TMRs run at either a fixed
Let's add .get_acl() to read the file's acl
from its xattrs to make POSIX ACL usable.
Signed-off-by: Gao Xiang
---
This [PATCH 2/2] currently hasn't tested, please ignore temporarily...
I will test it asap...
Thanks,
Gao Xiang
drivers/staging/erofs/inode.c | 3 +++
drivers/staging/erofs/nam
The 83xx has 8 SPRG registers and uses at least SPRG4
for DTLB handling LRU.
Fixes: 2319f1239592 ("powerpc/mm: e300c2/c3/c4 TLB errata workaround")
Cc: sta...@vger.kernel.org
Signed-off-by: Christophe Leroy
---
arch/powerpc/platforms/83xx/suspend-asm.S | 34 ---
1 fil
On Fri, Jan 25, 2019 at 10:28:14AM +0800, Baoquan He wrote:
> This is a RESEND post.
>
> The original v1 post can be found here:
> http://lkml.kernel.org/r/20180829141624.13985-1-...@redhat.com
>
> It's trying to fix several corner case issues for kexec/kdump when
> dynamic switching of paging mo
On Fri, Jan 25, 2019 at 04:57:27PM +0900, Masahiro Yamada wrote:
> My main motivation is to get rid of crappy header search path manipulation
> from Kbuild core.
>
> Before that, I want to finish as many cleanup works as possible.
>
> If you are interested in the big picture of this work,
> the f
Hi,
On 25/01/2019 12:53, Baolin Wang wrote:
Hi,
On Fri, 25 Jan 2019 at 19:44, Jonas Bonn wrote:
Some devices are slow and cannot keep up with the SPI bus and therefore
require a short delay between words of the SPI transfer.
The example of this that I'm looking at is a SAMA5D2 with a minimum
On 25/01/2019 12:01, Jon Hunter wrote:
>
> On 25/01/2019 03:23, Joseph Lo wrote:
>> Hi Jon,
>>
>> Thanks for reviewing.
>>
>> On 1/24/19 6:30 PM, Jon Hunter wrote:
>>>
>>> On 07/01/2019 03:28, Joseph Lo wrote:
The Tegra210 timer provides fourteen 29-bit timer counters and one
32-bit
>>
On Fri, Jan 25, 2019 at 4:01 PM Viresh Kumar wrote:
>
> On 25-01-19, 12:32, Amit Kucheria wrote:
> > All cpufreq drivers do similar things to register as a cooling device.
> > Provide a cpufreq driver flag so drivers can just ask the cpufreq core
> > to register the cooling device on their behalf.
On 1/25/2019 5:12 PM, Jon Hunter wrote:
On 25/01/2019 11:06, Sameer Pujar wrote:
If CONFIG_PM is disabled or runtime PM calls are forbidden, the clocks
will not be ON. This could cause issue during probe, where hda init
setup is done. This patch enables clocks unconditionally during probe.
Al
The following changes since commit 1c7fc5cbc33980acd13d668f1c8f0313d6ae9fd8:
Linux 5.0-rc2 (2019-01-14 10:41:12 +1200)
are available in the Git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb.git tags/usb-5.0-rc4
for you to fetch changes up to 4f9b838927812b5949a9899
The following changes since commit 1c7fc5cbc33980acd13d668f1c8f0313d6ae9fd8:
Linux 5.0-rc2 (2019-01-14 10:41:12 +1200)
are available in the Git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty.git tags/tty-5.0-rc4
for you to fetch changes up to 815d835b7ba46685c316b00
The following changes since commit bfeffd155283772bbe78c6a05dec7c0128ee500c:
Linux 5.0-rc1 (2019-01-06 17:08:20 -0800)
are available in the Git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc.git
tags/char-misc-5.0-rc4
for you to fetch changes up to 52768f3242
The following changes since commit 1c7fc5cbc33980acd13d668f1c8f0313d6ae9fd8:
Linux 5.0-rc2 (2019-01-14 10:41:12 +1200)
are available in the Git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging.git
tags/staging-5.0-rc4
for you to fetch changes up to 31eb79db420a3f
Some devices are slow and cannot keep up with the SPI bus and therefore
require a short delay between words of the SPI transfer.
The example of this that I'm looking at is a SAMA5D2 with a minimum SPI
clock of 400kHz talking to an AVR-based SPI slave. The AVR cannot put
bytes on the bus fast enou
If the SPI slave requires an inter-word delay, configure the DLYBCT
register accordingly.
Tested on a SAMA5D2 board (derived from SAMA5D2-Xplained reference
board).
Signed-off-by: Jonas Bonn
CC: Nicolas Ferre
CC: Mark Brown
CC: Alexandre Belloni
CC: Ludovic Desroches
CC: linux-...@vger.kerne
Resubmission to fix thinko in spi-atmel patch.
Changed in v2:
* Fix atmel-spi driver to not unconditionally set minimal delay if no
delay is required (erroneous clamping)
This short series adds support for SPI inter-word delays and configures
the spi-atmel driver to honour the setting.
Some SP
On 1/25/19 12:39 PM, Miguel Ojeda wrote:
> On Fri, Jan 25, 2019 at 11:58 AM Arnd Bergmann wrote:
>>
>> On Fri, Jan 25, 2019 at 11:43 AM Laura Abbott wrote:
>>>
>>> Commit bee20031772a ("disable -Wattribute-alias warning for
>>> SYSCALL_DEFINEx()") disabled -Wattribute-alias with gcc8.
>>> gcc9 ch
Sorry, this version raced with my vacation, I missed it.
I'll try to read this code carefully but after a quick glance I have some
concerns,
On 12/21, Roman Gushchin wrote:
>
> +static void cgroup_update_frozen(struct cgroup *cgrp)
> +{
> + bool frozen;
> +
> + lockdep_assert_held(&css_se
Hi Souptick,
On 2019-01-25 05:55, Souptick Joarder wrote:
> On Tue, Jan 22, 2019 at 8:37 PM Marek Szyprowski
> wrote:
>> On 2019-01-11 16:11, Souptick Joarder wrote:
>>> Convert to use vm_insert_range_buggy to map range of kernel memory
>>> to user vma.
>>>
>>> This driver has ignored vm_pgoff. W
Hi Jianxin,
Jianxin Pan wrote on Tue, 15 Jan 2019
23:38:02 +0800:
> These two patches try to add initial NAND driver support for Amlogic Meson
> SoCs, current it has been tested on GXL(p212) and AXG(s400) platform.
>
Applied to nand/next.
Thanks,
Miquèl
Hi Jianxin,
Jianxin Pan wrote on Sun, 20 Jan 2019
01:02:35 +0800:
> Add entry for Amlogic NAND controller driver and its bindings[0].
>
> [0]
> https://lore.kernel.org/lkml/1547566684-57472-1-git-send-email-jianxin@amlogic.com/
>
> Signed-off-by: Liang Yang
> Signed-off-by: Jianxin Pan
Em Wed, Jan 23, 2019 at 04:52:23PM -0800, Tony Jones escreveu:
> Seeteena posted, earlier this week, some patches to add Python3 support
> to scripts/python/*.py. Unfortunately there were some issues with these
> patches (such as: https://lkml.org/lkml/2019/1/17/351)
>
> Since I already had a tes
ITLB miss on kernel pages only occur with CONFIG_MODULES and
CONFIG_DEBUG_PAGEALLOC.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_32.S | 4
1 file changed, 4 insertions(+)
diff --git a/arch/powerpc/kernel/head_32.S b/arch/powerpc/kernel/head_32.S
index 53f65124edd5..3bbf937
PAGE_DIRTY corresponds to the C bit. If writing on
a page for which the C bit is not set, a DataStoreTLBMiss
is generated. No need to check it in DataLoadTLBMiss.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_32.S | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff -
Use SPRN_SPRG5 to store the current thread PGDIR and
avoid reading thread_struct->pgdir at every TLB miss.
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/reg.h | 1 +
arch/powerpc/kernel/cpu_setup_6xx.S | 4
arch/powerpc/kernel/head_32.S | 28 -
There is no reason to re-read each time the pointer at
location 0xf0 as it is fixed and known.
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/mmu.h | 2 ++
arch/powerpc/kernel/head_32.S | 5 ++---
arch/powerpc/kernel/head_40x.S | 5 ++---
arch/powerpc/kernel/head_8xx.S | 1 +
arch
_PAGE_RW and _PAGE_DIRTY do not matter for ITLB misses.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_32.S | 8 ++--
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/arch/powerpc/kernel/head_32.S b/arch/powerpc/kernel/head_32.S
index 3bbf937ad634..2aec3f91c9f5 100
The purpose of this serie is to optimise the handling of
TLB misses on the 603/e300.
Today the TLB miss handlers are implemented by more or less
copying the actions performed by the hash page handlers used
on processors having HASH pagetable.
This serie brings some simplification.
Christophe Ler
Since commit c62ce9ef97ba ("powerpc: remove remaining bits from
CONFIG_APUS"), tophys() has become a pure constant operation.
PAGE_OFFSET is known at compile time so the physical address
can be builtin directly.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_32.S | 15 ++---
PP bits take user access into account, so no need to check _PAGE_USER
here. A DSI or ISI will be generated if needed.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_32.S | 12 +++-
1 file changed, 3 insertions(+), 9 deletions(-)
diff --git a/arch/powerpc/kernel/head_32.S b
PAGE_ACCESSED is only needed for CONFIG_SWAP. When CONFIG_SWAP
is not set, just ignore it. If CONFIG_SWAP is set and PAGE_ACCESSED
is not, let's take a minor fault.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_32.S | 24 +---
1 file changed, 13 insertions(+),
For pages without _PAGE_USER, PP field is 00
For pages with _PAGE_USER, PP field is 10 for RW and 11 for RO.
This patch sets _PAGE_USER to 0x002 and _PAGE_RW to 0x001
is order to simplify TLB handling by reducing amount of shifts.
The location of _PAGE_PRESENT and _PAGE_HASHPTE doesn't matter
as
Since commit c62ce9ef97ba ("powerpc: remove remaining bits from
CONFIG_APUS"), tophys() has become a pure constant operation.
PAGE_OFFSET is known at compile time so the physical address
can be builtin directly.
Signed-off-by: Christophe Leroy
---
arch/powerpc/mm/hash_low_32.S | 62 +
Hi Yoshio,
Yoshio Furuyama wrote on Wed, 16
Jan 2019 14:53:19 +0900:
> Add device table for Toshiba Memory products.
> Also, generalize OOB layout structure and function names.
>
> Signed-off-by: Yoshio Furuyama
>
> ---
Applied to nand/next with the mathematical operations enclosed in
braces
Libphy provides a standard set of helpers to access the MMD PHY
registers. Use those instead of relying on custom driver-specific
functions.
Signed-off-by: Carlo Caione
---
drivers/net/phy/at803x.c | 16 +++-
1 file changed, 3 insertions(+), 13 deletions(-)
diff --git a/drivers/net/
On Mon, Jan 21, 2019 at 03:51:35PM +0200, Heikki Krogerus wrote:
> Hi,
>
> On Mon, Jan 21, 2019 at 04:36:13PM +0800, Chen Yu wrote:
> > Have the fwnode_get_name() patches been accepted?
>
> No, I didn't have a user for the function anymore:
> https://lkml.org/lkml/2018/12/17/284
>
> > And I will
Hi Mathieu,
Mathieu Malaterre wrote on Wed, 16 Jan 2019 20:50:04
+0100:
> There is a plan to build the kernel with -Wimplicit-fallthrough and
> these places in the code produced warnings (W=1).
>
> This commit removes the following warnings:
>
> drivers/mtd/nand/raw/nand_base.c:5556:6: warni
Hi Mathieu,
Mathieu Malaterre wrote on Wed, 16 Jan 2019 20:50:03
+0100:
> There is a plan to build the kernel with -Wimplicit-fallthrough and
> these places in the code produced warnings (W=1).
>
> This commit removes the following warnings:
>
> drivers/mtd/nand/raw/nand_legacy.c:332:6: warn
Hi Masahiro,
Masahiro Yamada wrote on Mon, 21 Jan
2019 15:32:07 +0900:
> Now that the last user of this hook, denali.c, stopped using it,
> we can remove the erase hook from nand_legacy.
>
> I squashed single_erase() because only the difference between
> single_erase() and nand_erase_op() is th
Setting the BPNV bit defaults the block protection bits BP0-2 to 1 at
reset. This means that all the flash sectors are protected until they
are explicity unlocked by the user.
Together with protection of the status register via the SRWD bit and the
WP# signal, this allows a flash device to be eff
Hi Masahiro,
Masahiro Yamada wrote on Mon, 21 Jan
2019 13:52:06 +0900:
> Commit f9ebd1bb4103 ("mtd: rawnand: Deprecate ->erase()") discouraged
> the use of this hook, so I am happy to follow the suggestion.
>
> Although the Denali IP provides a special MAP10 command for erasing,
> using it woul
On Thu, 2019-01-24 at 20:56 -0600, Gustavo A. R. Silva wrote:
> In preparation to enabling -Wimplicit-fallthrough, mark switch
> cases where we are expecting to fall through.
>
> This patch fixes the following warnings:
>
> security/integrity/ima/ima_appraise.c:116:26: warning: this statement may
Hi Masahiro,
Masahiro Yamada wrote on Tue, 22 Jan
2019 00:57:43 +0900:
> On Mon, Jan 21, 2019 at 10:14 PM Boris Brezillon
> wrote:
> >
> > On Mon, 21 Jan 2019 22:05:34 +0900
> > Masahiro Yamada wrote:
> >
> > > nand_scan_ident() iterates over maxchips to find as many homogeneous
> > > chips
On Fri, 25 Jan 2019 12:36:00 +0100,
Jon Hunter wrote:
>
>
> On 24/01/2019 19:08, Takashi Iwai wrote:
> > On Thu, 24 Jan 2019 18:36:43 +0100,
> > Sameer Pujar wrote:
> >>
> >> If CONFIG_PM is disabled or runtime PM calls are forbidden, the clocks
> >> will not be ON. This could cause issue during
On Fri, Jan 25, 2019 at 11:05:30AM +0100, Miquel Raynal wrote:
> Hi Lorenzo,
>
> Lorenzo Pieralisi wrote on Wed, 23 Jan 2019
> 17:05:09 +:
>
> > On Tue, Jan 08, 2019 at 05:24:25PM +0100, Miquel Raynal wrote:
> > > Hello,
> > >
> > > As part of an effort to bring suspend to RAM support to Ar
On 24. 01. 19 9:28, Jan Kiszka wrote:
> From: Jan Kiszka
>
> Somewhere along recent changes to power control of the wl1831, power-on
> became very unreliable on the Ultra96, failing like this:
>
> wl1271_sdio: probe of mmc2:0001:1 failed with error -16
> wl1271_sdio: probe of mmc2:0001:2 failed
On Thu, Jan 24, 2019 at 10:37:23PM +0800, Ayaka wrote:
> > +#define V4L2_H264_DPB_ENTRY_FLAG_VALID0x01
> > +#define V4L2_H264_DPB_ENTRY_FLAG_ACTIVE0x02
> > +#define V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM0x04
> > +
> > +struct v4l2_h264_dpb_entry {
> > +__
When used on a 2GB memory IMX6 device, the driver configures etnaviv
memory_base address to:
dma_mask - SZ_2G + 1
which is 2GB as the dma_mask has all bits on. This results in the gpu
having a narrow linear memory window of only 256MB. This patch changes
the behavior to configure etnaviv
Hi Lorenzo,
Lorenzo Pieralisi wrote on Fri, 25 Jan 2019
12:40:11 +:
> On Fri, Jan 25, 2019 at 11:05:30AM +0100, Miquel Raynal wrote:
> > Hi Lorenzo,
> >
> > Lorenzo Pieralisi wrote on Wed, 23 Jan 2019
> > 17:05:09 +:
> >
> > > On Tue, Jan 08, 2019 at 05:24:25PM +0100, Miquel Raynal
On 01/25, Vladis Dronov wrote:
>
> Ring buffer implementation in hid_debug_event() and hid_debug_events_read()
> is strange allowing lost or corrupted data. After commit 717adfdaf147
> ("HID: debug: check length before copy_to_user()") it is possible to enter
> an infinite loop in hid_debug_events_
On Fri, 25 Jan 2019 12:11:43 +0100,
Baolin Wang wrote:
>
> Hi Takashi,
> On Fri, 25 Jan 2019 at 18:10, Takashi Iwai wrote:
> >
> > On Fri, 25 Jan 2019 10:25:37 +0100,
> > Baolin Wang wrote:
> > >
> > > Hi Jaroslav,
> > > On Thu, 24 Jan 2019 at 21:43, Jaroslav Kysela wrote:
> > > >
> > > > Dne 23
Hi,
On Thu, 2019-01-24 at 20:23 +0800, Ayaka wrote:
>
> Sent from my iPad
>
> > On Jan 24, 2019, at 6:27 PM, Paul Kocialkowski
> > wrote:
> >
> > Hi,
> >
> > > On Thu, 2019-01-10 at 21:32 +0800, ayaka wrote:
> > > I forget a important thing, for the rkvdec and rk hevc decoder, it would
> >
On Fri, 25 Jan 2019 12:24:29 +0100,
Baolin Wang wrote:
>
> On Fri, 25 Jan 2019 at 18:20, Takashi Iwai wrote:
> >
> > On Fri, 25 Jan 2019 11:10:25 +0100,
> > Takashi Iwai wrote:
> > >
> > > On Fri, 25 Jan 2019 10:25:37 +0100,
> > > Baolin Wang wrote:
> > > >
> > > > Hi Jaroslav,
> > > > On Thu, 24
On 1/25/19 11:09 AM, Javier González wrote:
In order to respect mw_cuinits, pblk's write buffer maintains a
backpointer to protect data not yet persisted; when writing to the write
buffer, this backpointer defines a threshold that pblk's rate-limiter
enforces.
On small PU configurations, the fol
Hi Masahiro,
Masahiro Yamada wrote on Thu, 24 Jan
2019 13:19:05 +0900:
> Masahiro Yamada (2):
> mtd: rawnand: denali: remove unneeded denali_reset_irq() call
> mtd: rawnand: denali: remove unused function argument 'raw'
>
> drivers/mtd/nand/raw/denali.c | 21 +
> 1 file
When the connections are defined in firmware, struct
device_connection will have the fwnode member pointing to
the device node (struct fwnode_handle) of the requested
device, and the endpoint will not be used at all in that
case.
Signed-off-by: Heikki Krogerus
---
drivers/usb/roles/class.c | 21
When the connections are defined in firmware, struct
device_connection will have the fwnode member pointing to
the device node (struct fwnode_handle) of the requested
device, and the endpoint will not be used at all in that
case.
Signed-off-by: Heikki Krogerus
---
drivers/usb/typec/class.c | 24
When the connections are defined in firmware, struct
device_connection will have the fwnode member pointing to
the device node (struct fwnode_handle) of the requested
device, and the endpoint will not be used at all in that
case.
Signed-off-by: Heikki Krogerus
---
drivers/usb/typec/mux.c | 78 ++
On 25/01/2019 12:19, Sameer Pujar wrote:
>
> On 1/25/2019 5:12 PM, Jon Hunter wrote:
>> On 25/01/2019 11:06, Sameer Pujar wrote:
>>> If CONFIG_PM is disabled or runtime PM calls are forbidden, the clocks
>>> will not be ON. This could cause issue during probe, where hda init
>>> setup is done. T
This will prepare the device connection API for connections
described in firmware.
Signed-off-by: Heikki Krogerus
---
include/linux/device.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/include/linux/device.h b/include/linux/device.h
index 5663003a95eb..1fb077f5a936 100644
--- a/inc
Driver for fusb302 does not support alternate modes, so the
connection is not really needed for now. Removing that
connection description allows us to improve the USB Type-C
mux API.
Signed-off-by: Heikki Krogerus
---
drivers/platform/x86/intel_cht_int33fe.c | 11 ---
1 file changed, 4 i
Hi Masahiro,
Masahiro Yamada wrote on Thu, 24 Jan
2019 15:28:57 +0900:
> This is a leftover of commit 997cde2a2220 ("mtd: nand: denali: skip
> driver internal bounce buffer when possible").
>
> Signed-off-by: Masahiro Yamada
> ---
>
> drivers/mtd/nand/raw/denali.h | 1 -
> 1 file changed, 1
We can replace the second parameter that is passed to the
typec_mux_get() function with alt mode description
structure, and simply pass NULL with accessory modes.
With accessory modes there is no need for additional
identification (in practice the accessory mode can only be
Audio Accessory if muxi
Hi,
This series adds support for OF and ACPI device graph parsing to the
device connection API.
Handling the graph is straightforward, but because I'm adding that
fwnode member to struct device_connection, I had to make sure all the
existing users consider it.
The plan is to only support matchin
If connections between devices are described in OF graph or
ACPI device graph, we can find them by using the
fwnode_graph_*() functions.
Signed-off-by: Heikki Krogerus
---
drivers/base/devcon.c | 39 ---
1 file changed, 36 insertions(+), 3 deletions(-)
diff -
When the connections are defined in firmware, struct
device_connection will have the fwnode member pointing to
the device node (struct fwnode_handle) of the requested
device. The endpoint member for the device names will not be
used at all in that case.
Signed-off-by: Heikki Krogerus
---
drivers
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