On Tue, Jan 22, 2019 at 4:50 PM Miquel Raynal wrote:
>
> Hi Masahiro,
>
> Masahiro Yamada wrote on Tue, 22 Jan
> 2019 16:42:55 +0900:
>
> > Although drivers do not directly get access to the private data of
> > instruction patterns, let's use unnamed union field to be consistent
> > with nand_op_
On Tue, 2019-01-22 at 10:48 +0300, Dan Carpenter wrote:
> On Thu, Jan 17, 2019 at 05:52:28PM +0800, Ching Huang wrote:
> > On Thu, 2019-01-17 at 12:16 +0300, Dan Carpenter wrote:
> > > On Thu, Jan 17, 2019 at 04:47:07PM +0800, Ching Huang wrote:
> > > > On Thu, 2019-01-17 at 10:59 +0300, Dan Carpen
On Mon, Jan 21, 2019 at 10:25:10AM +, Yinbo Zhu wrote:
> From: yinbo.zhu
This line is still wrong :(
On 01/22/2019 07:26 AM, Alexandre Courbot wrote:
> Documents the protocol that user-space should follow when
> communicating with stateless video decoders.
>
> The stateless video decoding API makes use of the new request and tags
> APIs. While it has been implemented with the Cedrus driver so far
When limiting memory size via kernel parameter "mem=" this should be
respected even in case of memory made accessible via a PCI card.
Today this kind of memory won't be made usable in initial memory
setup as the memory won't be visible in E820 map, but it might be
added when adding PCI devices due
On a customer system running Xen a boot problem was observed due to
the kernel not respecting the memory size limit imposed by the Xen
hypervisor.
During analysis I found the same problem should be able to occur on
bare metal in case the memory would be limited via the "mem=" boot
parameter.
The
Don't allow memory to be added above the allowed maximum allocation
limit set by Xen.
Trying to do so would result in cases like the following:
[ 584.559652] [ cut here ]
[ 584.564897] WARNING: CPU: 2 PID: 1 at ../arch/x86/xen/multicalls.c:129
xen_alloc_pte+0x1c7/0x390(
On Mon, Jan 21, 2019 at 10:25:00AM +, Yinbo Zhu wrote:
> From: Nikhil Badola
>
> Set USB_EN bit to select ULPI phy for USB controller version 2.5
>
> Signed-off-by: Nikhil Badola
> Signed-off-by: Yinbo Zhu
> ---
> Change in v2:
> replace Yinbo.Zhu with Yinbo Zhu
>
> driver
Hi Masahiro,
Masahiro Yamada wrote on Tue, 22 Jan
2019 17:00:54 +0900:
> On Tue, Jan 22, 2019 at 4:50 PM Miquel Raynal
> wrote:
> >
> > Hi Masahiro,
> >
> > Masahiro Yamada wrote on Tue, 22 Jan
> > 2019 16:42:55 +0900:
> >
> > > Although drivers do not directly get access to the private dat
Hi Baolin,
On Tue, Jan 22, 2019 at 3:23 AM Baolin Wang wrote:
> On Mon, 21 Jan 2019 at 21:53, Rob Herring wrote:
> > On Tue, Jan 15, 2019 at 7:47 AM Baolin Wang wrote:
> > > From: Lanqing Liu
> >
> > The email address should be updated with unisoc.com.
>
> Sure.
>
> >
> > > Add the DMA propert
--
Greetings From Mrs Elodie Antoine,
May be this letter will definitely come to you as a huge surprise, but
I implore you to take the time to go through it carefully as the
decision you make will go off a long way to determine my future and
continued existence. I am Mrs.Elodie Antoine agin
According to the datasheet and the reference code from Allwinner, the
bit used to de-assert the TCON reset is bit 4, not bit 3.
Fix it in the V3s CCU driver.
Signed-off-by: Paul Kocialkowski
---
drivers/clk/sunxi-ng/ccu-sun8i-v3s.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --g
Hello Dan,
looks already quite good...
Am 17.01.19 um 21:05 schrieb Dan Murphy:
> Create a m_can platform framework that peripherial
> devices can register to and use common code and register sets.
> The peripherial devices may provide read/write and configuration
> support of the IP.
>
> Signed
Hi Paul,
On Fri, Dec 7, 2018 at 5:30 PM Paul Kocialkowski
wrote:
>
> Hi,
>
> Thanks for this new version! I only have one comment left, see below.
>
> On Wed, 2018-12-05 at 19:01 +0900, Alexandre Courbot wrote:
> > Documents the protocol that user-space should follow when
> > communicating with s
On Tue, Jan 22, 2019 at 5:06 PM Hans Verkuil wrote:
>
> On 01/22/2019 07:26 AM, Alexandre Courbot wrote:
> > Documents the protocol that user-space should follow when
> > communicating with stateless video decoders.
> >
> > The stateless video decoding API makes use of the new request and tags
> >
On 1/21/2019 7:24 PM, Marc Gonzalez wrote:
On 21/01/2019 14:35, Rob Herring wrote:
On Mon, Jan 21, 2019 at 6:19 AM Robin Murphy wrote:
On 21/01/2019 11:57, Marc Gonzalez wrote:
[...]
# echo dump=0xffc021e0 > /sys/kernel/debug/kmemleak
kmemleak: Object 0xffc021e0 (size 209715
Hi Alexey,
On 2019-01-21 22:23, Alexey Khoroshilov wrote:
> If clk_prepare_enable() fails in dwc3_exynos_probe() or in
> dwc3_exynos_resume(), exynos->clks[0] is left undisabled
> because of usage preincrement in while condition.
>
> Found by Linux Driver Verification project (linuxtesting.org).
>
device_register exposes the device to userspace.
Therefore, while the register process is ongoing, the userspace program
will fail to open the device (ENODEV will be set to errno currently).
The program in userspace must re-open the device to cover this case.
It is more reasonable to expose the d
On Mon, Jan 21, 2019 at 10:55:36AM -0500, Jerome Glisse wrote:
> On Mon, Jan 21, 2019 at 03:57:01PM +0800, Peter Xu wrote:
> > The idea comes from a discussion between Linus and Andrea [1].
> >
> > Before this patch we only allow a page fault to retry once. We achieved
> > this by clearing the FA
From: Naveen Kumar Parna
There is no advantage to keep 'struct file_operations.open & .close'
API's. So removed the unnecessary code efi_rtc_open & efi_rtc_close.
Signed-off-by: Naveen Kumar Parna
---
drivers/char/efirtc.c | 23 ---
1 file changed, 23 deletions(-)
diff --g
On Tue, Jan 22, 2019 at 5:19 PM Alexandre Courbot wrote:
>
> On Tue, Jan 22, 2019 at 5:06 PM Hans Verkuil wrote:
> >
> > On 01/22/2019 07:26 AM, Alexandre Courbot wrote:
> > > Documents the protocol that user-space should follow when
> > > communicating with stateless video decoders.
> > >
> > >
On Mon, Jan 21, 2019 at 12:23:12PM +0200, Mike Rapoport wrote:
> On Mon, Jan 21, 2019 at 03:57:03PM +0800, Peter Xu wrote:
> > From: Shaohua Li
> >
> > add helper for writeprotect check. Will use it later.
>
> I'd merge this with the commit that actually uses this helper.
Hi, Mike,
Yeah actual
h4_recv_buf() callers store the return value to socket buffer and
recursively pass the buffer to h4_recv_buf() without protection. So,
ERR_PTR returned from h4_recv_buf() can be dereferenced, if called again
before setting the socket buffer to NULL from previous error. Check if
skb is ERR_PTR in h4
On Tue, 22 Jan 2019 09:08:30 +0100
Miquel Raynal wrote:
> Hi Masahiro,
>
> Masahiro Yamada wrote on Tue, 22 Jan
> 2019 17:00:54 +0900:
>
> > On Tue, Jan 22, 2019 at 4:50 PM Miquel Raynal
> > wrote:
> > >
> > > Hi Masahiro,
> > >
> > > Masahiro Yamada wrote on Tue, 22 Jan
> > > 2019 16:42:
Thanks for your quick reply! Paul
On 1/22/19 12:01 PM, Paul E. McKenney wrote:
On Tue, Jan 22, 2019 at 11:40:53AM +0800, Su Yue wrote:
Hi, guys
While running rcutorture tests with "onoff_interval", some tests
failed and results show like:
On Mon, 21 Jan 2019 at 20:04, Michel Dänzer wrote:
>
> On 2019-01-21 7:28 p.m., Ard Biesheuvel wrote:
> > On Mon, 21 Jan 2019 at 19:24, Michel Dänzer wrote:
> >> On 2019-01-21 7:20 p.m., Ard Biesheuvel wrote:
> >>> On Mon, 21 Jan 2019 at 19:04, Michel Dänzer wrote:
> On 2019-01-21 6:59 p.m.
Fix link errors when PINCTRL_IMX_SCU, PINCTRL_IMX8QM or PINCTRL_IMXBQXP
is enabled as a module and the dependent module is built-in.
ld: drivers/pinctrl/freescale/pinctrl-scu.o: in function
`imx_pinctrl_sc_ipc_init':
pinctrl-scu.c:(.text+0x10): undefined reference to `imx_scu_get_handle'
ld: pinc
On Mon, Jan 14, 2019 at 01:13:46PM +0100, Andreas Kemnade wrote:
> On Mon, 14 Jan 2019 11:51:29 +0100
> Johan Hovold wrote:
> > Good point. Unless we know the current state, we'd need to sleep for
> > HIBERNATE_TIMEOUT before waiting for data reception.
> >
> > > > - timeout: failure
> > >
Hi Geert,
On Tue, 22 Jan 2019 at 16:11, Geert Uytterhoeven wrote:
>
> Hi Baolin,
>
> On Tue, Jan 22, 2019 at 3:23 AM Baolin Wang wrote:
> > On Mon, 21 Jan 2019 at 21:53, Rob Herring wrote:
> > > On Tue, Jan 15, 2019 at 7:47 AM Baolin Wang
> > > wrote:
> > > > From: Lanqing Liu
> > >
> > > The
On 11/10/2018 2:58 AM, Rob Herring wrote:
On Fri, Nov 9, 2018 at 1:09 AM Prateek Patel wrote:
From: Sri Krishna chowdary
Memory reserved with "nomap" DT property in of_reserved_mem.c
removes the memory block. The removed memory blocks don't have
VA to PA mapping created in kernel page table
sdhci-omap can support both external dma controller via dmaengine
framework as well as ADMA which standard SD host controller
provides.
Signed-off-by: Chunyan Zhang
Signed-off-by: Faiz Abbas
---
Documentation/devicetree/bindings/mmc/sdhci-omap.txt | 7 +++
1 file changed, 7 insertions(+)
d
On Mon 21 Jan 2019 at 18:44, Sean Wang wrote:
On Mon, Jan 21, 2019 at 9:29 AM Loys Ollivier
wrote:
On Mon 21 Jan 2019 at 17:10, Rob Herring wrote:
> On Thu, 17 Jan 2019 17:54:32 +0100, Loys Ollivier wrote:
>> Add binding for Mediatek-based GNSS receivers.
>>
>> Signed-off-by: Loys Ollivie
Hi Myungho,
> h4_recv_buf() callers store the return value to socket buffer and
> recursively pass the buffer to h4_recv_buf() without protection. So,
> ERR_PTR returned from h4_recv_buf() can be dereferenced, if called again
> before setting the socket buffer to NULL from previous error. Check if
On Mon 21 Jan 2019 at 21:51, Rob Herring wrote:
On Mon, Jan 21, 2019 at 11:29 AM Loys Ollivier
wrote:
On Mon 21 Jan 2019 at 17:10, Rob Herring wrote:
> On Thu, 17 Jan 2019 17:54:32 +0100, Loys Ollivier wrote:
>> Add binding for Mediatek-based GNSS receivers.
>>
>> Signed-off-by: Loys Olli
>>> On 22.01.19 at 09:06, wrote:
> Don't allow memory to be added above the allowed maximum allocation
> limit set by Xen.
This reads as if the hypervisor was imposing a limit here, but looking at
xen_get_max_pages(), xen_foreach_remap_area(), and
xen_count_remap_pages() I take it that it's a res
On Mon 21-01-19 18:41:28, Shakeel Butt wrote:
> On Mon, Jan 21, 2019 at 1:59 PM Shakeel Butt wrote:
> >
> > From the start of the git history of Linux, the kernel after selecting
> > the worst process to be oom-killed, prefer to kill its child (if the
> > child does not share mm with the parent).
On Mon, Jan 21, 2019 at 12:20:35PM +0200, Mike Rapoport wrote:
> On Mon, Jan 21, 2019 at 03:57:04PM +0800, Peter Xu wrote:
> > From: Shaohua Li
> >
> > Add API to enable/disable writeprotect a vma range. Unlike mprotect,
> > this doesn't split/merge vmas.
> >
> > Cc: Andrea Arcangeli
> > Cc: Pa
On Mon, Jan 21, 2019 at 08:02:18AM -0800, Davidlohr Bueso wrote:
> Hi - considering that the wake_q patches were picked up for tip/urgent, can
> this one make it in as well?
Ah, here it is. Yes, got it now.
I was actually wondering what happened, but couldn't find it in a hurry.
All sorted now.
Hello Mark,
Can you please apply below patch in SPI tree?
Patch has been reviewed by Boris and Frieder.
--
Regards
Yogesh Gaur
> -Original Message-
> From: Yogesh Narayan Gaur
> Sent: Tuesday, January 15, 2019 5:30 PM
> To: linux-...@lists.infradead.org; bbrezil...@kernel.org;
> marek.va
On Tue, Jan 22, 2019 at 5:33 PM Boris Brezillon wrote:
>
> On Tue, 22 Jan 2019 09:08:30 +0100
> Miquel Raynal wrote:
>
> > Hi Masahiro,
> >
> > Masahiro Yamada wrote on Tue, 22 Jan
> > 2019 17:00:54 +0900:
> >
> > > On Tue, Jan 22, 2019 at 4:50 PM Miquel Raynal
> > > wrote:
> > > >
> > > > Hi
Use the mtk_pwm_data struction to define different registers
and add MT8183 specific register operations, such as MT8183
doesn't have commit register, needs to disable double buffer
before writing register, and needs to select commit mode
and use PWM_PERIOD/PWM_HIGH_WIDTH.
Signed-off-by: Jitao Shi
On 21.01.2019 18:23, Mark Rutland wrote:
> Hi Stefan,
>
> On Mon, Jan 21, 2019 at 03:41:11PM +0100, Stefan Agner wrote:
>> Currently, if only a single interrupt is available, the code assigns
>> this single interrupt to the first CPU. All other CPUs are left
>> unsupported. This allows to use perf
Hi Rob,
On 22/01/2019 at 02:07, Rob Herring wrote:
> On Wed, Jan 16, 2019 at 10:57:38AM +0100, Nicolas Ferre wrote:
>> Update the Reset Controller's binding to add new SoC compatibility string.
>>
>> Signed-off-by: Nicolas Ferre
>> ---
>> Documentation/devicetree/bindings/arm/atmel-sysregs.txt
On 22.01.19 04:18, Peter Xu wrote:
> On Mon, Jan 21, 2019 at 03:33:21PM +0100, David Hildenbrand wrote:
>
> [...]
>
>> Does this series fix the "false positives" case I experienced on early
>> prototypes of uffd-wp? (getting notified about a write access although
>> it was not a write access?)
>
Hi Rob / Shawn,
Can you please apply patches [1] [2].
--
Regards,
Yogesh Gaur
[1] https://patchwork.ozlabs.org/patch/1025136/
[2] https://patchwork.ozlabs.org/patch/1025137/
> -Original Message-
> From: Yogesh Narayan Gaur
> Sent: Tuesday, January 15, 2019 5:30 PM
> To: linux-...@list
Add imem clocks for exynos5433. This will enable to use crypto Slim
Security SubSystem (in short SlimSSS) IP block.
Acked-by: Chanwoo Choi
Signed-off-by: Kamil Konieczny
---
drivers/clk/samsung/clk-exynos5433.c | 32
1 file changed, 32 insertions(+)
diff --git a/dr
Use the mtk_pwm_data struction to define different registers
and add MT8183 specific register operations, such as MT8183
doesn't have commit register, needs to disable double buffer
before writing register, and needs to select commit mode
and use PWM_PERIOD/PWM_HIGH_WIDTH.
Signed-off-by: Jitao Shi
On Tue, Jan 22, 2019 at 09:16:19AM +0100, Paul Kocialkowski wrote:
> According to the datasheet and the reference code from Allwinner, the
> bit used to de-assert the TCON reset is bit 4, not bit 3.
>
> Fix it in the V3s CCU driver.
>
> Signed-off-by: Paul Kocialkowski
Applied, thanks!
Maxime
On Mon, Jan 21, 2019 at 11:05:03AM -0500, Alan Stern wrote:
> On Mon, 21 Jan 2019, Peter Zijlstra wrote:
> > Any additional ordering; like the one you have above; are not strictly
> > required for the proper functioning of the refcount. Rather, you rely on
> > additional ordering and will need to
On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1),
memory accesses may cause undefined fault (Data abort,
DFSC=0b11) due to the CPU Errata (Fujitsu #010001).
This patch introduces the workaround to the problem.
The workaround is to change the fault handler for Data abort
DFSC=0b11
On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1),
memory accesses may cause undefined fault (Data abort, DFSC=0b11).
This problem will be fixed by next version of Fujitsu-A64FX.
I would like to post a workaround to avoid this problem on existing version.
The workaround is to replace t
Missatge de Nick Crews del dia ds., 19 de gen.
2019 a les 1:17:
>
> From: Duncan Laurie
>
> In order to allow this code to be re-used, remove the dependency
> on the rest of the cros_ec code from the cros_ec_lpc_mec functions.
>
> Instead of using a hardcoded register base address of 0x800 have
>
On Tue, Jan 22, 2019 at 12:03:33PM +0530, Alok Chauhan wrote:
> Get the interconnect paths for I2C based Serial Engine device
> and vote accordingly based on maximum supported I2C frequency.
>
> Signed-off-by: Alok Chauhan
Acked-by: Wolfram Sang
signature.asc
Description: PGP signature
Hi Rob,
On 22/01/2019 at 02:10, Rob Herring wrote:
> On Wed, Jan 16, 2019 at 10:57:40AM +0100, Nicolas Ferre wrote:
>> This removes a line left while adding the correct compatibility string for
>> sama5d3 10/100 interface. Now use the "atmel,sama5d3-macb" string.
>>
>> Signed-off-by: Nicolas Ferre
On 22/01/2019 09:52, Jan Beulich wrote:
On 22.01.19 at 09:06, wrote:
>> Don't allow memory to be added above the allowed maximum allocation
>> limit set by Xen.
>
> This reads as if the hypervisor was imposing a limit here, but looking at
> xen_get_max_pages(), xen_foreach_remap_area(), and
> On 01/18, Elena Reshetova wrote:
> >
> > For the signal_struct.sigcnt it might make a difference
> > in following places:
> > - put_signal_struct(): decrement in refcount_dec_and_test() only
> >provides RELEASE ordering and control dependency on success
> >vs. fully ordered atomic counte
On Thu, Jan 17, 2019 at 05:10:38PM +0100, Codrin Ciubotariu - M19940 wrote:
> From: Codrin Ciubotariu
>
> atchan->status is used for two things:
> - pass channel interrupts status from interrupt handler to tasklet;
> - channel information like whether it is cyclic or paused;
>
> Since these op
On 2019-01-22 07:33, Alok Chauhan wrote:
> Get the interconnect paths for I2C based Serial Engine device
> and vote accordingly based on maximum supported I2C frequency.
>
> Signed-off-by: Alok Chauhan
> ---
> drivers/i2c/busses/i2c-qcom-geni.c | 13 +
> 1 file changed, 13 insertions
/commits/Vladimir-Zapolskiy/pinctrl-remove-unused-pinconf-config-debugfs-interface/20190122-044655
base:
https://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl.git devel
config: i386-randconfig-x0-01221345 (attached as .config)
compiler: gcc-5 (Debian 5.5.0-3) 5.4.1 20171010
reproduce
On Tue, Jan 22, 2019 at 05:02:43PM +0800, Jitao Shi wrote:
> Use the mtk_pwm_data struction to define different registers
> and add MT8183 specific register operations, such as MT8183
> doesn't have commit register, needs to disable double buffer
> before writing register, and needs to select commi
On Tue, 22 Jan 2019 09:00:14 +
Yogesh Narayan Gaur wrote:
> Hi Rob / Shawn,
>
> Can you please apply patches [1] [2].
No, DT bindings should go through Mark's tree. Just wait a bit please.
On Tue, Jan 22, 2019 at 09:32:32AM +0200, Priit Laes wrote:
> From: Priit Laes
>
> Although TMDS clock is required for HDMI to properly function,
> nobody called clk_prepare_enable(). This fixes reference counting
> issues and makes sure clock is running when it needs to be running.
>
> Due to T
On Monday, January 21, 2019 9:37:08 AM CET Greg KH wrote:
> On Mon, Jan 21, 2019 at 09:14:00AM +0100, Federico Vaga wrote:
> > On Monday, January 21, 2019 2:43:38 AM CET Jonathan Corbet wrote:
> > > On Fri, 18 Jan 2019 22:58:04 +0100
> > >
> > > Federico Vaga wrote:
> > > > The link referred by t
On Tue, Jan 15, 2019 at 03:18:56PM +1100, Finn Thain wrote:
> A multi-platform kernel binary has to decide at run-time how to dispatch
> the arch_nvram_ops calls. Add a platform-independent arch_nvram_ops
> struct for this, to replace the atari-specific one.
>
> Enable CONFIG_HAVE_ARCH_NVRAM_OPS f
Hi Boris,
> -Original Message-
> From: Boris Brezillon [mailto:bbrezil...@kernel.org]
> Sent: Tuesday, January 22, 2019 2:47 PM
> To: Yogesh Narayan Gaur
> Cc: r...@kernel.org; shawn...@kernel.org; mark.rutl...@arm.com;
> devicet...@vger.kernel.org; linux-kernel@vger.kernel.org;
> frieder
On, Jan 14, 2019 at 10:10:05PM +0800, Guan Yung Tseng wrote:
>> Modified NI devices class to PCI_CLASS_COMMUNICATION_MULTISERIAL.
>> The reason of doing this is because all NI multi port serial cards
>> use PCI_CLASS_COMMUNICATION_OTHER class and thus fail the
>> serial_pci_is_class_communication t
On Tue, Jan 22, 2019 at 10:19:17AM +0100, Greg Kroah-Hartman wrote:
> On Tue, Jan 15, 2019 at 03:18:56PM +1100, Finn Thain wrote:
> > A multi-platform kernel binary has to decide at run-time how to dispatch
> > the arch_nvram_ops calls. Add a platform-independent arch_nvram_ops
> > struct for this,
On Mon, Jan 14, 2019 at 09:44:15PM +0100, Mathieu Malaterre wrote:
> There is a plan to build the kernel with -Wimplicit-fallthrough and
> this place in the code produced a warning (W=1).
>
> This commit remove the following warning:
>
> drivers/char/generic_nvram.c:83:3: warning: this statemen
From: "james qian wang (Arm Technology China)"
1. Add detailed layer/layer_state definitions
2. Add d71_layer_init to report layer features and capabilities according
to D71 layer block.
3. Add d71_layer_updat/disable
v2: Rebase.
Signed-off-by: James Qian Wang (Arm Technology China)
---
..
On Tue, Jan 15, 2019 at 03:18:56PM +1100, Finn Thain wrote:
> The "generic" NVRAM module, drivers/char/generic_nvram.c, implements a
> /dev/nvram misc device. This module is used only by 32-bit PowerPC
> platforms.
>
> The RTC "CMOS" NVRAM module, drivers/char/nvram.c, also implements a
> /dev/nvr
From: "james qian wang (Arm Technology China)"
D71 consists of a number of Register Blocks, every Block controls a
specific HW function, every block has a common block_header to represent
its type and pipeline information.
GCU (Global Control Unit) is the first Block which describe the global
in
This is the 2nd patchset for komeda-driver.
These patches focus on CHIP(D71) Layer for pipeline/component descovery and
initialization. All basic and essential display component: layer, compiz,
improc, timing-ctrlr and irq handling have been added, other component
support: scaler, wb_layer, merger
From: "james qian wang (Arm Technology China)"
Add a debugfs node "register" and entry function dump_register to
dev/pipeline/component to register dump, then user can read
"/sys/kernel/debug/komeda/register" to get the register values via these
chip function.
Signed-off-by: James Qian Wang (Arm
From: "james qian wang (Arm Technology China)"
komeda_accemble_pipelines is for:
1. Verifing the component->supported_inputs according to the
pipeline->avail_components.
2. Generating component->supported_outputs.
v2: Lower the debug message of komeda_component_dump to DRM_DEBUG.
Signed-off
From: "james qian wang (Arm Technology China)"
Implement d71_compiz_init and add compiz component to komeda-CORE
v2: Rebase.
Signed-off-by: James Qian Wang (Arm Technology China)
---
.../arm/display/komeda/d71/d71_component.c| 92 ++-
.../drm/arm/display/komeda/komeda_pipe
From: "james qian wang (Arm Technology China)"
1. Added irq_handler/irq_enable/irq_disable to komeda_dev_func, then the
Komeda-CORE can control the HW irq via these chip function.
2. Install irq and register irq_handler to system by DRM, so once the IRQ
coming, the handling sequence is:
This is a note to let you know that I've just added the patch titled
ihex: Share code between ihex_validate_fw() and ihex_next_binrec()
to my driver-core git tree which can be found at
git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core.git
in the driver-core-testing branch
This is a note to let you know that I've just added the patch titled
tools/firmware/ihex2fw: Simplify next record offset calculation
to my driver-core git tree which can be found at
git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core.git
in the driver-core-testing branch.
This is a note to let you know that I've just added the patch titled
ihex: Check if zero-length record is at the end of the blob
to my driver-core git tree which can be found at
git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core.git
in the driver-core-testing branch.
The
This is a note to let you know that I've just added the patch titled
tools/firmware/ihex2fw: Replace explicit alignment with ALIGN
to my driver-core git tree which can be found at
git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core.git
in the driver-core-testing branch.
Th
From: "james qian wang (Arm Technology China)"
Add and initialize improc and timing_ctrlr according to D71 capablitites
v2: Rebase.
Signed-off-by: James Qian Wang (Arm Technology China)
---
.../arm/display/komeda/d71/d71_component.c| 111 +-
.../gpu/drm/arm/display/komeda/
This is a note to let you know that I've just added the patch titled
ihex: Simplify next record offset calculation
to my driver-core git tree which can be found at
git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core.git
in the driver-core-testing branch.
The patch will sho
On Tue, 2019-01-08 at 21:50 +0800, Jianxin Pan wrote:
> When CLK_DIVIDER_ONE_BASED flag is set, the sclk divider will be:
> one based divider (div = val), and zero value gates the clock
>
> Signed-off-by: Jianxin Pan
> ---
> drivers/clk/meson/Makefile | 3 ++-
> drivers/clk/meson/clkc-audio
On Tue, 2019-01-22 at 11:35 +0800, Ryder Lee wrote:
> On Mon, 2019-01-21 at 19:59 +0800, Jianjun Wang wrote:
> > There is no need to create the inner domain as a parent for MSI domian,
> > some feature has been implemented by MSI framework.
> >
> > Remove the inner domain and its irq chip, it will
On Tue, 2019-01-08 at 21:50 +0800, Jianxin Pan wrote:
> From: Yixun Lan
>
> The patch will add a MMC clock controller driver which used by MMC or NAND,
> It provide a mux and divider clock, and three phase clocks - core, tx, tx.
>
> Two clocks are provided as the parent of MMC clock controller f
On Tue, Dec 25, 2018 at 11:29:11PM -0600, Kangjie Lu wrote:
> When memory_read_from_buffer() fails, the return value is a negative
> error code, thus we shouldn't count it as the number of read bytes.
>
> The fix checks the return value of memory_read_from_buffer, and count
> the number only when
On Tue, Jan 22, 2019 at 09:11:42AM +, Reshetova, Elena wrote:
> Will you be able to take this and the other scheduler
> patch to whatever tree/path it should normally go to get eventually
> integrated?
I've queeud them up.
On Mon, Jan 21, 2019 at 11:48 PM Christian Brauner wrote:
>
> On Mon, Jan 21, 2019 at 03:44:17PM -0700, Jens Axboe wrote:
> > On 1/21/19 1:23 PM, Christian Brauner wrote:
> > > On Mon, Jan 21, 2019 at 09:15:27PM +0100, Arnd Bergmann wrote:
> > >> On Mon, Jan 21, 2019 at 8:13 PM Christian Brauner
On Tue, 2019-01-08 at 21:50 +0800, Jianxin Pan wrote:
> From: Yixun Lan
>
> Document the MMC sub clock controller driver, the potential consumer
> of this driver is MMC or NAND. Also add four clock bindings IDs which
> provided by this driver.
>
> Reviewed-by: Rob Herring
> Signed-off-by: Yixun
Hello Stephen,
On 1/19/2019 12:31 AM, Stephen Boyd wrote:
Quoting Taniya Das (2019-01-17 03:19:22)
On 1/15/2019 3:55 AM, Stephen Boyd wrote:
Quoting Taniya Das (2019-01-13 22:12:39)
On 1/8/2019 2:34 AM, Stephen Boyd wrote:
As far as I know, I'm not suggesting the use of CLK_IS_CRITICAL
On Tue, Jan 22, 2019 at 10:26:56AM +0100, Arnd Bergmann wrote:
> On Mon, Jan 21, 2019 at 11:48 PM Christian Brauner
> wrote:
> >
> > On Mon, Jan 21, 2019 at 03:44:17PM -0700, Jens Axboe wrote:
> > > On 1/21/19 1:23 PM, Christian Brauner wrote:
> > > > On Mon, Jan 21, 2019 at 09:15:27PM +0100, Arn
Drivers under MIT, BSD-17-clause, or uncle-Bob's-newest-take-on-PD are
all fine, not just GPL.
Signed-off-by: Adam Borowski
---
Not reformatting to fill lines, it'll semi-conflict with another patch
that's been acked but not yet pushed.
Documentation/process/stable-api-nonsense.rst | 3 ++-
1 f
> On Tue, Jan 22, 2019 at 09:11:42AM +, Reshetova, Elena wrote:
> > Will you be able to take this and the other scheduler
> > patch to whatever tree/path it should normally go to get eventually
> > integrated?
>
> I've queeud them up.
Thank you!
Best Regards,
Elena.
Hello,
Am 17.01.19 um 21:05 schrieb Dan Murphy:
> Migrate the m_can code to use the m_can_platform framework
> code.
>
> Signed-off-by: Dan Murphy
> ---
> drivers/net/can/m_can/Kconfig | 12 +
> drivers/net/can/m_can/Makefile | 4 +-
> drivers/net/can/m_can/m_can.c
Hi Bin,
Sorry to bother you again, I encounter a problem about the extcon
property.
I don't find a common driver describing the usb-connector. Is
there any driver that I can refer to, specially the way to switch MUSB
controller between host and device mode?
If it needs to implement by myself, is
On Mon, Jan 21, 2019 at 03:44:12PM +, Patrick Bellasi wrote:
> On 21-Jan 16:33, Peter Zijlstra wrote:
> > On Tue, Jan 15, 2019 at 10:15:02AM +, Patrick Bellasi wrote:
> >
> > > +static inline void
> > > +uclamp_task_update_active(struct task_struct *p, unsigned int clamp_id)
> > > +{
> > >
On Fri, Jan 18, 2019 at 7:50 PM Andy Lutomirski wrote:
> On Fri, Jan 18, 2019 at 8:25 AM Arnd Bergmann wrote:
>
> I have a patch that I'll send soon to make x32 use its own table. As
> far as I'm concerned, 547 is *it*. 548 is just a normal number and is
> not special. But let's please not reu
On Mon, Jan 14, 2019 at 4:36 PM Jon Hunter wrote:
> I have noticed that system suspend has started failing consistently on a
> couple Tegra boards over the last few days with the linux-next branch.
> The following error is seen on on entering suspend ...
>
> [ 58.222033] spi_master spi1: could n
There is no need to create the inner domain as a parent for MSI domian,
some feature has been implemented by MSI framework.
Remove the inner domain and its irq chip, it will be more closer to
hardware implementation.
Signed-off-by: Jianjun Wang
---
drivers/pci/controller/pcie-mediatek.c | 86 ++
On Tue, Jan 22, 2019 at 03:25:07AM +0800, Peng Hao wrote:
> Add pvpanic driver framework.
>
You need a lot more description of what you did here than this, as I can
not understand from this text, what the patch does, or more importantly,
why it is doing this, at all.
> Signed-off-by: Peng Hao
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