Ben, please backport Thomas Gleixner's patch to the 3.16 series.
commit ef1d4deab953ecb1dfcf9f167043bda8b3f14a11
Author: Thomas Gleixner
Date: Thu Aug 31 20:08:16 2017 +0200
x86/eisa: Add missing include
The seperation of the EISA init missed to include linux/io.h which breaks
the
Am Freitag, den 18.01.2019, 14:59 +0100 schrieb Stefan Agner:
> Explicitly specify interrupt affinity to avoid HW perfevents
> need to guess. This avoids the following error upon boot:
> hw perfevents: no interrupt-affinity property for /pmu, guessing.
>
But then it isn't correct either AFAICS.
Em Thu, Jan 17, 2019 at 01:03:20PM -0800, Stephane Eranian escreveu:
> On Thu, Jan 10, 2019 at 5:17 PM Stephane Eranian wrote:
> >
> > The perf_proc_update_handler() handles
> > /proc/sys/kernel/perf_event_max_sample_rate
> > syctl variable. When the PMU IRQ handler timing monitoring is disabled
Hi,
On Fri, Jan 18, 2019 at 5:07 AM, Boris Brezillon
wrote:
Hi Paul,
On Thu, 17 Jan 2019 22:06:27 -0300
Paul Cercueil mailto:p...@crapouillou.net>>
wrote:
This is currently done inside the jz4780-bch driver, but it really
should be done here instead.
I disagree with that statement. I
Hi Miquel,
On mar., janv. 08 2019, Miquel Raynal wrote:
> The error message should state that the driver failed to get the
> parent clock, not the opposite.
>
> Signed-off-by: Miquel Raynal
Reviewed-by: Gregory CLEMENT
Thanks,
Gregory
> ---
> drivers/clk/mvebu/armada-37xx-tbg.c | 2 +-
>
Hi Miquel,
On mar., janv. 08 2019, Miquel Raynal wrote:
> So far the clk_hw_register_fixed_factor() calls are not providing any
> device structure. While doing so is harmless for regular use, the
> missing device structure may be a problem for suspend to RAM support.
>
> Since, device links ha
Hi Miquel,
On mar., janv. 08 2019, Miquel Raynal wrote:
> So far the clk_hw_register_fixed_factor() call was not providing any
> device structure. While doing so is harmless for regular use, the
> missing device structure may be a problem for suspend to RAM support.
>
> Since, device links hav
Hi,
On Fri, Jan 18, 2019 at 12:52:38PM +, Zhang, Lei wrote:
> On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1),
> memory accesses may cause undefined fault (Data abort, DFSC=0b11).
So that we can better understand the problem, could you please let us
know the following:
* Under
On Fri, Jan 18, 2019 at 03:03:22PM +0100, Corentin Labbe wrote:
> Hello
>
> Thirteen years later, coding style have change a bit.
> This patch series fixes the gap.
>
> This patch serie was tested on my precious so rare real hardware.
>
Series applied to hwmon-next.
Thanks,
Guenter
> Regards
>
Hi,
On Fri, Jan 18, 2019 at 5:35 AM, Boris Brezillon
wrote:
On Thu, 17 Jan 2019 22:06:33 -0300
Paul Cercueil mailto:p...@crapouillou.net>>
wrote:
The jz4780-nand driver uses an API provided by the jz4780-bch
driver.
This makes it difficult to support other SoCs in the jz4780-bch
driver.
Hello, Linus.
On Sat, Jan 05, 2019 at 01:54:03PM -0800, Linus Torvalds wrote:
> And the first hit is 'fincore', which probably nobody cares about
> anyway, but it does
>
> fd = open (name, O_RDONLY)
> ..
> mmap(window, len, PROT_NONE, MAP_PRIVATE, ..
So, folks here have been using fi
I get this on a Geminilake NUC after rebasing my maintainer trees:
tpm tpm0: A TPM error (-1) occurred attempting the self test
I checked the latest commit ID from drivers/char/tpm to make sure
that I did not put anything broken to my last PR [1]. It works
without issues.
In addition [2] gives m
From: Shengjiu Wang
When stopping audio, ASoC will first stop DMA then CPU DAI.
Sometimes there is a delay between DMA stop and CPU DAI stop, which
triggers an underrun error. Now, because of the delay introduced
by dev_err another underrun error will occur causing a vicious circle
making impossi
On Thu, Jan 17, 2019 at 08:38:15AM -0800, Stefan Schaeckeler wrote:
> From: Stefan M Schaeckeler
>
> Add support for the Aspeed AST2500 SoC EDAC driver.
>
> Changes since v1:
> - Addressed all cosmetic issues
> - Fixed (un-)recoverable address calculation in reg58 and reg5c
> - Removed status fi
On Fri, Jan 18, 2019 at 9:42 PM Kairui Song wrote:
>
> On Fri, Jan 18, 2019 at 8:37 PM Dave Young wrote:
> >
> > On 01/18/19 at 08:34pm, Dave Young wrote:
> > > On 01/18/19 at 06:53am, Mimi Zohar wrote:
> > > > On Fri, 2019-01-18 at 17:17 +0800, Kairui Song wrote:
> > > > > This patch series adds
+CC: Hans
On 17.01.2019 20:47, Ville Syrjälä wrote:
> On Fri, Dec 14, 2018 at 01:10:16PM +0100, Christoph Manszewski wrote:
>> Range setting makes sense for YCbCr and RGB buffers. Current
>> drm_color_range enum labels suggest use with YCbCr buffers.
>> Create enum labels without colorspace specif
Steeve, all,
On 1/17/19 3:49 PM, Steve Longerbeam wrote:
Disable the CSI immediately after receiving the last EOF before stream
off (and thus before disabling the IDMA channel).
This fixes a complete system hard lockup on the SabreAuto when streaming
from the ADV7180, by repeatedly sending a st
On Fri, Jan 11, 2019 at 07:28:58AM -0800, James Bottomley wrote:
> On Fri, 2019-01-11 at 16:02 +0200, Jarkko Sakkinen wrote:
> > On Tue, Jan 08, 2019 at 05:43:53PM -0800, Andy Lutomirski wrote:
> > > (Also, do we have a sensible story of how the TPM interacts with
> > > hibernation at all? Presuma
Commit 8ce5f8415753 ("of: Remove struct device_node.type pointer")
removed struct device_node.type pointer, but the conversion to use
of_node_is_type() accessor was missed in chrp_init_IRQ().
Fixes: 8ce5f8415753 ("of: Remove struct device_node.type pointer")
Reported-by: kbuild test robot
Cc: Ben
Steve, all,
On 1/17/19 3:49 PM, Steve Longerbeam wrote:
The CSI must be disabled immediately after receiving the last EOF before
stream off (and thus before disabling the IDMA channel). This can be
accomplished by moving upstream stream off to just after receiving the
last EOF completion in prp_
Hi Marek,
On mar., nov. 13 2018, Marek Behún wrote:
> This is a RFC, please do not merge.
>
> This adds basic support for the Turris Mox board from CZ.NIC.
>
> Turris Mox is as modular router based on the Armada 3720 SOC (same as
> EspressoBin).
>
> The basic module can be extended by differen
On 01/18/2019 04:17 AM, Kairui Song wrote:
commit 9dc92c45177a ('integrity: Define a trusted platform keyring')
introduced a .platform keyring for storing preboot keys, used for
verifying kernel images' signature. Currently only IMA-appraisal is able
to use the keyring to verify kernel images
On Fri, Jan 11, 2019 at 03:19:56PM -0800, Sean Christopherson wrote:
> On Fri, Jan 11, 2019 at 02:58:26PM +0200, Jarkko Sakkinen wrote:
> > On Wed, Jan 09, 2019 at 08:31:37AM -0800, Sean Christopherson wrote:
> > > On Tue, Jan 08, 2019 at 02:54:11PM -0800, Andy Lutomirski wrote:
> > > > On Tue, Jan
Since commit 01973a01f9ec34b7 ("eeprom: at25: remove nvmem regmap
dependency") changed the type of "off" from "loff_t" to "unsigned int",
"off" and "offset" are now the same type, and can be merged into a
single variable.
Signed-off-by: Geert Uytterhoeven
---
v2:
- Merge "off" and "offset" into
On Fri, Jan 18, 2019 at 02:40:00PM +0100, Vlastimil Babka wrote:
> > Signed-off-by: Mel Gorman
>
> Great, you crossed off this old TODO item, and didn't need pageblock isolation
> to do that :D
>
The TODO is not just old, it's ancient! The idea of capture was first
floated in 2008! A version wa
Reduce code duplication in at25_ee_read() by using the
spi_message_init_with_transfers() helper.
Signed-off-by: Geert Uytterhoeven
Acked-by: Arnd Bergmann
---
v2:
- Add Acked-by.
---
drivers/misc/eeprom/at25.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/mi
Hi all,
This patch series contains two improvements for the AT25 SPI EEPROM
driver, related to SPI transfers.
Changes compared to v1:
- Merge "off" and "offset" into a single variable instead of just
killing the cast, as suggested by Arnd,
- Add Acked-by,
- Dropped "[PATCH 3/3]
On Fri, Jan 18, 2019 at 09:53:20AM +0530, Srinath Mannam wrote:
> Add changes related to IPROC PCIe RC IP new features.
>
> This patch set is based on Linux-5.0-rc2.
>
> Srinath Mannam (3):
> PCI: iproc: Add feature to set order mode
Since this apparently refers to a PCIe feature, the subject
This series implements support for YUV formats using the display engine
frontend in the sun4i DRM driver, with various fixes along the way.
Scaling is supported for every format handled by the frontend.
The tiling mode used by the VPU on Allwinner platforms is also supported
by this series and a d
Both the backend and the frontend need the BT.601 CSC coefficients for
YUV to RGB conversion. Since the backend has a dependency on the
frontend (and not the other way round), move the coefficients there
so that both can access them without having to duplicate them.
Signed-off-by: Paul Kocialkowsk
The helper returning the input mode needs to know the number of planes
for the provided format. Passing the fourcc requires iterating through
the format info list in order to return the number of planes.
Pass the DRM format info structure directly instead to all helpers
related to configuring the
Since all the RGB input formats have the same value for the DATA_FMT
field of the INPUT_FMT register, we can group them when the format is
known to be RGB. Here, we assume that a non-YUV format is RGB, because
the hardware does not support any other colorspace than RGB and YUV.
Use the DRM format
From: Maxime Ripard
The COEF_RDY bit isn't found in all the SoCs featuring some variant of the
frontend.
Add it to our quirks structure.
Signed-off-by: Maxime Ripard
Signed-off-by: Paul Kocialkowski
---
drivers/gpu/drm/sun4i/sun4i_frontend.c | 9 +
drivers/gpu/drm/sun4i/sun4i_fronten
From: Maxime Ripard
The FIR filters phase depend on the SoC, so let's move it to our quirks
structure instead of removing them.
Signed-off-by: Maxime Ripard
Signed-off-by: Paul Kocialkowski
---
drivers/gpu/drm/sun4i/sun4i_frontend.c | 28 --
drivers/gpu/drm/sun4i/sun4i
On Fri, Jan 18, 2019 at 03:34:18PM +0100, Andrzej Hajda wrote:
> +CC: Hans
>
> On 17.01.2019 20:47, Ville Syrjälä wrote:
> > On Fri, Dec 14, 2018 at 01:10:16PM +0100, Christoph Manszewski wrote:
> >> Range setting makes sense for YCbCr and RGB buffers. Current
> >> drm_color_range enum labels sugg
This is the final step to indicate to the core that our driver
supports framebuffer modifiers.
Signed-off-by: Paul Kocialkowski
Acked-by: Maxime Ripard
---
drivers/gpu/drm/sun4i/sun4i_drv.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/sun4i/sun4i_drv.c
b/drivers/gpu/drm/
This adds the appropriate device-tree compatible for hooking frontend
support for the A20. Since the hardware is very similar to the A10, it
shares the same quirks (which were already introduced).
Signed-off-by: Paul Kocialkowski
---
drivers/gpu/drm/sun4i/sun4i_frontend.c | 4
1 file change
This introduces stride and offset configuration for the VPU tiling mode.
Stride is calculated differently than it is for linear formats and an
offset is calculated, for which new register definitions are introduced.
Signed-off-by: Paul Kocialkowski
---
drivers/gpu/drm/sun4i/sun4i_frontend.c | 49
This introduces support for packed YUV formats with 4:2:2 sampling using
the frontend. Definitions are introduced for the data format and pixel
sequence input format register values.
Signed-off-by: Paul Kocialkowski
Acked-by: Maxime Ripard
---
drivers/gpu/drm/sun4i/sun4i_frontend.c | 22 +++
This adds the appropriate device-tree compatible and quirk data for
hooking frontend support for the A20. It supports the FIR coefficients
ready bit but not the access control bit. It also takes different phase
values than the A33 for these coefficients.
The compatible is already used in the A10 d
Hi Paul,
On dim., déc. 09 2018, Paul Gortmaker wrote:
> The Kconfig currently controlling compilation of this code is:
>
> drivers/phy/marvell/Kconfig:config ARMADA375_USBCLUSTER_PHY
> drivers/phy/marvell/Kconfig:def_bool y
>
> ...meaning that it currently is not being built as a module by
From: Maxime Ripard
The ACCESS_CTRL bit is not found on all the variants of the frontend, so
let's introduce a structure that will hold whether or not we need to set
it, and associate it with the compatible.
This will be extended for further similar quirks later on.
Signed-off-by: Maxime Ripard
This introduces specific definitions for vendor Allwinner and its
associated tiled format modifier. This modifier is used for the output
format of the VPU, that can be imported directly with the display
engine hardware supported by the sun4i-drm driver.
Signed-off-by: Paul Kocialkowski
Reviewed-b
This introduces a list of supported modifiers for the driver, that
includes the Allwinner tiled modifier, as well as a format_mod_supported
callback.
The callback uses both the backend and frontend helpers to indicate
per-format modifier support (including for the linear modifier).
Signed-off-by:
This introduces a helper to check whether a frontend input format
supports tiling mode. This helper is used when tiling is requested in
the frontend format support helper.
Only semiplanar and planar YUV formats are supported by the hardware.
Signed-off-by: Paul Kocialkowski
Acked-by: Maxime Ripa
Semi-planar YUV formats use two distinct planes, one for luminance and
one for chrominance. To add support for them, we need to configure the
second line stride and buffer address registers to setup the second YUV
plane.
New definitions are introduced to configure the input format register
for the
Checking for the number of planes is not sufficient to en ensure that
the format is a packed YUV422.
Use explicit fourcc helpers for the check instead.
Signed-off-by: Paul Kocialkowski
Acked-by: Maxime Ripard
---
drivers/gpu/drm/sun4i/sun4i_backend.c | 3 ++-
1 file changed, 2 insertions(+), 1
This introduces the data input mode definitions for the tiled YUV mode,
that are used in the input mode helper if tiling is requested.
The modifier is passed to the helper from the framebuffer to determine
if tiling is requested.
Only semiplanar and planar YUV formats are supported for tiling mod
Em Thu, Jan 17, 2019 at 08:15:17AM -0800, Song Liu escreveu:
> This patch handles PERF_RECORD_KSYMBOL in perf record/report.
> Specifically, map and symbol are created for ksymbol register, and
> removed for ksymbol unregister.
>
> This patch also set perf_event_attr.ksymbol properly. The flag is
On Fri, Jan 18, 2019 at 02:51:00PM +0100, Vlastimil Babka wrote:
> On 1/4/19 1:50 PM, Mel Gorman wrote:
> > Remote compaction is expensive and possibly counter-productive. Locality
> > is expected to often have better performance characteristics than remote
> > high-order pages. For small allocatio
From: Maxime Ripard
Unlike what is currently being done, the ACCESS_CTRL bit documentation asks
that this bit should be set before modifying any register. The code in the
BSP also does this, so make sure we do this as well.
Signed-off-by: Maxime Ripard
Signed-off-by: Paul Kocialkowski
---
dri
Planar YUV formats come with 3 distinct planes, which requires
configuring the frontend line stride and address registers for the
third plane.
Our hardware only supports the YUV planes order and in order to support
formats with a YVU plane order, a helper is introduced to indicate
whether to inver
From: Maxime Ripard
The COEF_RDY bit is used to tell the hardware that new FIR filters
coefficients have been written to the registers and that the hardware
should take them into account starting next frame.
Signed-off-by: Maxime Ripard
Signed-off-by: Paul Kocialkowski
---
drivers/gpu/drm/sun
Em Thu, Jan 17, 2019 at 08:15:18AM -0800, Song Liu escreveu:
> This patch adds basic handling of PERF_RECORD_BPF_EVENT.
> Tracking of PERF_RECORD_BPF_EVENT is OFF by default. Option --bpf-event
> is added to turn it on.
ditto
> Signed-off-by: Song Liu
> ---
> tools/perf/builtin-record.c | 1 +
In prevision of adding support for YUV formats, set the YUV to RGB
colorspace conversion coefficients if required and don't bypass the
CSC engine when converting.
The BT601 coefficients from the A33 BSP are copied over from the backend
code. Because of module inter-dependency, we can't have the fr
Display engine drivers often need to distinguish between different types of
YUV sub-sampling. This introduces helpers to check for common sub-sampling
ratios in their commonly-used denomination from the DRM format info.
Signed-off-by: Paul Kocialkowski
Reviewed-by: Maxime Ripard
---
include/drm
It is often useful to check whether the DRM format info retrieved from
the DRM framebuffer matches a specific YUV planes disposition.
This introduces helpers to quickly check that a provided format info
matches a YUV format with a specific disposition, in commonly-used
terminology.
The intent of
Em Thu, Jan 17, 2019 at 08:15:19AM -0800, Song Liu escreveu:
> This patch synthesize PERF_RECORD_KSYMBOL and PERF_RECORD_BPF_EVENT for
> BPF programs loaded before perf-record. This is achieved by gathering
> information about all BPF programs via sys_bpf.
Ditto
> Signed-off-by: Song Liu
> ---
The percpu member of this structure is declared as:
struct ... ** __percpu member;
So its type is:
__percpu pointer to pointer to struct ...
But looking at how it's used, its type should be:
pointer to __percpu pointer to struct ...
and it should thus be declared as:
The percpu members of these structure are declared as:
struct ... ** __percpu member;
So their type is:
__percpu pointer to pointer to struct ...
But looking at how they're used, their type should be:
pointer to __percpu pointer to struct ...
and they should thus be declare
On 01/18/2019 05:02 AM, Peter Zijlstra wrote:
>
>> e.g. We can't take an SError during the SError handler.
>>
>> But we can take this SError/NMI on another CPU while the first one is still
>> running the handler.
>>
>> These multiple NMIlike notifications mean having multiple locks/fixmap-slots,
>>
This series implements support for YUV formats using the display engine
frontend in the sun4i DRM driver, with various fixes along the way.
Scaling is supported for every format handled by the frontend.
The tiling mode used by the VPU on Allwinner platforms is also supported
by this series and a d
Since all the RGB input formats have the same value for the DATA_FMT
field of the INPUT_FMT register, we can group them when the format is
known to be RGB. Here, we assume that a non-YUV format is RGB, because
the hardware does not support any other colorspace than RGB and YUV.
Use the DRM format
Semi-planar YUV formats use two distinct planes, one for luminance and
one for chrominance. To add support for them, we need to configure the
second line stride and buffer address registers to setup the second YUV
plane.
New definitions are introduced to configure the input format register
for the
This introduces stride and offset configuration for the VPU tiling mode.
Stride is calculated differently than it is for linear formats and an
offset is calculated, for which new register definitions are introduced.
Signed-off-by: Paul Kocialkowski
Acked-by: Maxime Ripard
---
drivers/gpu/drm/su
This introduces support for packed YUV formats with 4:2:2 sampling using
the frontend. Definitions are introduced for the data format and pixel
sequence input format register values.
Signed-off-by: Paul Kocialkowski
Acked-by: Maxime Ripard
---
drivers/gpu/drm/sun4i/sun4i_frontend.c | 22 +++
This is the final step to indicate to the core that our driver
supports framebuffer modifiers.
Signed-off-by: Paul Kocialkowski
Acked-by: Maxime Ripard
---
drivers/gpu/drm/sun4i/sun4i_drv.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/sun4i/sun4i_drv.c
b/drivers/gpu/drm/
From: Maxime Ripard
The ACCESS_CTRL bit is not found on all the variants of the frontend, so
let's introduce a structure that will hold whether or not we need to set
it, and associate it with the compatible.
This will be extended for further similar quirks later on.
Signed-off-by: Maxime Ripard
This introduces a helper to check whether a frontend input format
supports tiling mode. This helper is used when tiling is requested in
the frontend format support helper.
Only semiplanar and planar YUV formats are supported by the hardware.
Signed-off-by: Paul Kocialkowski
Acked-by: Maxime Ripa
From: Maxime Ripard
The FIR filters phase depend on the SoC, so let's move it to our quirks
structure instead of removing them.
Signed-off-by: Maxime Ripard
Signed-off-by: Paul Kocialkowski
---
drivers/gpu/drm/sun4i/sun4i_frontend.c | 28 --
drivers/gpu/drm/sun4i/sun4i
On Fri, Jan 11, 2019 at 12:55:38PM -0300, Arnaldo Carvalho de Melo wrote:
> Hi Peter,
>
> bpf_perf_event_open() already returns a value, but if
> perf_event_output's output_begin (mostly perf_output_begin) fails,
> the only way to know about that is looking before/after the rb->lost,
> right
From: Maxime Ripard
Unlike what is currently being done, the ACCESS_CTRL bit documentation asks
that this bit should be set before modifying any register. The code in the
BSP also does this, so make sure we do this as well.
Signed-off-by: Maxime Ripard
Signed-off-by: Paul Kocialkowski
---
dri
On Fri, Jan 18, 2019 at 11:35:34AM -0200, Marcelo Ricardo Leitner wrote:
> On Fri, Jan 18, 2019 at 08:10:22AM -0500, Neil Horman wrote:
> > On Tue, Jan 15, 2019 at 12:29:26PM -0200, Marcelo Ricardo Leitner wrote:
> > > On Mon, Dec 17, 2018 at 04:00:21PM -0500, Kent Overstreet wrote:
> > > > On Mon,
This adds the appropriate device-tree compatible for hooking frontend
support for the A20. Since the hardware is very similar to the A10, it
shares the same quirks (which were already introduced).
Signed-off-by: Paul Kocialkowski
---
drivers/gpu/drm/sun4i/sun4i_frontend.c | 4
1 file change
From: Maxime Ripard
The COEF_RDY bit is used to tell the hardware that new FIR filters
coefficients have been written to the registers and that the hardware
should take them into account starting next frame.
Signed-off-by: Maxime Ripard
Signed-off-by: Paul Kocialkowski
---
drivers/gpu/drm/sun
From: Maxime Ripard
The COEF_RDY bit isn't found in all the SoCs featuring some variant of the
frontend.
Add it to our quirks structure.
Signed-off-by: Maxime Ripard
Signed-off-by: Paul Kocialkowski
---
drivers/gpu/drm/sun4i/sun4i_frontend.c | 9 +
drivers/gpu/drm/sun4i/sun4i_fronten
This adds the appropriate device-tree compatible and quirk data for
hooking frontend support for the A20. It supports the FIR coefficients
ready bit but not the access control bit. It also takes different phase
values than the A33 for these coefficients.
The compatible is already used in the A10 d
This introduces the data input mode definitions for the tiled YUV mode,
that are used in the input mode helper if tiling is requested.
The modifier is passed to the helper from the framebuffer to determine
if tiling is requested.
Only semiplanar and planar YUV formats are supported for tiling mod
This introduces a list of supported modifiers for the driver, that
includes the Allwinner tiled modifier, as well as a format_mod_supported
callback.
The callback uses both the backend and frontend helpers to indicate
per-format modifier support (including for the linear modifier).
Signed-off-by:
Planar YUV formats come with 3 distinct planes, which requires
configuring the frontend line stride and address registers for the
third plane.
Our hardware only supports the YUV planes order and in order to support
formats with a YVU plane order, a helper is introduced to indicate
whether to inver
This introduces specific definitions for vendor Allwinner and its
associated tiled format modifier. This modifier is used for the output
format of the VPU, that can be imported directly with the display
engine hardware supported by the sun4i-drm driver.
Signed-off-by: Paul Kocialkowski
Reviewed-b
Display engine drivers often need to distinguish between different types of
YUV sub-sampling. This introduces helpers to check for common sub-sampling
ratios in their commonly-used denomination from the DRM format info.
Signed-off-by: Paul Kocialkowski
Reviewed-by: Maxime Ripard
---
include/drm
The helper returning the input mode needs to know the number of planes
for the provided format. Passing the fourcc requires iterating through
the format info list in order to return the number of planes.
Pass the DRM format info structure directly instead to all helpers
related to configuring the
Both the backend and the frontend need the BT.601 CSC coefficients for
YUV to RGB conversion. Since the backend has a dependency on the
frontend (and not the other way round), move the coefficients there
so that both can access them without having to duplicate them.
Signed-off-by: Paul Kocialkowsk
Checking for the number of planes is not sufficient to en ensure that
the format is a packed YUV422.
Use explicit fourcc helpers for the check instead.
Signed-off-by: Paul Kocialkowski
Acked-by: Maxime Ripard
---
drivers/gpu/drm/sun4i/sun4i_backend.c | 3 ++-
1 file changed, 2 insertions(+), 1
It is often useful to check whether the DRM format info retrieved from
the DRM framebuffer matches a specific YUV planes disposition.
This introduces helpers to quickly check that a provided format info
matches a YUV format with a specific disposition, in commonly-used
terminology.
The intent of
In prevision of adding support for YUV formats, set the YUV to RGB
colorspace conversion coefficients if required and don't bypass the
CSC engine when converting.
The BT601 coefficients from the A33 BSP are copied over from the backend
code. Because of module inter-dependency, we can't have the fr
Hi Thomas,
Here's a handful of irqchip fixes for 5.0-rc3. Only the menu, an
uninitialised mutex, an interesting MSI allocation corner case in the ITS, a
stm32 DT parsing fix, and some cleanups.
Please pull,
M.
The following changes since commit bfeffd155283772bbe78c6a05dec7c0128ee500c:
Remove sys/socket.h and sys/uio.h which are included more than once
Signed-off-by: Sabyasachi Gupta
---
arch/um/drivers/vector_user.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/arch/um/drivers/vector_user.c b/arch/um/drivers/vector_user.c
index d2c17dd..c863921 100644
--- a/arch/um/dri
On Fri, Jan 11, 2019 at 08:28:00PM +, Safford, David (GE Global Research)
wrote:
> You might mention that this is an important feature, as on at least some
> systems, ppi function 23 is the only way to enable/disable PCR banks.
>
> I have tested this patch set on my HP Spectre laptop, and I a
This adds nodes for the Video Engine and the associated reserved memory
for the A10. Up to 96 MiB of memory are dedicated to the CMA pool.
The VPU can only map the first 256 MiB of DRAM, so the reserved memory
pool has to be located in that area. Following Allwinner's decision in
downstream softwa
This adds support for the C1 SRAM region (to be used with the SRAM
controller driver) for the A10 platform. The region is shared
between the Video Engine and the CPU.
Signed-off-by: Paul Kocialkowski
---
arch/arm/boot/dts/sun4i-a10.dtsi | 13 +
1 file changed, 13 insertions(+)
diff
On Wed, Jan 16, 2019 at 08:52:03PM -0200, Thiago Jung Bauermann wrote:
>
> Hello,
>
> Jarkko Sakkinen writes:
>
> > Added the tests that I've been using for testing TPM 2.0 functionality
> > for long time but have out-of-tree so far residing in
> >
> > https://github.com/jsakkine-intel/tpm2-scr
On Fri, Jan 18, 2019 at 10:36 PM Nayna wrote:
> On 01/18/2019 04:17 AM, Kairui Song wrote:
> > commit 9dc92c45177a ('integrity: Define a trusted platform keyring')
> > introduced a .platform keyring for storing preboot keys, used for
> > verifying kernel images' signature. Currently only IMA-appra
Adopt the SPDX license identifier headers to ease license compliance
management.
Signed-off-by: Gregory CLEMENT
---
drivers/phy/marvell/phy-armada375-usb2.c | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/drivers/phy/marvell/phy-armada375-usb2.c
b/drivers/phy/marvell/phy
On Fri, 18 Jan 2019, Ran Wang wrote:
> Hi Alan,
>
> On January 18, 2019 00:08, Alan Stern wrote:
> >
> > On Thu, 17 Jan 2019, Ran Wang wrote:
> >
> > > arm/arm64's io.h doesn't define clrbits32() and clrsetbits_be32(),
> > > which causing compile failure on some Layerscape Platforms (such as
>
On Wed, 16 Jan 2019 at 16:43, Tony Lindgren wrote:
>
> * Ulf Hansson [190116 11:37]:
> > During "wlan-up", we are programming the FW into the WiFi-chip. However,
> > re-programming the FW doesn't work, unless a power cycle of the WiFi-chip
> > is made in-between the programmings.
> >
> > To confo
On Fri, Jan 18, 2019 at 02:27:25PM +0200, Elena Reshetova wrote:
> I would really love finally to merge these old patches
> (now rebased on top of linux-next/master as of last friday),
> since as far as I remember none has raised any more concerns
> on them.
>
> refcount_t has been now successfull
Hello Christoph,
I was able to compile 257002094bc5935dd63207a380d9698ab81f0775 from your
Git powerpc-dma.6-debug today.
Unfortunately I don't see any error messages (kernel ring buffer) and I
don't have a RS232 serial null modem cable to get them.
Cheers,
Christian
On Fri, Jan 18, 2019 at 09:53:21AM +0530, Srinath Mannam wrote:
> Order mode in RX header of incoming pcie packets can be override to
> strict or loose order based on requirement.
> Sysfs entry is provided to set dynamic and default order modes of upstream
> traffic.
s/pcie/PCIe/
If this is two p
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