On Thu, Dec 06, 2018 at 06:53:06PM +0530, Jagan Teki wrote:
> Some camera modules have the SoC feeding a master clock to the sensor
> instead of having a standalone crystal. This clock signal is generated
> from the clock control unit and output from the CSI MCLK function of
> pin PE1.
>
> Add a p
On 6.12.2018 14:59, Uwe Kleine-König wrote:
> On Thu, Dec 06, 2018 at 01:41:31PM +, Vokáč Michal wrote:
>>
>> +static int imx_pwm_init_pinctrl_info(struct imx_chip *imx_chip,
>> +struct platform_device *pdev)
>
> Please indent the follow up line to the opening parenthesis.
Meh,
On 12/06/2018 03:41 AM, Peter Zijlstra wrote:
> On Wed, Dec 05, 2018 at 02:49:28PM -0500, Waiman Long wrote:
>> Since conditional STIBP is the default, it should be treated as
>> the likely case. Changes the use of static_branch_unlikely() to
>> static_branch_likely() for switch_to_cond_stibp.
> So
On Thu, Dec 06, 2018 at 08:08:24AM +1100, NeilBrown wrote:
> On Wed, Dec 05 2018, Nishad Kamdar wrote:
>
> > The below patch
> > https://lore.kernel.org/patchwork/patch/995533/
> > does not completely remove an #if 0 block in sd.c.
>
> Standard practice is to identify patches by their commit id.
On Thu, Dec 06, 2018 at 10:35:28AM -0500, Vince Weaver wrote:
> On Wed, 5 Dec 2018, Jiri Olsa wrote:
>
> > On Wed, Dec 05, 2018 at 12:11:19PM -0500, Vince Weaver wrote:
> > > On Wed, 5 Dec 2018, Jiri Olsa wrote:
> > >
> > > > On Wed, Dec 05, 2018 at 01:45:38PM +0100, Jiri Olsa wrote:
> > > > > On
> "Jean" == Jean Delvare writes:
Hi,
>> I get that - but it changes the content of sysfs entries, breaking real
>> systems - E.G. a user space ABI regression.
> I know it's very convenient to play the "user-space ABI regression"
> card whenever you want a change reverted.
Sorry, I am r
Hi All,
Please let me know if anyone has any issue with this patch series.
Regards,
Bharat
> -Original Message-
> From: Bharat Kumar Gogada [mailto:bharat.kumar.gog...@xilinx.com]
> Sent: Wednesday, November 14, 2018 8:18 PM
> To: linux-kernel@vger.kernel.org
> Cc: bhelg...@google.com; R
Hi All,
Please let me know if anyone has any issue with this patch.
Regards,
Bharat
> As per Figure 6-3 in PCIe r4.0, sec 6.2.6, ERR_ messages will be forwarded
> from the secondary interface to the primary interface, if the SERR# Enable
> bit in the Bridge Control register is set.
> Currently PC
On 2018-11-30 15:26, Dave Rodgman wrote:
> This patch series introduces performance improvements for lzo.
>
> The previous version of this patchset is here:
> https://lkml.org/lkml/2018/11/30/807
>
> This version of the patchset fixes a maybe-used-uninitialized warning
> (although the previous ve
On Wed, Dec 05, 2018 at 06:47:54PM -0500, Steven Rostedt wrote:
> From: "Steven Rostedt (VMware)"
>
> Functions in the set_graph_notrace no longer subtract FTRACE_NOTRACE_DEPTH
> from curr_ret_stack, as that is now implemented via the trace_recursion
> flags. Access to curr_ret_stack no longer ne
On Wed, 2018-12-05 at 17:13 +, Vineet Gupta wrote:
> On 12/5/18 9:06 AM, Eugeniy Paltsev wrote:
> > Fix description comment as this code doesn't belong only to
> > ARC700 anymore.
> >
> > Also while I'm at it, use SPDX License Identifier.
> >
> > Signed-off-by: Eugeniy Paltsev
>
> Maybe squ
Acked-by: Markus F.X.J. Oberhumer
On 2018-11-30 15:26, Dave Rodgman wrote:
> Modify the ifdefs in lzodefs.h to be more consistent with normal kernel
> macros (e.g., change __aarch64__ to CONFIG_ARM64).
>
> Signed-off-by: Dave Rodgman
> Cc: Herbert Xu
> Cc: David S. Miller
> Cc: Nitin Gupta
On Sun, 2018-11-25 at 10:04 +, Jonathan Cameron wrote:
> On Fri, 23 Nov 2018 15:24:10 +0100
> Philippe Schenker wrote:
>
> > From: Stefan Agner
> >
> > This adds the devicetree bindings for the STMPE ADC.
> >
> > Signed-off-by: Stefan Agner
> > Signed-off-by: Max Krummenacher
> > Signed-
Am Donnerstag, den 06.12.2018, 09:45 -0600 schrieb Robert Hancock:
> On 2018-12-06 2:10 a.m., Baruch Siach wrote:
> > Hi Andrey,
> >
> > Adding Robert Hancock who reported[1] on a PCIe MSI issue with i.MX6.
> >
> > Andrey Smirnov writes:
> >
> > > Building a kernel with CONFIG_PCI_IMX6=y, but CO
On 06/12/2018 15:11, Tony Battersby wrote:
On 12/6/18 4:25 AM, Krzysztof Kozlowski wrote:
On Thu, 6 Dec 2018 at 02:31, Tony Lindgren wrote:
Hi,
Looks like with commit 26abe88e830d ("mm/dmapool.c: improve scalability
of dma_pool_free()") I'm now getting spammed with lots of "(bad vaddr)"
on at
I think that LZO_USE_CTZ64 should only be defined for ARM64 and
not for 32-bit ARM.
On 2018-11-30 15:26, Dave Rodgman wrote:
> From: Matt Sealey
>
> ARMv6 Thumb state introduced an RBIT instruction which, combined with CLZ
> as present in ARMv5, introduces an extremely fast path for counting
>
[+ Ingo and Mark]
On Tue, Dec 04, 2018 at 10:47:13PM +0100, Anders Roxell wrote:
> Some distibutions and build systems doesn't include 'fold' from
> coreutils default.
>
> .../scripts/atomic/atomic-tbl.sh: line 183: fold: command not found
>
> Rework to use 'grep' instead of 'fold' to use a depe
Acked-by: Markus F.X.J. Oberhumer
On 2018-11-30 15:26, Dave Rodgman wrote:
> From: Matt Sealey
>
> LZO leaves some performance on the table by not realising that arm64 can
> optimize count-trailing-zeros bit operations.
>
> Add CONFIG_ARM64 to the checked definitions alongside CONFIG_X86_64
On Thu, Dec 06, 2018 at 08:34:09AM +0100, Ingo Molnar wrote:
> I like your '!' idea, but with a further simplification: how about using
> '-/+' differentiation and a single character and a fixed-length message.
>
> The new output will be lines of:
>
> #PF error code: -P -W -U -S -I -K (0x00)
>
Acked-by: Markus F.X.J. Oberhumer
On 2018-11-30 15:26, Dave Rodgman wrote:
> From: Matt Sealey
>
> Enable faster 8-byte copies on arm64.
>
> Link: http://lkml.kernel.org/r/20181127161913.23863-6-dave.rodg...@arm.com
> Signed-off-by: Matt Sealey
> Signed-off-by: Dave Rodgman
> Cc: David S.
On Fri, 2018-11-30 at 08:00 +, Jürg Billeter wrote:
> This patch adds a new prctl to kill all descendant processes on exit.
> See commit message for details of the prctl.
>
> This is a replacement of PR_SET_PDEATHSIG_PROC I proposed last year [1].
> In the following discussion, Oleg suggested
On Thu, 6 Dec 2018 15:49:32 +
Will Deacon wrote:
> On Wed, Dec 05, 2018 at 06:47:54PM -0500, Steven Rostedt wrote:
> > From: "Steven Rostedt (VMware)"
> >
> > Functions in the set_graph_notrace no longer subtract FTRACE_NOTRACE_DEPTH
> > from curr_ret_stack, as that is now implemented via t
*NOT* acked by Markus Oberhumer, original author of the LZO data compression
library and author of the current Linux kernel LZO implementation.
Please see my email reply to the patch series header for more info.
On 2018-11-30 15:26, Dave Rodgman wrote:
> From: Matt Sealey
>
> Most compilers sh
Commit 2a54e3259e2a ("staging: mt7621-mmc: Remove #if 0 blocks in sd.c")
does not completely remove an #if 0 block in sd.c. This causes the function
msdc_select_clksrc() which was eariler not compiled, to be compiled.
That causes an error - MSDC_CLKSRC_REG is not defined.
This patch completely rem
*NOT* acked by Markus Oberhumer, original author of the LZO data compression
library and author of the current Linux kernel LZO implementation.
Please see my email reply to the patch series header for more info.
On 2018-11-30 15:26, Dave Rodgman wrote:
> When using zram, we frequently encounter
On Thu, 6 Dec 2018 13:20:07 +
Will Deacon wrote:
> On Wed, Dec 05, 2018 at 12:48:54PM -0500, Steven Rostedt wrote:
> > From: "Steven Rostedt (VMware)"
> >
> > It has been reported that ftrace_replace_code() which is called by
> > ftrace_modify_all_code() can cause a soft lockup warning for
This fixes two issues in dcache_by_line_op: patch #4 fixes the logic
that is applied when patching DC CVAP instructions, and patch #5 gets
rid of some unintended undefined symbols resulting from incorrect use
of conditional GAS directives.
Patches #1 to #3 are groundwork for #4.
Cc: Robin Murphy
In preparation of permitting callback type alternatives patching
routines to use any number of alternative instructions, move the
relative reference to the callback routine out of the primary
'struct alt_instr' data structure, where we are currently overloading
the 'alt_offset' member depending on
Permit callback type alternatives to carry a sequence of alternative
instructions, and leave it up to the callback handler to decide how
to use them.
Signed-off-by: Ard Biesheuvel
---
arch/arm64/include/asm/alternative.h | 13 -
1 file changed, 12 insertions(+), 1 deletion(-)
diff -
Use the enhanced alternative_cb implementation to reimplement the code
patching logic for DC CVAP instructions so that we don't fall back to
DV CVAC instructions on systems that require those to be upgraded to
DC CIVAC to work around silicon errata. At the same time, we don't want
to use DV CIVAC n
The GAS directives that are currently being used in dcache_by_line_op
rely on assembler behavior that is not documented, and probably not
guaranteed to produce the correct behavior going forward.
Currently, we end up with some undefined symbols in cache.o:
$ nm arch/arm64/mm/cache.o
...
Callback handlers for alternative patching will shortly be able to
access a set of alternative instructions provided at assembly time.
So update the callback handler prototypes so we can pass this number.
Signed-off-by: Ard Biesheuvel
---
arch/arm64/include/asm/alternative.h | 4 ++--
arch/arm6
On Mon, Dec 03, 2018 at 10:30:53AM +0100, KarimAllah Ahmed wrote:
> Guest memory can either be directly managed by the kernel (i.e. have a "struct
> page") or they can simply live outside kernel control (i.e. do not have a
> "struct page"). KVM mostly support these two modes, except in a few places
On 2018-12-06 2:10 a.m., Baruch Siach wrote:
> Hi Andrey,
>
> Adding Robert Hancock who reported[1] on a PCIe MSI issue with i.MX6.
>
> Andrey Smirnov writes:
>
>> Building a kernel with CONFIG_PCI_IMX6=y, but CONFIG_PCIEPORTBUS=n
>> produces a system where built-in PCIE bridge (16c3:abcd) isn't
It seems that we somehow missed this patch. Cc'ing a few more people
that touched hugetlbpage.c.
Catalin
On Tue, Oct 23, 2018 at 06:36:57AM +0530, Allen Pais wrote:
> Add hstate for each supported hugepage size using arch initcall.
>
> * no hugepage parameters
>
> Without hugepage parameters,
On Thu, Dec 06, 2018 at 10:59:14AM -0500, Steven Rostedt wrote:
> On Thu, 6 Dec 2018 13:20:07 +
> Will Deacon wrote:
>
> > On Wed, Dec 05, 2018 at 12:48:54PM -0500, Steven Rostedt wrote:
> > > From: "Steven Rostedt (VMware)"
> > >
> > > It has been reported that ftrace_replace_code() which
unreferenced object 0x808ec6dc5a80 (size 128):
comm "swapper/0", pid 1, jiffies 4294938063 (age 2560.530s)
hex dump (first 32 bytes):
ff ff ff ff 00 00 00 00 6b 6b 6b 6b 6b 6b 6b 6b
6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b
backtrace:
On 11/27/2018 8:19 PM, Omar Sandoval wrote:
> On Tue, Nov 27, 2018 at 10:16:56AM -0500, Steven Sistare wrote:
>> On 11/9/2018 7:50 AM, Steve Sistare wrote:
>>> From: Steve Sistare
>>>
>>> Provide struct sparsemask and functions to manipulate it. A sparsemask is
>>> a sparse bitmap. It reduces ca
On 2018-12-06 9:50 a.m., Lucas Stach wrote:
> Am Donnerstag, den 06.12.2018, 09:45 -0600 schrieb Robert Hancock:
>> On 2018-12-06 2:10 a.m., Baruch Siach wrote:
>>> Hi Andrey,
>>>
>>> Adding Robert Hancock who reported[1] on a PCIe MSI issue with i.MX6.
>>>
>>> Andrey Smirnov writes:
>>>
Build
On Thu, Dec 06, 2018 at 03:41:16PM +0100, Michel Dänzer wrote:
> On 2018-12-06 1:23 p.m., Joe Perches wrote:
> > On Thu, 2018-12-06 at 12:52 +0100, Michel Dänzer wrote:
> >> In contrast to the 2b case, the pr_debug output isn't visible by default
> >> with 1b, so the latter doesn't fit "always prod
On 12/6/18 10:51 AM, Robin Murphy wrote:
>> Here is the prototype:
>>
>> void dma_pool_free(struct dma_pool *pool, void *vaddr, dma_addr_t dma);
>>
>> With the old code, the 'dma' value had to be correct for use with
>> pool_find_page(), or else you would get an error. If the 'vaddr' value
>> was
* Mark Rutland wrote:
> Andrew and Ingo report that the check-atomics.sh script is simply too
> slow to run for every kernel build, and it's impractical to make it
> faster without rewriting it in something other than shell.
>
> Rather than committing the generated headers, let's regenerate th
On Thu, Dec 6, 2018 at 3:07 AM Guo Ren wrote:
>
> The broken macros make the glibc compile error. If there is no
> __NR3264_fstat*, we should also removed related definitions.
>
> Signed-off-by: Guo Ren
> Signed-off-by: Mao Han
> Cc: Arnd Bergmann
> ---
Thanks for the reminder!
Marcin had alr
On 06/12/2018 15:05, Greg Kroah-Hartman wrote:
On Thu, Dec 06, 2018 at 09:43:46AM +, Bryan O'Donoghue wrote:
On 05/12/2018 21:00, Sicilia Cristian wrote:
It doesn't change the result string
So why do it then ?
Because it is easier to read this way and odds are checkpatch is
happier.
F
* Will Deacon wrote:
> [+ Ingo and Mark]
>
> On Tue, Dec 04, 2018 at 10:47:13PM +0100, Anders Roxell wrote:
> > Some distibutions and build systems doesn't include 'fold' from
> > coreutils default.
> >
> > .../scripts/atomic/atomic-tbl.sh: line 183: fold: command not found
> >
> > Rework to
On Thu, Dec 06, 2018 at 03:37:55PM +, Vokáč Michal wrote:
> On 6.12.2018 14:59, Uwe Kleine-König wrote:
> > On Thu, Dec 06, 2018 at 01:41:31PM +, Vokáč Michal wrote:
> >> +{
> >> + imx_chip->pinctrl = devm_pinctrl_get(&pdev->dev);
> >> + if (IS_ERR(imx_chip->pinctrl)) {
> >> + de
On Thu, Dec 6, 2018 at 7:02 AM Eric W. Biederman wrote:
>
> Christian Brauner writes:
>
> > The kill() syscall operates on process identifiers (pid). After a process
> > has exited its pid can be reused by another process. If a caller sends a
> > signal to a reused pid it will end up signaling th
On Thu, Dec 6, 2018 at 9:05 PM Maxime Ripard wrote:
>
> On Thu, Dec 06, 2018 at 06:53:06PM +0530, Jagan Teki wrote:
> > Some camera modules have the SoC feeding a master clock to the sensor
> > instead of having a standalone crystal. This clock signal is generated
> > from the clock control unit a
Markus,
> Request 2 - add COPY16; *NOT* acked by me
>
> [PATCH 2/8] lib/lzo: clean-up by introducing COPY16
>
> is still not correct because of possible overlapping copies. I'll
> address this on the weekend.
Can you give a syndrome as to why
{
COPY8(op, ip);
COPY8(op+8,ip+8)
On Thu, Dec 06, 2018 at 04:14:53PM +, Bryan O'Donoghue wrote:
> On 06/12/2018 15:05, Greg Kroah-Hartman wrote:
> > On Thu, Dec 06, 2018 at 09:43:46AM +, Bryan O'Donoghue wrote:
> > > On 05/12/2018 21:00, Sicilia Cristian wrote:
> > > > It doesn't change the result string
> > >
> > > So why
On 06/12/2018 16:23, Greg Kroah-Hartman wrote:
On Thu, Dec 06, 2018 at 04:14:53PM +, Bryan O'Donoghue wrote:
On 06/12/2018 15:05, Greg Kroah-Hartman wrote:
On Thu, Dec 06, 2018 at 09:43:46AM +, Bryan O'Donoghue wrote:
On 05/12/2018 21:00, Sicilia Cristian wrote:
It doesn't change the
* Sean Christopherson wrote:
> On Thu, Dec 06, 2018 at 08:34:09AM +0100, Ingo Molnar wrote:
> > I like your '!' idea, but with a further simplification: how about using
> > '-/+' differentiation and a single character and a fixed-length message.
> >
> > The new output will be lines of:
> >
>
* Borislav Petkov wrote:
> On Wed, Dec 05, 2018 at 07:01:58PM +0100, Ingo Molnar wrote:
> > Oh - I thought we'd have arch/x86/mce/ or so?
> >
> > There's machine check events that are not tied to any particular CPU,
> > correct? So this would be the right conceptual level - and it would also
* Nadav Amit wrote:
> > On Dec 4, 2018, at 5:34 PM, Nadav Amit wrote:
> >
> > A following patch is going to make module allocated memory
> > non-executable. This requires to modify ftrace and make the memory
> > executable again after it is configured.
> >
> > In addition, this patch makes f
* Tony Battersby [181206 16:13]:
> On 12/6/18 10:51 AM, Robin Murphy wrote:
> >> Here is the prototype:
> >>
> >> void dma_pool_free(struct dma_pool *pool, void *vaddr, dma_addr_t dma);
> >>
> >> With the old code, the 'dma' value had to be correct for use with
> >> pool_find_page(), or else you w
On Thu, Dec 6, 2018 at 6:51 AM Greg KH wrote:
>
> On Wed, Dec 05, 2018 at 03:19:24PM -0800, Todd Kjos wrote:
> > Add __acquire()/__release() annnotations to fix warnings
> > in sparse context checking
> >
> > There is one case where the warning was due to a lack of
> > a "default:" case in a switc
On Tue, Oct 23, 2018 at 06:36:57AM +0530, Allen Pais wrote:
> Add hstate for each supported hugepage size using arch initcall.
>
> * no hugepage parameters
>
> Without hugepage parameters, only a default hugepage size is
> available for dynamic allocation. It's different, for example, from
>
> On Dec 6, 2018, at 7:53 AM, Sean Christopherson
> wrote:
>
>> On Thu, Dec 06, 2018 at 08:34:09AM +0100, Ingo Molnar wrote:
>> I like your '!' idea, but with a further simplification: how about using
>> '-/+' differentiation and a single character and a fixed-length message.
>>
>> The new
On 12/3/2018 11:56 AM, Valentin Schneider wrote:
> Hi Steve,
> On 26/11/2018 19:06, Steven Sistare wrote:
>> [...]
>>> Mmm I was thinking we could abuse the wrap() and start at
>>> (fls(prev_span) + 1), but we're not guaranteed to have contiguous spans -
>>> the Arm Juno for instance has [0, 3, 4],
Commit-ID: a50480cb6d61d5c5fc13308479407b628b6bc1c5
Gitweb: https://git.kernel.org/tip/a50480cb6d61d5c5fc13308479407b628b6bc1c5
Author: Andrea Righi
AuthorDate: Thu, 6 Dec 2018 10:56:48 +0100
Committer: Ingo Molnar
CommitDate: Thu, 6 Dec 2018 16:52:03 +0100
kprobes/x86: Blacklist non-a
* Andy Lutomirski wrote:
> > vs. (with SGX added as 'G' for testing purposes)
> >
> > [0.158849] #PF error code(0001): +P !W !U !S !I !K !G
> > [0.159292] #PF error code(0003): +P +W !U !S !I !K !G
> > [0.159742] #PF error code(0007): +P +W +U !S !I !K !G
> > [0.160190] #PF
On Thu, Dec 6, 2018 at 7:02 AM David Abdurachmanov
wrote:
>
> The patch adds support for SECCOMP and SECCOMP_FILTER (BPF).
>
> Signed-off-by: David Abdurachmanov
> ---
> arch/riscv/Kconfig | 14 ++
> arch/riscv/include/asm/thread_info.h | 5 -
> arch/riscv/kern
For x86 PMUs that do not support context exclusion let's advertise the
PERF_PMU_CAP_NO_EXCLUDE capability. This ensures that perf will
prevent us from handling events where any exclusion flags are set.
Let's also remove the now unnecessary check for exclusion flags.
This change means that amd/iomm
On Thu, Dec 6, 2018 at 7:02 AM David Abdurachmanov
wrote:
>
> Testing with libseccomp master branch revealed that testcases with
> filters on syscall arguments were failing due to wrong values. Seccomp
> uses syscall_get_argumentsi() to copy syscall arguments, and there is a
> bug in pointer arith
Hi,
we have received a Mac 18,1 (A1418), from a customer, on which we are
unable to get any screen since seemingly 4.17.x (tested with 4.17.16).
4.16.16 works fine. Tried several 4.17, 4.18 and 4.19 releases (latest
4.19.4), none of these show any output on the screen after the bootloader.
On Thu, Dec 6, 2018 at 7:02 AM David Abdurachmanov
wrote:
> The patch adds support for SECCOMP and SECCOMP_FILTER (BPF).
Can you add support to tools/testing/selftests/seccomp/seccomp_bpf.c
as well? That selftest finds a lot of weird corner-cases...
> diff --git a/arch/riscv/include/asm/thread_i
As suggested by Paolo, introduce new KVM_GET_SUPPORTED_HV_CPUID returning
all Hyper-V CPUID feature leaves, this way we won't need to add a new
KVM_CAP_HYPERV_* for every new Hyper-V enlightenment we implement in
KVM.
(Using the existing KVM_GET_SUPPORTED_CPUID doesn't seem to be possible:
Hyper-V
The newly introduced KVM_GET_SUPPORTED_HV_CPUID covers Direct Mode stimers
feature so we can drop KVM_CAP_HYPERV_STIMER_DIRECT and reuse its number.
Signed-off-by: Vitaly Kuznetsov
---
- This patch only makes sense befor 4.21 merge window, disregard if it
doesn't make it in time.
---
arch/x86/k
hyperv-tlfs.h is a bit messy: CPUID feature bits are not always sorted,
it's hard to get which CPUID they belong to, some items are duplicated
(e.g. HV_X64_MSR_CRASH_CTL_NOTIFY/HV_CRASH_CTL_CRASH_NOTIFY).
Do some housekeeping work. While on it, replace all (1 << X) with BIT(X)
macro.
Signed-off-b
The upcoming KVM_GET_SUPPORTED_HV_CPUID ioctl will need to return
Enlightened VMCS version in HYPERV_CPUID_NESTED_FEATURES.EAX when
it was enabled.
Signed-off-by: Vitaly Kuznetsov
---
arch/x86/include/asm/kvm_host.h | 1 +
arch/x86/kvm/svm.c | 7 +++
arch/x86/kvm/vmx.c
Quoting jgli...@redhat.com (2018-12-06 15:47:04)
> From: Jérôme Glisse
>
> The debugfs take reference on fence without dropping them. Also the
> rcu section are not well balance. Fix all that ...
Wouldn't the code be a lot simpler (and a consistent snapshot) if it used
reservation_object_get_fen
Add a simple (and stupid) hyperv_cpuid test: check that we got the
expected number of entries with and without Enlightened VMCS enabled
and that all currently reserved fields are zeroed.
Signed-off-by: Vitaly Kuznetsov
---
tools/testing/selftests/kvm/Makefile | 1 +
.../selftests/kvm/
With every new Hyper-V Enlightenment we implement we're forced to add a
KVM_CAP_HYPERV_* capability. While this approach works it is fairly
inconvenient: the majority of the enlightenments we do have corresponding
CPUID feature bit(s) and userspace has to know this anyways to be able to
expose the
BIT(13) in HYPERV_CPUID_FEATURES.EBX is described as "ConfigureProfiler" in
TLFS v4.0 but starting 5.0 it is replaced with 'Reserved'. As we don't
currently us it in kernel it can just be dropped.
Signed-off-by: Vitaly Kuznetsov
---
arch/x86/include/asm/hyperv-tlfs.h | 1 -
1 file changed, 1 del
Em Wed, Dec 05, 2018 at 11:21:40AM +0100, Jiri Olsa escreveu:
> On Mon, Nov 19, 2018 at 09:06:35PM -0800, Andi Kleen wrote:
> > From: Andi Kleen
> >
> > Fix incorrect event names for the Load_Miss_Real_Latency metric for
> > Skylake and Skylake Server.
> >
> > Fixes https://github.com/andikleen/
On Tue 20 Nov 13:08 PST 2018, Sibi Sankar wrote:
> Add power-domain bindings for Q6V5 MSS on SDM845 SoCs.
>
Thanks Sibi,
> Signed-off-by: Sibi Sankar
> ---
>
> Add dt-binding corresponding to https://patchwork.kernel.org/patch/10586893/
> (remoteproc: q6v5: Add support to vote for rpmh power
Em Mon, Nov 19, 2018 at 09:06:17PM -0800, Andi Kleen escreveu:
> From: Andi Kleen
>
> This is a fix for another instance of the skid problem Milian
> recently found [1]
Milian, have you tested this?
Adrian, can I have your Reviewed-by or Acked-by?
Thanks,
- Arnaldo
> The LBRs don't freeze a
W dniu 06.12.2018 o 17:14, Arnd Bergmann pisze:
> On Thu, Dec 6, 2018 at 3:07 AM Guo Ren wrote:
>>
>> The broken macros make the glibc compile error. If there is no
>> __NR3264_fstat*, we should also removed related definitions.
>>
>> Signed-off-by: Guo Ren
>> Signed-off-by: Mao Han
>> Cc: Arnd
> On Dec 6, 2018, at 8:47 AM, Ingo Molnar wrote:
>
>
> * Andy Lutomirski wrote:
>
>>> vs. (with SGX added as 'G' for testing purposes)
>>>
>>> [0.158849] #PF error code(0001): +P !W !U !S !I !K !G
>>> [0.159292] #PF error code(0003): +P +W !U !S !I !K !G
>>> [0.159742] #PF er
Em Wed, Dec 05, 2018 at 08:19:41PM +0300, Alexey Budankov escreveu:
>
> Sending a part which was missed between v12 and v13 of the patch set
> introducing AIO trace streaming for perf record mode.
>
> The part is essential to avoid memory leakage during deallocation
> of AIO related trace data b
From: Colin Ian King
Currently the node name is being formatting into a temporary string
node_name, however, kobject_init_and_add allows one to format up
a node name, so use that instead. This removes the need for the
node_name string and also cleans up the following warning:
Fixes clang warning
On Thu, Dec 6, 2018 at 7:02 AM David Abdurachmanov
wrote:
> The patch adds support for SECCOMP and SECCOMP_FILTER (BPF).
I built this against linux-next but it's missing seccomp.h. Was that
accidentally left out of the commit?
CC arch/riscv/kernel/asm-offsets.s
In file included from ./in
Hi Maxime
On Thu, Dec 6, 2018 at 4:34 PM Maxime Ripard wrote:
>
> On Thu, Dec 06, 2018 at 06:53:05PM +0530, Jagan Teki wrote:
> > Allwinner A64 CSI controller has similar features as like in
> > H3, So add support for A64 via H3 fallback.
> >
> > Also updated CSI_SCLK to use 300MHz via assigned-c
On Sun, Nov 18, 2018 at 08:23:42PM -0800, Andrei Vagin wrote:
> On Fri, Sep 21, 2018 at 05:33:01PM +0100, David Howells wrote:
> > @@ -1993,57 +2009,53 @@ int cgroup_setup_root(struct cgroup_root *root, u16
> > ss_mask, int ref_flags)
> > return ret;
> > }
> >
> > -struct dentry *cgroup_do_
Em Sun, Dec 02, 2018 at 12:46:03AM +0900, Sihyeon Jang escreveu:
> According to definition of snprintf, it gets size factor including null('\0')
> byte.
> So '-1' is not neccessary. Also it will be helpful unfied style with other
> cases. (eg. builtin-script.c)
Thanks, applied.
- Arnaldo
> Cc
On Thu, Dec 6, 2018 at 5:47 PM Kees Cook wrote:
>
> On Thu, Dec 6, 2018 at 7:02 AM David Abdurachmanov
> wrote:
> >
> > The patch adds support for SECCOMP and SECCOMP_FILTER (BPF).
> >
> > Signed-off-by: David Abdurachmanov
> > ---
> > arch/riscv/Kconfig | 14 ++
>
On Thu, Dec 6, 2018 at 5:52 PM Kees Cook wrote:
>
> On Thu, Dec 6, 2018 at 7:02 AM David Abdurachmanov
> wrote:
> > The patch adds support for SECCOMP and SECCOMP_FILTER (BPF).
>
> Can you add support to tools/testing/selftests/seccomp/seccomp_bpf.c
> as well? That selftest finds a lot of weird c
On Thu, Dec 6, 2018 at 5:49 PM Kees Cook wrote:
>
> On Thu, Dec 6, 2018 at 7:02 AM David Abdurachmanov
> wrote:
> >
> > Testing with libseccomp master branch revealed that testcases with
> > filters on syscall arguments were failing due to wrong values. Seccomp
> > uses syscall_get_argumentsi() t
On December 7, 2018 4:01:19 AM GMT+13:00, ebied...@xmission.com wrote:
>Christian Brauner writes:
>
>> The kill() syscall operates on process identifiers (pid). After a
>process
>> has exited its pid can be reused by another process. If a caller
>sends a
>> signal to a reused pid it will end up si
On Thu, Dec 6, 2018 at 6:07 PM Kees Cook wrote:
>
> On Thu, Dec 6, 2018 at 7:02 AM David Abdurachmanov
> wrote:
> > The patch adds support for SECCOMP and SECCOMP_FILTER (BPF).
>
> I built this against linux-next but it's missing seccomp.h. Was that
> accidentally left out of the commit?
>
>
>
Clock drivers for Armada AP and Armada CP use the same function to
generate unique clock name. A third drivers is coming with the same
need, so it's time to move this function in a common file.
Signed-off-by: Gregory CLEMENT
---
drivers/clk/mvebu/Kconfig | 5
drivers/clk/
The CPU frequency is managed at the AP level for the Armada 7K/8K. The
CPU frequency is modified by cluster: the CPUs of the same cluster have
the same frequency.
This patch adds the clock driver that will be used by CPUFreq, it is
based on the work of Omri Itach .
Signed-off-by: Gregory CLEMENT
This commit makes sure the driver for the Armada 7K/8K CPU clock is
enabled.
Signed-off-by: Gregory CLEMENT
---
arch/arm64/Kconfig.platforms | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index 51bc479334a4..8a05870b1ba8 100644
---
Actually, the clocks exposed for the cluster are not the CPU clocks, but
the PLL clock used as entry clock for the CPU clocks. The CPU clock will
be managed by a driver submitting in the following patches.
Signed-off-by: Gregory CLEMENT
---
drivers/clk/mvebu/ap806-system-controller.c | 4 ++--
1
Add cpu clock node on AP
Signed-off-by: Gregory CLEMENT
---
arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi | 4
arch/arm64/boot/dts/marvell/armada-ap806.dtsi | 6 ++
2 files changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi
b/arch/arm64
On Fri, 30 Nov 2018 09:22:17 -0500
"Michael S. Tsirkin" wrote:
> Fix an extra space that sneaked in with commit 09c205afd "(x86, boot:
> Define the 2.12 bzImage boot protocol").
>
> Signed-off-by: Michael S. Tsirkin
Applied, thanks.
jon
Hello,
This is the second version of a series allowing to manage the cpu
clock for Armada 7K/8K. For these SoCs, the CPUs share the same clock
by cluster, so actually the clock management is done at cluster level.
As for the other Armada 7K/8K clocks it is possible to have multiple
AP so here aga
Daniel Colascione writes:
> On Thu, Dec 6, 2018 at 7:02 AM Eric W. Biederman
> wrote:
>>
>> Christian Brauner writes:
>>
>> > The kill() syscall operates on process identifiers (pid). After a process
>> > has exited its pid can be reused by another process. If a caller sends a
>> > signal to a
Hi Steve,
On 06/12/2018 16:40, Steven Sistare wrote:
> [...]
>>
>> Ah yes, that would work. Thing is, I had excluded having the misfit masks
>> being in the sd_llc_shareds, since from a logical standpoint they don't
>> really belong there.
>>
>> With asymmetric CPU capacities we kind of disregard
> On Dec 6, 2018, at 1:57 AM, Peter Zijlstra wrote:
>
> On Tue, Dec 04, 2018 at 05:34:07PM -0800, Nadav Amit wrote:
>
>> So let's remove it. Andy suggested that the changes of the PTEs can be
>> avoided (excluding the direct-mapping alias), which is true. However,
>> in x86 it requires some clea
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