On Fri, Oct 19, 2018 at 10:32:24AM +1100, Benjamin Herrenschmidt wrote:
> On Thu, 2018-10-18 at 15:25 +0530, Vinod wrote:
> >
> > > It's not a dmaengine driver. It's a serial UART driver that happens to
> > > use a dedicated DMA engine.
> >
> > Then I see no reason for it to use dmaengine APIs. T
Hi Frank,
On Fri, Oct 19, 2018 at 2:06 AM Frank Rowand wrote:
> On 10/18/18 12:32, Rob Herring wrote:
> > On Tue, Oct 16, 2018 at 05:34:26PM -0700, frowand.l...@gmail.com wrote:
> >> Provide a sysfs file, /sys/firmware/devicetree/tree_version, to allow
> >> user space to determine if the live de
On 10/18/2018 06:26 AM, Andrew Morton wrote:
On Wed, 17 Oct 2018 09:36:00 +0800 kernel test robot
wrote:
FYI, we noticed the following commit (built with gcc-6):
commit: 6558038e4540a22ee4f99a5def74791189102bc0 ("mm/memory.c: recheck page table
entry with page table lock held")
https://g
On Thu, Oct 18, 2018 at 04:33:23PM -0700, David Miller wrote:
>
> The main bit here is fixing how fallback system calls are handled in
> the sparc vDSO.
>
> Unfortunately, I fat fingered the commit and some perf debugging hacks
> slipped into the vDSO fix, which I revert in the very next commit.
Hi all,
News: I will not be doing linux-next releases next week. Unfortunately
this will probably be the first week of the merge window. :-(
Changes since 20181018:
The net-next tree gained a conflict against the net tree and a build
failure due to an interaction with the rdma tree for which I
On Fri, 31 Aug 2018 21:53:11 +0300
Numan Demirdöğen wrote:
>If I put laptop to suspend or hibernate by closing lid, power
>manager or any other method and then I resume/wake up laptop, keyboard
>is not responding. My laptop is a Sony Vaio VPCEH2F1E.
>
>Steps to produce bug:
>1. Boot
>2. Put lapt
On 2018/10/19 3:33, Boris Brezillon wrote:
On Thu, 18 Oct 2018 13:09:05 +0800
Jianxin Pan wrote:
From: Liang Yang
Add initial support for the Amlogic NAND flash controller which found
in the Meson-GXBB/GXL/AXG SoCs.
Signed-off-by: Liang Yang
Signed-off-by: Yixun Lan
Signed-off-by: Jian
On 2018/10/18 22:24, Boris Brezillon wrote:
On Thu, 18 Oct 2018 13:09:05 +0800
Jianxin Pan wrote:
+static int meson_nfc_exec_op(struct nand_chip *chip,
+const struct nand_operation *op, bool check_only)
+{
+ struct mtd_info *mtd = nand_to_mtd(chip);
+
On Fri, 2018-10-19 at 10:14 +0530, Nayna Jain wrote:
>
> On 10/17/2018 10:02 PM, Tomas Winkler wrote:
> > diff --git a/drivers/char/tpm/tpm_i2c_nuvoton.c
> > b/drivers/char/tpm/tpm_i2c_nuvoton.c
> > index caa86b19c76d..f74f451baf6a 100644
> > --- a/drivers/char/tpm/tpm_i2c_nuvoton.c
> > +++ b/dri
On Thu, 18 Oct 2018 at 11:57, Marek Szyprowski wrote:
>
> Move interrupts allocation from exynos4_timer_resources() into separate
> function together with the interrupt number parsing code from
> mct_init_dt(), so the code for managing interrupts is kept together.
> While touching exynos4_timer_re
On Thu, 18 Oct 2018 at 11:57, Marek Szyprowski wrote:
>
> To get ARM Architected Timers working on Samsung Exynos SoCs, one has to
> first configure and enable Exynos Multi-Core Timer, because they both
> share some common hardware blocks (global system counter). This patch
> adds a mode of cooper
On 18/10/2018 22:46, Andy Lutomirski wrote:
>> [0] drivers/usb/gadget/function/f_fs.c::ffs_user_copy_worker()
>>
>> Sebastian
> I think we need an entirely new API:
>
> user_mm_ctx_t ctx = user_mm_ctx_get();
>
> ...
>
> use_user_mm_ctx(ctx);
> unuse_user_mm_ctx(ctx);
>
> ...
>
> user_mm_ctx_pu
The ad7124-4 and ad7124-8 are a family of 4 and 8 channel sigma-delta ADCs
with 24-bit precision and reference.
Three power modes are available which in turn affect the output data rate:
* Full power: 9.38 SPS to 19,200 SPS
* Mid power: 2.34 SPS to 4800 SPS
* Low power: 1.17 SPS to 2400 SPS
Th
From: Lars-Peter Clausen
Some newer devices from the Sigma-Delta ADC family do have their data
register at a different address than the current default address. Add a
parameter to the ad_sigma_delta_info struct which allows to override the
default address.
Signed-off-by: Lars-Peter Clausen
Sign
Add support for Analog Devices AD7124 4-channels and 8-channels ADC.
Signed-off-by: Stefan Popa
---
Changes in v2:
- Nothing changed.
.../devicetree/bindings/iio/adc/adi,ad7124.txt | 96 ++
MAINTAINERS| 1 +
2 files change
On Wed, Oct 17, 2018 at 10:59:33AM -0700, Tim Chen wrote:
> diff --git a/kernel/cpu.c b/kernel/cpu.c
> index 3adecda..ad28afc 100644
> --- a/kernel/cpu.c
> +++ b/kernel/cpu.c
> @@ -349,6 +349,8 @@ EXPORT_SYMBOL_GPL(cpu_hotplug_enable);
> #ifdef CONFIG_HOTPLUG_SMT
> enum cpuhp_smt_control cpu_smt_
On Wed, Oct 17, 2018 at 10:59:28AM -0700, Tim Chen wrote:
> Application to application exploit is in general difficult due to address
> space layout randomization in applications and the need to know an
Does the BTB attack on KASLR not work for userspace?
* Thara Gopinath wrote:
> > Yeah, so I'd definitely suggest to not integrate this averaging into
> > pelt.c in the fashion presented, because:
> >
> > - This couples your thermal throttling averaging to the PELT decay
> >half-time AFAICS, which would break the other user every time the
>
Just Ping.
This is a very serious issue. The OS boot from this raid controller
couldn't find bock devices after installing OS.
I think this patch should be merged asap.
Feng Li 于2018年10月12日周五 上午11:13写道：
>
> I use 'HPE Smart Array E208i-a SR Gen10 Controller', and pass through
> the SAS controlle
On 2018/10/19 4:39, Boris Brezillon wrote:
On Thu, 18 Oct 2018 13:09:05 +0800
Jianxin Pan wrote:
+static int meson_nfc_calc_set_timing(struct meson_nfc *nfc,
+const struct nand_sdr_timings *timings)
+{
+ struct nand_timing *timing = &nfc->timing;
+
On Thu 18-10-18 19:11:47, Andrew Morton wrote:
> On Wed, 26 Sep 2018 16:22:27 +0200 Michal Hocko wrote:
>
> > > MPOL_PREFERRED is handled by policy_node() before we call
> > > __alloc_pages_nodemask.
> > > __GFP_THISNODE is applied only when we are not using
> > > __GFP_DIRECT_RECLAIM which is h
I planed to get to review this earlier but been busy. Anyway, this patch
should be applied only after movability one to prevent from
(theoretical) bisectability issues.
I would probably fold it into the one which defines arch specific hook.
On Fri 12-10-18 09:29:55, Anshuman Khandual wrote:
> Arc
On Fri, Oct 19, 2018 at 11:41:31AM +0900, Masahiro Yamada wrote:
> Adding -Wshadow to KBUILD_HOSTCFLAGS emits another warning in Kconfig.
> Of course, it is easy to fix.
> But, I just started to think this option is a kind of harsh...
What is more, if we added -Wshadow to KBUILD_HOSTCFLAGS, then t
On Fri, 19 Oct 2018 15:29:05 +0800
Liang Yang wrote:
> > How about defining that the HW returns an array of __le64 instead and then
> > define the following macros which you can use after converting in the
> > CPU endianness
> >
> > #define ECC_GET_PROTECTED_OOB_BYTE(x, y)(((x) >> (8 * (1 +
On Wed 17-10-18 17:03:03, John Hubbard wrote:
> On 10/17/18 4:09 AM, Michal Hocko wrote:
> > On Tue 16-10-18 18:48:23, John Hubbard wrote:
> > [...]
> >> It's hard to say exactly what the active/inactive/unevictable list should
> >> be when DMA is done and put_user_page*() is called, because we don
On Thu, Oct 18, 2018 at 06:41:32PM -0700, Nathan Chancellor wrote:
> On Thu, Oct 18, 2018 at 07:54:15PM +0200, Greg Kroah-Hartman wrote:
> > This is the start of the stable review cycle for the 4.14.78 release.
> > There are 41 patches in this series, all will be posted as a response
> > to this on
Which tree it applies?
On Thu, Sep 27, 2018 at 08:03:45PM +0300, Mike Rapoport wrote:
>During removal of HAVE_MEMBLOCK definition, the #else clause of the
>
> #ifdef CONFIG_HAVE_MEMBLOCK
> ...
> #else
> ...
> #endif
>
>conditional was not removed.
>
>R
Since commit 1d5cfdb07628
("tree wide: use kvfree() than conditional kfree()/vfree()")
size in CODA_FREE is no longer used and that macro
hides nothing more than kvfree()
Signed-off-by: Fabian Frederick
---
fs/coda/coda_linux.h | 2 --
fs/coda/psdev.c | 8
fs/coda/upcall.c |
This small patchset applies some sparse clean-up / optimizations
Fabian Frederick (7):
coda: remove CODA_FREE
coda: destroy mutex in put_super()
coda: use SIZE() for stat
coda: add __init to init_coda_psdev()
coda: remove sysctl object from module when unused
coda: remove sb test in co
On Thu, Oct 18, 2018 at 09:29:39PM -0700, Andy Lutomirski wrote:
> > Another example is __BPF_PROG_RUN_ARRAY(), which also uses
> > preempt_enable_no_resched().
>
> Alexei, I think this code is just wrong. Do you know why it uses
> preempt_enable_no_resched()?
Yes, that's a straight up bug.
It
init_coda_psdev() was only called by __init function.
Signed-off-by: Fabian Frederick
---
fs/coda/psdev.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/fs/coda/psdev.c b/fs/coda/psdev.c
index cbdddf4..6d1c95f 100644
--- a/fs/coda/psdev.c
+++ b/fs/coda/psdev.c
@@ -352,7 +352
we can safely destroy vc_mutex at the end of umount process.
Signed-off-by: Fabian Frederick
---
fs/coda/inode.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/fs/coda/inode.c b/fs/coda/inode.c
index dd819c1..69bb64d 100644
--- a/fs/coda/inode.c
+++ b/fs/coda/inode.c
@@ -244,6 +244,7 @@ sta
This patch moves cfi check in coda_ftoc() instead of repeating
it in the wild.
Module size
textdata bss dec hex filename
282971040 700 300377555 fs/coda/coda.ko.before
28263 980 700 2994374f7 fs/coda/coda.ko.after
Signed-off-by: Fabian Frederick
max_t expression was already defined in coda sources
Signed-off-by: Fabian Frederick
---
fs/coda/upcall.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/fs/coda/upcall.c b/fs/coda/upcall.c
index d0d0fed..1323793 100644
--- a/fs/coda/upcall.c
+++ b/fs/coda/upcall.c
@@ -553,7
Inspired by NFS sysctl process
Signed-off-by: Fabian Frederick
---
fs/coda/Makefile | 3 ++-
fs/coda/coda_int.h | 10 ++
fs/coda/coda_linux.h | 4
fs/coda/sysctl.c | 11 ---
4 files changed, 12 insertions(+), 16 deletions(-)
diff --git a/fs/coda/Makefile b/fs/co
coda_fid_to_inode() is only called by coda_downcall() where
sb is already being tested.
Signed-off-by: Fabian Frederick
---
fs/coda/cnode.c | 5 -
1 file changed, 5 deletions(-)
diff --git a/fs/coda/cnode.c b/fs/coda/cnode.c
index 845b5a6..c42d340 100644
--- a/fs/coda/cnode.c
+++ b/fs/coda/
On Thu, Oct 18, 2018 at 10:00:53PM -0700, Alexei Starovoitov wrote:
> >
> > >
> > > Another example is __BPF_PROG_RUN_ARRAY(), which also uses
> > > preempt_enable_no_resched().
> >
> > Alexei, I think this code is just wrong.
>
> why 'just wrong' ?
Because you lost a preemption point, this is
On Thu, Oct 18, 2018 at 10:07:52PM +0800, Sean Wang wrote:
> On Tue, Oct 9, 2018 at 3:16 AM Manivannan Sadhasivam <
> manivannan.sadhasi...@linaro.org> wrote:
>
> > Add pinctrl support for Mediatek MT6797 SoC.
> >
> > Signed-off-by: Manivannan Sadhasivam
> > ---
> > arch/arm64/boot/dts/mediatek/
On Sat, Oct 13, 2018 at 01:04:45PM -0400, Pavel Tatashin wrote:
>This is incorrect: next_present_section_nr() returns "int" and -1 no
>next section, this change would lead to infinite loop.
Yes, the -1 is a very special value.
--
Wei Yang
Help you, Help me
On 2018/10/19 4:50, Boris Brezillon wrote:
On Thu, 18 Oct 2018 13:09:05 +0800
Jianxin Pan wrote:
+static int meson_nfc_buffer_init(struct mtd_info *mtd)
+{
+ struct nand_chip *nand = mtd_to_nand(mtd);
+ struct meson_nfc *nfc = nand_get_controller_data(nand);
+ static int m
jffs2_sync_fs makes the assumption that if CONFIG_JFFS2_FS_WRITEBUFFER
is defined then a write buffer is available and has been initialized.
However, this does is not the case when the mtd device has no
out-of-band buffer:
int jffs2_nand_flash_setup(struct jffs2_sb_info *c)
{
if (!c->mtd->
On 2018/10/19 16:10, Boris Brezillon wrote:
On Fri, 19 Oct 2018 15:29:05 +0800
Liang Yang wrote:
How about defining that the HW returns an array of __le64 instead and then
define the following macros which you can use after converting in the
CPU endianness
#define ECC_GET_PROTECTED_OOB_BYT
Hi Christoph,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm-exynos/exynos-drm-next]
[also build test ERROR on v4.19-rc8 next-20181019]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https
On Fri, Oct 19, 2018 at 01:08:23AM +, Nadav Amit wrote:
> Consider for example do_int3(), and see my inlined comments:
>
> dotraplinkage void notrace do_int3(struct pt_regs *regs, long error_code)
> {
> ...
> ist_enter(regs);// => preempt_disable()
> cond_loca
This patch adds zynqmp nvmem firmware driver to access the
SoC revision information from the hardware register.
Signed-off-by: Nava kishore Manne
---
Changes for v1:
-None
Changes for RFC-V3:
-Changed nvmem_register() to devm_nvmem_register()
and
Hi Leo,
On 10/19/2018 05:56 AM, Leo Yan wrote:
Commit 4d3ebd3658d8 ("coreisght: tmc: Claim device before use") uses
CLAIM tag to validate if the device is available, it needs to pass
the device base address to access related registers.
In the function tmc_etb_disable_hw() it wrongly passes the
This series of patches are created On top of the
below repo
//git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc.git
BRANCH: next/drivers
Nava kishore Manne (3):
firmware: xilinx: Add zynqmp_pm_get_chipid() API
dt-bindings: nvmem: Add bindings for ZynqMP nvmem driver
nvmem: zynqmp: Added z
Add documentation to describe Xilinx ZynqMP nvmem driver
bindings.
Signed-off-by: Nava kishore Manne
---
Changes for v1:
Created a Seperate(New) DT binding file as
suggested by Rob.
Changes for RFC-V3:
-None.
Changes for RFC-V2:
-M
This patch adds a new API to provide access to the
hardware related data like soc revision, IDCODE... etc.
Signed-off-by: Nava kishore Manne
---
Changes for v1:
-None.
Changes for RFC-V3:
-corrected typo error in commit msg.
Changes for RFC-v2:
-N
Add a reset controller driver for Xilinx Zynq UltraScale+ MPSoC.
The zynqmp reset-controller has the ability to reset lines
connected to different blocks and peripheral in the Soc.
Signed-off-by: Nava kishore Manne
---
Changes for v1:
-None.
Changes for RFC-V3:
-N
This Patch Adds reset API's to support release, assert
and status functionalities by using firmware interface.
Signed-off-by: Nava kishore Manne
---
Changes for v1:
-None.
Changes for RFC-V3:
-None.
Changes for RFC-V2:
-New Patch.
drivers/firmwa
On Fri, 19 Oct 2018 16:29:40 +0800
Liang Yang wrote:
> On 2018/10/19 4:50, Boris Brezillon wrote:
> > On Thu, 18 Oct 2018 13:09:05 +0800
> > Jianxin Pan wrote:
> >
> >> +static int meson_nfc_buffer_init(struct mtd_info *mtd)
> >> +{
> >> + struct nand_chip *nand = mtd_to_nand(mtd);
> >> + s
Add documentation to describe Xilinx ZynqMP reset driver
bindings.
Signed-off-by: Nava kishore Manne
---
Changes for v1:
-Created a Seperate(New) DT binding file as
suggested by Rob.
Changes for RFC-V3:
-Corrected Commit Msg.
Changes for RFC-V2:
This series of patches are created On top of the
below repo.
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc.git (fetch)
BRANCH: next/drivers
Nava kishore Manne (3):
firmware: xilinx: Add reset API's
dt-bindings: reset: Add bindings for ZynqMP reset driver
reset: reset-zynqmp: Ad
On 13/10/2018 09:20, Chaotian Jing wrote:
> for MSDC IP which supports both data tune and async fifo, it can
> tune cmd/data together. which can save the time and make the tune
> result of CMD more stable as data line are 4bit or 8bit.
>
> Signed-off-by: Chaotian Jing
> ---
> drivers/mmc/host
This series of patches are created On top of the
below repo.
//git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc.git
BRANCH: next/drivers.
Nava kishore Manne (3):
firmware: xilinx: Add fpga API's
dt-bindings: fpga: Add bindings for ZynqMP fpga driver
fpga manager: Adding FPGA Manager sup
This patch adds FPGA Manager support for the Xilinx
ZynqMp chip.
Signed-off-by: Nava kishore Manne
---
Changes for v1:
-None.
Changes for RFC-V2:
-Updated the Fpga Mgr registrations call's
to 4.18
drivers/fpga/Kconfig | 9 +++
drivers/fp
This Patch Adds fpga API's to support the Bitstream loading
by using firmware interface.
Signed-off-by: Nava kishore Manne
---
Changes for v1:
-None.
Changes for RFC-V2:
-New Patch.
drivers/firmware/xilinx/zynqmp.c | 46
include/
Add documentation to describe Xilinx ZynqMP fpga driver
bindings.
Signed-off-by: Nava kishore Manne
---
Changes for v1:
Created a Seperate(New) DT binding file as
suggested by Rob.
Changes for RFC-V2:
-Moved pcap node as a child to firwmare
On 13/10/2018 09:20, Chaotian Jing wrote:
> the tuning code is becoming more and more bloated, let's make the
> set cmd/data delay to inline function to avoid too much redundant code.
>
> Signed-off-by: Chaotian Jing
> ---
> drivers/mmc/host/mtk-sd.c | 133
> +
On Fri, Oct 19, 2018 at 01:57:03PM +0800, Aaron Lu wrote:
> >
> > I don't think this is the right way of thinking about it because it's
> > possible to have the system split in such a way so that the migration
> > scanner only encounters unmovable pages before it meets the free scanner
> > where u
irq_create_mapping calls irq_find_mapping internally and will use the
found mapping if one exists, so there is no need to manually call this
from i2c_smbus_host_notify_to_irq.
Signed-off-by: Charles Keepax
---
drivers/i2c/i2c-core-base.c | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
The IRQ will be mapped in i2c_device_probe only if client->irq is zero and
i2c_device_remove does not clear this. When rebinding an I2C device,
whos IRQ provider has also been rebound this means that an IRQ mapping
will never be created, causing the I2C device to fail to acquire its
IRQ. Fix this i
4.4, 4.9 and 4.14 contain a new file named
arch/riscv/include/asm/asm-prototypes.h
this doesnt seem to belong to these kernels since arch/riscv was not
even present before
Sebastian
Am 18.10.2018 um 19:54 schrieb Greg Kroah-Hartman:
This is the start of the stable review cycle for the 4.4.
On 2018/10/19 16:42, Boris Brezillon wrote:
On Fri, 19 Oct 2018 16:29:40 +0800
Liang Yang wrote:
On 2018/10/19 4:50, Boris Brezillon wrote:
On Thu, 18 Oct 2018 13:09:05 +0800
Jianxin Pan wrote:
+static int meson_nfc_buffer_init(struct mtd_info *mtd)
+{
+ struct nand_chip *nand
Hi Nava,
On Sat, 2018-10-20 at 14:11 +0530, Nava kishore Manne wrote:
> Add a reset controller driver for Xilinx Zynq UltraScale+ MPSoC.
> The zynqmp reset-controller has the ability to reset lines
> connected to different blocks and peripheral in the Soc.
>
> Signed-off-by: Nava kishore Manne
>
On 13/10/2018 09:20, Chaotian Jing wrote:
> MT8183 puts the tune register at top layer, so need add new code
> to support it.
>
> Signed-off-by: Chaotian Jing
> ---
> drivers/mmc/host/mtk-sd.c | 283
> ++
> 1 file changed, 233 insertions(+), 50 del
On 18-10-18, 17:01, Dmitry Torokhov wrote:
> On Thu, Oct 18, 2018 at 10:54:37AM +0530, Vinod wrote:
> > On 19-09-18, 18:49, Bjorn Andersson wrote:
> > > From: Vinod Koul
> > >
> > > Update the binding and driver for pms405 pwrkey.
> >
> > Rob, Dmitry
> >
> > Gentle reminder for this patch...
>
On Thu, Oct 18, 2018 at 03:41:29PM -0500, Rob Herring wrote:
> On Thu, Oct 18, 2018 at 05:03:13PM +0200, Marcel Holtmann wrote:
> > Hi Lars,
> >
> > > Add pn532 to the trivial-devices.txt binding doc.
> > >
> > > Signed-off-by: Lars Poeschel
> > > ---
> > > Documentation/devicetree/bindings/triv
On Fri, Oct 19, 2018 at 12:53 AM Rajat Jain wrote:
>
> Problem:
>
> The card detect IRQ does not work with modern BIOS (that want
> to use DSD to provide the card detect GPIO to the driver).
>
> Details:
>
> (Discussion: https://lkml.org/lkml/2018/9/25/1113)
We have a Link tag for such reference
On Fri, Oct 19, 2018 at 10:40:48AM +0200, Sebastian Gottschall wrote:
> 4.4, 4.9 and 4.14 contain a new file named
> arch/riscv/include/asm/asm-prototypes.h
>
> this doesnt seem to belong to these kernels since arch/riscv was not even
> present before
Good catch, patch now dropped from all of tho
Hi,
On Fri, Oct 19, 2018 at 02:23:27PM +0800, 陈华才 wrote:
> Hi, Sudeep,
>
> I use MIPS, and there is no "size" in
> /sys/devices/system/cpu/cpuX/cache/indexX/ file after your patch. Because
> the DT node only has "next-level-cache = <&L2>;" but has no "size"
> information.
>
Thanks for the confirm
Hi Philipp
Thanks for the quicks response
> -Original Message-
> From: Philipp Zabel [mailto:p.za...@pengutronix.de]
> Sent: Friday, October 19, 2018 2:33 PM
> To: Nava kishore Manne ; robh...@kernel.org;
> mark.rutl...@arm.com; Michal Simek ; Rajan Vaja
> ; Jolly Shah ;
> devicet...@
On 10/16/18 4:44 PM, Vinod wrote:
> On 16-10-18, 11:19, Pierre Yves MORDRET wrote:
>>
>>
>> On 10/15/18 7:14 PM, Vinod wrote:
>>> On 10-10-18, 09:02, Pierre Yves MORDRET wrote:
On 10/10/2018 06:03 AM, Vinod wrote:
> On 09-10-18, 10:40, Pierre Yves MORDRET wrote:
>>
>>
Nickhu 於 2018年10月18日 週四 下午4:38寫道：
>
> When the kernel configs of ftrace and frame pointer options are
> choosed, the compiler option of kernel will incompatible.
> Error message:
> nds32le-linux-gcc: error: -pg and -fomit-frame-pointer are
> incompatible
>
> Signed
Nickhu 於 2018年10月18日 週四 下午4:34寫道：
>
> The patches are about unaligned access handler. We fix some
> bugs in unaligned access handler and add some kernel configs
> for unaligned access handler. Then we add the kernel unaligned
> access handled by software in handler.
>
> Nickhu (3):
> nds32: Fix
Commit-ID: 9506a7425b094d2f1d9c877ed5a78f416669269b
Gitweb: https://git.kernel.org/tip/9506a7425b094d2f1d9c877ed5a78f416669269b
Author: Waiman Long
AuthorDate: Thu, 18 Oct 2018 21:45:17 -0400
Committer: Ingo Molnar
CommitDate: Fri, 19 Oct 2018 07:53:17 +0200
locking/lockdep: Fix debug_
Commit-ID: 01a14bda11add9dcd4a59200f13834d634559935
Gitweb: https://git.kernel.org/tip/01a14bda11add9dcd4a59200f13834d634559935
Author: Waiman Long
AuthorDate: Thu, 18 Oct 2018 21:45:18 -0400
Committer: Ingo Molnar
CommitDate: Fri, 19 Oct 2018 07:53:18 +0200
locking/lockdep: Make globa
The regmap API had a noinc_read function added for instances where devices
supported returning data from an internal FIFO in a single read.
This commit adds the noinc_write variant to allow writing to a non
incrementing register, this is used in devices such as the sx1301 for
loading firmware.
Si
From: Dong Aisheng
CAN transceiver is different on RevA and RevB board.
It's active high on RevA while active low on Rev B.
Signed-off-by: Dong Aisheng
Signed-off-by: Joakim Zhang
---
arch/arm/boot/dts/imx6sx-sdb.dts | 5
arch/arm/boot/dts/imx6sx-sdb.dtsi | 42 +
Hi Boris,
Sorry for the late reply.
I am busy with some other work.
> -Original Message-
> From: Boris Brezillon [mailto:boris.brezil...@bootlin.com]
> Sent: Thursday, October 4, 2018 1:09 AM
> To: Naga Sureshkumar Relli
> Cc: miquel.ray...@bootlin.com; rich...@nod.at; dw...@infradead.or
Hi Boris,
> -Original Message-
> From: Boris Brezillon [mailto:boris.brezil...@bootlin.com]
> Sent: Thursday, October 4, 2018 1:17 AM
> To: Naga Sureshkumar Relli
> Cc: miquel.ray...@bootlin.com; rich...@nod.at; dw...@infradead.org;
> computersforpe...@gmail.com; marek.va...@gmail.com; Mi
Lochnagar is an evaluation and development board for Cirrus
Logic Smart CODEC and Amp devices. It allows the connection of
most Cirrus Logic devices on mini-cards, as well as allowing
connection of various application processor systems to provide a
full evaluation platform. This driver supports the
Lochnagar is an evaluation and development board for Cirrus
Logic Smart CODEC and Amp devices. It allows the connection of
most Cirrus Logic devices on mini-cards, as well as allowing
connection of various application processor systems to provide a
full evaluation platform. This driver supports the
Lochnagar is an evaluation and development board for Cirrus
Logic Smart CODEC and Amp devices. It allows the connection of
most Cirrus Logic devices on mini-cards, as well as allowing
connection of various application processor systems to provide a
full evaluation platform. This driver supports the
Lochnagar is an evaluation and development board for Cirrus
Logic Smart CODEC and Amp devices. It allows the connection of
most Cirrus Logic devices on mini-cards, as well as allowing
connection of various application processor systems to provide a
full evaluation platform. This driver supports the
Lochnagar is an evaluation and development board for Cirrus
Logic Smart CODEC and Amp devices. It allows the connection of
most Cirrus Logic devices on mini-cards, as well as allowing
connection of various application processor systems to provide a
full evaluation platform. This driver supports the
Hi Paul,
I love your patch! Yet something to improve:
[auto build test ERROR on tty/tty-testing]
[also build test ERROR on v4.19-rc8 next-20181019]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day-ci/linux
Extend the documentation for trusted keys with documentation for how to
set up a key for a TPM 2.0 so it can be used with a TPM 2.0 as well.
Signed-off-by: Stefan Berger
Reviewed-by: Mimi Zohar
---
.../security/keys/trusted-encrypted.rst | 31 ++-
1 file changed, 30 insert
On 18/10/2018 12:18, Marcel Ziswiler wrote:
> From: Marcel Ziswiler
>
> This fixes the following error as seen post commit daecf46ee0e5
> ("ASoC: soc-core: use snd_soc_dai_link_component for platform") on
> Apalis TK1 after initial probe deferral:
>
> tegra-snd-sgtl5000 sound: ASoC: Both platf
Hi Ingo,
On Mon, Oct 08, 2018 at 06:15:24PM +0100, Mark Rutland wrote:
> On Tue, Sep 04, 2018 at 11:48:24AM +0100, Mark Rutland wrote:
> > As previously requested, this is a (trivial) rebase of the remaining
> > generated
> > atomic patches atop of v4.19-rc2, avoiding any potential conflict with
On Wednesday, October 17, 2018 1:39:54 PM CEST Andy Shevchenko wrote:
> On Wed, Oct 17, 2018 at 11:59 AM Hans de Goede wrote:
> >
> > Hi Rafael, Andy,
> >
> > For the why and what of this patch see the (somewhat long) commit message.
> >
> > The single patch in this set both touches drivers/acpi/s
On Wed, Oct 17, 2018 at 3:10 PM wrote:
>
> >
> > We take the normal path of sys_reboot => kernel_restart => machine_restart
> > ...
> >
> > I added code to print the c1 register in different paths. And I-cache
> > is enabled.
> > So now I am really confused about why the patch worked.
>
> Just sa
Hello Stephen,
On 10/10/2018 2:16 AM, Stephen Boyd wrote:
Quoting Taniya Das (2018-10-09 06:57:46)
diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c
index 6e3bd19..ca6142f 100644
--- a/drivers/clk/qcom/clk-rcg2.c
+++ b/drivers/clk/qcom/clk-rcg2.c
@@ -10,6 +10,7 @@
#includ
Arnd, Olof,
I know it is very late in this development cycle.
If possible, could you directly apply these two patches
to your ARM-SoC, aiming for the upcoming v4.20-rc1 MW?
If not, I can wait for v4.21-rc1.
Thanks,
Masahiro
Changes in v3:
- Capitalize 'Board' consistently
- Add Rob's Re
Now, the Socionext vendor directory is available at
Documentation/devicetree/bindings/arm/socionext/
Move cache-uniphier.txt over to it.
Signed-off-by: Masahiro Yamada
Reviewed-by: Rob Herring
---
Changes in v3: None
Changes in v2:
- New patch
.../devicetree/bindings/arm/{uniphier => socio
Document the list of SoCs and boards of UniPhier platform.
Signed-off-by: Masahiro Yamada
Reviewed-by: Rob Herring
---
Changes in v3:
- Capitalize 'Board' consistently
- Add Rob's Reviewed-by
Changes in v2:
Changes suggested by Rob.
- Move the file to
Documentation/devicetree/bindi
Hello Stephen,
On 10/10/2018 2:04 AM, Stephen Boyd wrote:
Quoting Taniya Das (2018-10-09 06:57:47)
diff --git a/drivers/clk/qcom/dispcc-sdm845.c b/drivers/clk/qcom/dispcc-sdm845.c
index 0cc4909..6d3136a 100644
--- a/drivers/clk/qcom/dispcc-sdm845.c
+++ b/drivers/clk/qcom/dispcc-sdm845.c
@@ -128
On 2018/10/19 8:54, Sergey Senozhatsky wrote:
> On (10/18/18 20:58), Tetsuo Handa wrote:
>>>
>>> A knob might do.
>>> As well as /proc/sys/kernel/printk tweaks, probably. One can even add
>>> echo "a b c d" > /proc/sys/kernel/printk to .bashrc and adjust printk
>>> console levels on login and rollb
Hi,
Thanks for the patch...
>
> This patch introduces the xilinx_prep_dma_addr_t macro which prepares
> dma_addr_t from hardware buffer descriptor LSB and MSB fields. It will be
> used in simple dma 64-bit programming sequence.
>
> Signed-off-by: Radhey Shyam Pandey
Reviewed-by: Appan
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