Add support for octal I/O data transfer in spi-mem framework.
Signed-off-by: Yogesh Gaur
---
Changes for v2:
Patch added in v2 version.
drivers/spi/spi-mem.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c
index c6bdea7.
Add mode flags for octal I/O data transfer support.
NXP FlexSPI controller supports octal mode data transfer.
Signed-off-by: Yogesh Gaur
---
Changes for v2:
None
drivers/spi/spi-nxp-fspi.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/spi/spi-nxp-fspi.c b/driv
Flash mt35xu512aba connected to FlexSPI controller supports
1-1-8/1-8-8 protocol.
Added flag spi-rx-bus-width and spi-tx-bus-width with values as
8 and 8 respectively for both flashes connected at CS0 and CS1.
Signed-off-by: Yogesh Gaur
---
Changes for v2:
None
arch/arm64/boot/dts/freescale/fs
Emlid Neutis N5 is a SoM based on Allwinner H5, has a WiFi & BT
module, DDR3 RAM and eMMC.
- add neutis n5 dtsi file for SoM needs
- add neutis devboard dts file
- add neutis devboard target to dtb makefile
Signed-off-by: Aleksandr Aleksandrov
---
arch/arm64/boot/dts/allwinner/Makefile
This patch addes Neutis N5 support.
Emlid Neutis N5 is a SoM based on Allwinner H5.
The patch includes device tree file for Dev board
and dtsi file for SoM needs.
Changes from v1: separate dts file: dtsi for SoM
and motherboard dts file that inlcudes dtsi file.
Changes from v2 (5 oct 2018):
- mak
Add vendor Emlid Ltd to vendor-prefixes.txt
Acked-by: Rob Herring
Signed-off-by: Aleksandr Aleksandrov
---
Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt
b/Documentation/devicetree/
On 13/10/2018 16:54, lantianyu1...@gmail.com wrote:
> while (mmu_unsync_walk(parent, &pages)) {
> bool protected = false;
> + LIST_HEAD(flush_list);
>
> - for_each_sp(pages, sp, parents, i)
> + for_each_sp(pages, sp, parents, i) {
>
On 13/10/2018 16:53, lantianyu1...@gmail.com wrote:
> @@ -1781,6 +1781,11 @@ static int kvm_set_pte_rmapp(struct kvm *kvm, struct
> kvm_rmap_head *rmap_head,
> }
> }
>
> + if (need_flush && kvm_available_flush_tlb_with_range()) {
> + kvm_flush_remote_tlbs_with
On Mon, Oct 8, 2018 at 5:24 PM Jack Wang wrote:
>
> From: Jack Wang
>
> After 9e1cc0a54556 ("md: use mddev_suspend/resume instead of ->quiesce()")
> We still have similar left in bitmap functions.
>
> Replace quiesce() with mddev_suspend/resume.
>
> Also move md_bitmap_create out of mddev_suspend
Hi Yogesh,
On Mon, 15 Oct 2018 11:47:55 +
Yogesh Narayan Gaur wrote:
> Add support for octal mode IO data transfer.
> Micron flash, mt35xu512aba, supports octal mode data transfer and
> NXP FlexSPI controller supports 8 data lines for data transfer (Rx/Tx).
>
> Patch series
> * Add support
On 15.10.2018 13:38, Claudio Imbrenda wrote:
> I don't have objections to this patch, but I wonder how much impact it
> would have. Have you performed any tests? does it really have such a big
> impact on the availability of order-1 page blocks?
I have no synthetic tests on compaction, so this pa
From: Rafael J. Wysocki
Since the correction factor cannot be greater than RESOLUTION * DECAY,
the result of the predicted_us computation in menu_select() cannot be
greater than data->next_timer_us, so it is not necessary to compare
the "typical interval" value coming from get_typical_interval()
Hi All,
The following patches are two more refinements of the menu governor (on top
of the recent changes in linux-next now). The are not expected to change the
overall behavior of it.
Please refer to the patch changelogs for details.
Thanks,
Rafael
From: Rafael J. Wysocki
If the minimum interval taken into account in the average computation
loop in get_typical_interval() is less than the expected idle
duration determined so far, the resultant average cannot be greater
than that value as well and the entire return result of the function
is g
Hi Boris,
> -Original Message-
> From: Boris Brezillon [mailto:boris.brezil...@bootlin.com]
> Sent: Monday, October 15, 2018 5:24 PM
> To: Yogesh Narayan Gaur
> Cc: linux-...@lists.infradead.org; marek.va...@gmail.com; vigne...@ti.com;
> linux-...@vger.kernel.org; devicet...@vger.kernel.o
From: Rafael J. Wysocki
Add low-level support for the (optional) real time capability of the
ACPI Time and Alarm Device (TAD) to the ACPI TAD driver.
This allows the real time to be acquired or set via sysfs with the
help of the _GRT and _SRT methods of the TAD, respectively.
Signed-off-by: Raf
On 2018-10-14 06:19, William Breathitt Gray wrote:
> a bit value of 0 in the
> bits array does not necessarily mean the input was not requested, but
> may instead mean that the value at the input is 0;
sure enough, but...
> therefore, the caller
> must keep track of the requested inputs rather t
On 10/12, Enke Chen wrote:
>
> For simplicity and consistency, this patch provides an implementation
> for signal-based fault notification prior to the coredump of a child
> process. A new prctl command, PR_SET_PREDUMP_SIG, is defined that can
> be used by an application to express its interest and
Hi All,
On 2018-10-08 15:17, Marc Zyngier wrote:
> + Mark Rutland
>
> Hi Marek,
>
> On 08/10/18 13:50, Marek Szyprowski wrote:
>> Use common infrastructure for ARM Architected Timers erratum to enable
>> support for systems with broken CPU firmware (timer registers not
>> properly configured). Thi
Add flags for Octal I/O data transfer
Required for the SPI controller which can do the data transfer (TX/RX)
on 8 data lines e.g. NXP FlexSPI controller.
SPI_TX_OCTAL: transmit with 8 wires
SPI_RX_OCTAL: receive with 8 wires
Signed-off-by: Yogesh Gaur
---
Changes for v2:
Incorporated review co
Add octal read flag for flash mt35xu512aba.
This flash, mt35xu512aba, is only complaint to SFDP JESD216B and does
not seem to support newer JESD216C standard that provides auto
detection of Octal mode capabilities and opcodes. Therefore, this
capability is manually added using new SPI_NOR_OCTAL_REA
- Add opcodes for octal I/O commands
* Read : 1-1-8 and 1-8-8 protocol
* Write : 1-1-8 and 1-8-8 protocol
* opcodes for 4-byte address mode command
- Entry of macros in _convert_3to4_xxx function
- Add flag specifying flash support octal read commands.
Signed-off-by: Vignesh R
Signed-off
Flash mt35xu512aba connected to FlexSPI controller supports
1-1-8/1-8-8 protocol.
Added flag spi-rx-bus-width and spi-tx-bus-width with values as
8 and 8 respectively for both flashes connected at CS0 and CS1.
Signed-off-by: Yogesh Gaur
---
Changes for v2:
Make spi-tx-bus-width as 8.
arch/arm6
Add mode flags for octal I/O data transfer support.
NXP FlexSPI controller supports octal mode data transfer.
Signed-off-by: Yogesh Gaur
---
Changes for v2:
None
drivers/spi/spi-nxp-fspi.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/spi/spi-nxp-fspi.c b/driv
Add support for octal mode IO data transfer.
Micron flash, mt35xu512aba, supports octal mode data transfer and
NXP FlexSPI controller supports 8 data lines for data transfer (Rx/Tx).
Patch series
* Add support for octal mode flags and parsing of same in spi driver.
* Add parsing logic for spi-mem
Add support for octal I/O data transfer based on the controller (spi)
mode.
Assign hw-capability mask bits for octal transfer.
Signed-off-by: Yogesh Gaur
---
Changes for v2:
Incorporated review comments of Boris.
drivers/mtd/devices/m25p80.c | 9 -
1 file changed, 8 insertions(+), 1 de
Add support for octal I/O data transfer in spi-mem framework.
Signed-off-by: Yogesh Gaur
---
Changes for v2:
Patch added in v2 version.
drivers/spi/spi-mem.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c
index c6bdea7.
Hello,
On Mon 15-10-18 04:32:02, syzbot wrote:
> syzbot found the following crash on:
>
> HEAD commit:90ad18418c2d Merge git://git.kernel.org/pub/scm/linux/kern..
> git tree: upstream
> console output: https://syzkaller.appspot.com/x/log.txt?x=17f1776e40
> kernel config: https://sy
On Fri, Oct 12, 2018 at 12:57 PM Dmitry Safonov wrote:
>
> Hi Guilherme,
>
> Just to let you know - I've done with more urgent issues now,
> so I'll be back on this patch on Monday, installing qemu-system-hppa
> and debugging the root case.
>
> Thanks,
> Dmitry
Awesome Dmitry, thanks for the head
+++ Mathieu Desnoyers [13/10/18 15:10 -0400]:
commit 46e0c9be206f ("kernel: tracepoints: add support for relative
references") changes the layout of the __tracepoint_ptrs section on
architectures supporting relative references. However, it does so
without turning struct tracepoint * const into co
On Mon, Oct 15, 2018 at 12:27 PM Amir Goldstein wrote:
>
> On Mon, Oct 15, 2018 at 10:50 AM Rong Chen wrote:
> [...]
> > the patch seems not work.
> >
> > tests: 1
> > testcase/path_params/tbox_group/run:
> > will-it-scale/16-thread-unlink2-performance/lkp-bdw-ep3d
> >
> > commit:
> >1e6cb7
On 15/10/2018 14:12, Marek Szyprowski wrote:
> Hi All,
>
> On 2018-10-08 15:17, Marc Zyngier wrote:
>> + Mark Rutland
>>
>> Hi Marek,
>>
>> On 08/10/18 13:50, Marek Szyprowski wrote:
>>> Use common infrastructure for ARM Architected Timers erratum to enable
>>> support for systems with broken CPU
On Mon, 15 Oct 2018 13:22:12 +0200
Ard Biesheuvel wrote:
> (+ Masami)
>
> On 15 October 2018 at 13:16, Anders Roxell wrote:
> > Commit 1404d6f13e47 ("arm64: dump: Add checking for writable and exectuable
> > pages")
> > has successfully identified code that leaves a page with W+X
> > permissio
On Mon, Oct 15, 2018 at 2:15 PM, Jan Kara wrote:
> Hello,
>
> On Mon 15-10-18 04:32:02, syzbot wrote:
>> syzbot found the following crash on:
>>
>> HEAD commit:90ad18418c2d Merge git://git.kernel.org/pub/scm/linux/kern..
>> git tree: upstream
>> console output: https://syzkaller.appspot.
On Exynos SoCs enabling MCT driver is required even if ARM Architected
Timer driver is used to for managing timer hardware and clock source
events.
Signed-off-by: Marek Szyprowski
---
arch/arm64/Kconfig.platforms | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/Kconfig.platforms b/
Exynos Multi-Core Timer driver (exynos_mct) must be started before
ARM Architected Timers (arch_timer), because both timers share common
hardware block and turning on MCT is needed to get ARM Architected
Timer working properly.
Signed-off-by: Marek Szyprowski
Acked-by: Krzysztof Kozlowski
---
i
While freeing interrupt handlers in error path, don't assume that all
requested interrupts are per-processor interrupts and properly release
standard interrupts too.
Suggested-by: Krzysztof Kozlowski
Fixes: 56a94f13919c ("clocksource: exynos_mct: Avoid blocking calls in the cpu
hotplug notifier"
Dear All,
This patchset is an attempt to submit the last piece of missing code
to have proper support for Exynos5433 SoCs based TM2(e) boards. It
performs a cleanup of timer configuration, which so far needed various
out-of-tree workarounds. The fixes provided by this patchset are also
needed for
Exynos Multi-Core Timer driver is used only on device-tree based
systems, so remove non-dt related code. In case of !CONFIG_OF
the code is anyway equal because of_irq_count() has a stub
returning 0.
Signed-off-by: Marek Szyprowski
Reviewed-by: Krzysztof Kozlowski
---
drivers/clocksource/exynos_
To get ARM Architected Timers working on Samsung Exynos SoCs, one has to
first configure and enable Exynos Multi-Core Timer, because they both
share some common hardware blocks. This patch adds a mode of cooperation
with arch_timer driver, so kernel can use CP15 based timer interface via
arch_timer
Move ARM architected timer device-tree node to the beginning of 'soc'
node, to group it together with other ARM CPU core devices (like PMU).
Signed-off-by: Marek Szyprowski
---
arch/arm64/boot/dts/exynos/exynos5433.dtsi | 23 +++---
1 file changed, 12 insertions(+), 11 deletions(
Zong Li 於 2018年10月3日 週三 上午11:12寫道：
>
> This patches contain the modificaion as follows:
> 1. Fix up the building fail on RV32.
> 2. Add umoddi3 and udivmoddi4 functions for RV32.
> 3. Fix ioremap problem on RV32.
>
> Thanks all for review these code and modify the copyright description.
>
> Change
On 8/30/18 9:54 PM, Dmitry Osipenko wrote:
> Hello,
>
> This patch series fixes couple bugs in the memory self-refresh code.
> The EMC / MC state is properly restored after patches being applied,
> please review.
>
> Dmitry Osipenko (4):
> ARM: tegra: Fix missed EMC registers latching on resume
On 8/30/18 9:04 PM, Dmitry Osipenko wrote:
> Hello,
>
> All consumer-grade Tegra30 devices, like Nexus 7 tablet; Ouya console and
> others, use Trusted Foundations firmware that doesn't allow CPU to access
> secure registers directly from the Linux kernel, these accesses shall be
> done via the fi
On 8/30/18 10:04 PM, Dmitry Osipenko wrote:
> Hello,
>
> This patch-series fixes CPU hanging after suspend-resume / LP2 cpuidle
> on Tegra30. The bug really appears during stress-testing, like frequent
> suspending under variable load + the upcoming Tegra30 CPUFREQ driver.
>
> Dmitry Osipenko (2)
Hello,
On Fri, Sep 7, 2018 at 12:34 PM Benjamin Tissoires
wrote:
>
> Hi Jiri, Nestor,
>
> I have this series in my tree for a while now (first commit was in January).
> I never sent it (as far as I can remember*) because I was requesting
> feedback regarding the G920 wheel. I think I haven't brea
On 8/30/18 9:36 PM, Dmitry Osipenko wrote:
> This fixes splats like the one below if CONFIG_DEBUG_ATOMIC_SLEEP=y
> and machine (Tegra30) booted with SMP=n or all secondary CPU's are put
> offline.
>
> BUG: sleeping function called from invalid context at
> kernel/locking/mutex.c:254
> in_atomic
The atomic replace allows to create cumulative patches. They
are useful when you maintain many livepatches and want to remove
one that is lower on the stack. In addition it is very useful when
more patches touch the same function and there are dependencies
between them.
Now, the question is if 13
From: Joe Lawrence
Add a few livepatch modules and simple target modules that the included
regression suite can run tests against:
- basic livepatching (multiple patches, atomic replace)
- pre/post (un)patch callbacks
- shadow variable API
Signed-off-by: Joe Lawrence
---
Documentation/l
The atomic replace and cumulative patches were introduced as a more secure
way to handle dependent patches. They simplify the logic:
+ Any new cumulative patch is supposed to take over shadow variables
and changes made by callbacks from previous livepatches.
+ All replaced patches are dis
User documentation for the atomic replace feature. It makes it easier
to maintain livepatches using so-called cumulative patches.
Signed-off-by: Petr Mladek
---
Documentation/livepatch/cumulative-patches.txt | 105 +
1 file changed, 105 insertions(+)
create mode 100644 D
module_put() is currently never called in klp_complete_transition() when
klp_force is set. As a result, we might keep the reference count even when
klp_enable_patch() fails and klp_cancel_transition() is called.
This might make an assumption that a module might get blocked in some
strange init sta
The address of the to be patched function and new function is stored
in struct klp_func as:
void *new_func;
unsigned long old_addr;
The different naming scheme and type is derived from the way how
the addresses are set. @old_addr is assigned at runtime using
kallsyms-based search.
The code for freeing livepatch structures is a bit scattered and tricky:
+ direct calls to klp_free_*_limited() and kobject_put() are
used to release partially initialized objects
+ klp_free_patch() removes the patch from the public list
and releases all objects except for patch->kobj
Replaced patches are removed from the stack when the transition is
finished. It means that Nop structures will never be needed again
and can be removed. Why should we care?
+ Nop structures make false feeling that the function is patched
even though the ftrace handler has no effect.
+ Ftr
From: Jason Baron
Sometimes we would like to revert a particular fix. Currently, this
is not easy because we want to keep all other fixes active and we
could revert only the last applied patch.
One solution would be to apply new patch that implemented all
the reverted functions like in the origi
The possibility to re-enable a registered patch was useful for immediate
patches where the livepatch module had to stay until the system reboot.
The improved consistency model allows to achieve the same result by
unloading and loading the livepatch module again.
Also we are going to add a feature
From: Jason Baron
Currently klp_patch contains a pointer to a statically allocated array of
struct klp_object and struct klp_objects contains a pointer to a statically
allocated array of klp_func. In order to allow for the dynamic allocation
of objects and functions, link klp_patch, klp_object, a
The definition of struct klp_func might be a bit confusing.
The original function is defined by name as a string.
The new function is defined by name as a function pointer
casted to unsigned long.
This patch adds helper macros that hide the different types.
The functions are defined just by the na
We are going to simplify the API and code by removing the registration
step. This would require calling init/free functions from enable/disable
ones.
This patch just moves the code to prevent more forward declarations.
This patch does not change the code except of two forward declarations.
Signe
On 2018/10/11 5:22, Jaegeuk Kim wrote:
> If we clear the cold data flag out of the writeback flow, we can miscount
> -1 by end_io.
I didn't get it, which count do you mean?
Thanks,
>
> Signed-off-by: Jaegeuk Kim
> ---
> fs/f2fs/data.c | 4
> 1 file changed, 4 deletions(-)
>
> diff --git
Hi Mathias,
On 28/09/18 15:11, Jon Hunter wrote:
> This series add genpd support for the Tegra xHCI device that requires
> more than one power-domain to operate.
>
> This series is making changes to more than one subsystem and at first
> glance may look like a maintainers nightmare. However, my p
On 7/24/18 7:42 PM, Dmitry Osipenko wrote:
> Changelog:
>
> v5:
> - Fixed wrong EMC clock divider type in the "Turn EMC clock gate into
> divider" patch. It is a Tegra's fractional 7.1 divider and not a
> simple integer divider. Peter, please take a look at the change.
Hi Dmirty!
On Mon 15-10-18 14:29:14, Dmitry Vyukov wrote:
> On Mon, Oct 15, 2018 at 2:15 PM, Jan Kara wrote:
> > Hello,
> >
> > On Mon 15-10-18 04:32:02, syzbot wrote:
> >> syzbot found the following crash on:
> >>
> >> HEAD commit:90ad18418c2d Merge
> >> git://git.kernel.org/pub/scm/linux/k
On 2018/10/15 20:24, Michal Hocko wrote:
> On Mon 15-10-18 19:57:35, Tetsuo Handa wrote:
>> On 2018/10/15 17:19, Michal Hocko wrote:
>>> As so many dozens of times before, I will point you to an incremental
>>> nature of changes we really prefer in the mm land. We are also after a
>>> simplicity wh
Extend qcom-opp bindings with properties needed for Core Power Reduction
(CPR).
CPR is included in a great variety of Qualcomm SoC, e.g. msm8916 and
msm8996, and was first introduced in msm8974.
Signed-off-by: Niklas Cassel
---
Hello Rob, Rajendra,
Sorry for not replying sooner.
Since Rob wante
On Mon, 15 Oct 2018 at 13:34, Rafael J. Wysocki wrote:
>
> On Monday, October 15, 2018 11:34:33 AM CEST Waldemar Rymarkiewicz wrote:
> > On Thu, 11 Oct 2018 at 23:10, Rafael J. Wysocki wrote:
> > >
> > > On Tuesday, October 9, 2018 6:06:08 PM CEST Waldemar Rymarkiewicz wrote:
> > > > On Tue, 9 Oc
On 15 October 2018 at 09:33, Wolfram Sang wrote:
>
>> Some sub-systems rebase, and some do not.
>> It is up to the sub-system maintainer.
>
> We used to have a very strict rule to not rebase anything which ends up
> in linux-next. Dunno what happened to this rule but I liked it.
>
>> I know what y
On 30/08/18 19:36, Dmitry Osipenko wrote:
> This fixes splats like the one below if CONFIG_DEBUG_ATOMIC_SLEEP=y
> and machine (Tegra30) booted with SMP=n or all secondary CPU's are put
> offline.
>
> BUG: sleeping function called from invalid context at
> kernel/locking/mutex.c:254
> in_atomi
PCI controller in K2G also has a limitation that memory read request
size (MRRS) must not exceed 256 bytes. Use the quirk to limit MRRS
(added for K2HK, K2L and K2E) for K2G as well.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/controller/dwc/pci-keystone.c | 3 +++
1 file changed, 3 in
No functional change. Remove unused "msi_intc_np" argument from
ks_dw_pcie_host_init().
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/controller/dwc/pci-keystone-dw.c | 3 +--
drivers/pci/controller/dwc/pci-keystone.c| 2 +-
drivers/pci/controller/dwc/pci-keystone.h| 3 +--
3 fil
Add bindings to get device control module which has the device id and
vendor id to be configured in the keystone PCIe controller.
Signed-off-by: Kishon Vijay Abraham I
Reviewed-by: Rob Herring
---
Documentation/devicetree/bindings/pci/pci-keystone.txt | 3 +++
1 file changed, 3 insertions(+)
d
Reuse the already existing quirk to set MRRS for PCI host bridge
instead of explicitly setting MRRS in ks_pcie_host_init.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/controller/dwc/pci-keystone.c | 37 +--
1 file changed, 15 insertions(+), 22 deletions(-)
diff --gi
Hi Paolo:
Thanks for your review.
On Mon, Oct 15, 2018 at 6:04 PM Paolo Bonzini wrote:
>
> On 13/10/2018 16:53, lantianyu1...@gmail.com wrote:
> > + bool flush = false;
> > int i;
> >
> > spin_lock(&kvm->mmu_lock);
> > @@ -5654,18 +5655,27 @@ void kvm_zap_gfn_range(s
No functional change. Move dw_pcie_setup_rc out of
ks_pcie_establish_link() so that ks_pcie_establish_link can be used only
to start the link.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/controller/dwc/pci-keystone.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --gi
No functional change. Remove redundant platform_set_drvdata invocation
in ks_pcie_probe().
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/controller/dwc/pci-keystone.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/pci/controller/dwc/pci-keystone.c
b/drivers/pci/controller/
Control module registers should be read using syscon APIs.
pci-keystone.c uses platform_get_resource to get control module registers.
Fix it here by using syscon APIs to get device id from control module.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/controller/dwc/pci-keystone.c | 45 ++
Invoke pm_runtime APIs to enable clocks and remove explicit
clock enabling using clk_prepare_enable().
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/controller/dwc/pci-keystone.c | 28 ++-
1 file changed, 12 insertions(+), 16 deletions(-)
diff --git a/drivers/pci/con
commit 025dd3daeda77f61a280da87ae701 ("PCI: keystone: Add error IRQ
handler") added dev_err() message only for ERR_AXI and ERR_FATAL. Add
debug error message for ERR_SYS, ERR_NONFATAL, ERR_CORR and ERR_AER here.
While at that avoid using ERR_IRQ_STATUS_RAW and use ERR_IRQ_STATUS
instead.
Signed-o
Cleanup PHY handling by using devm_phy_optional_get to get PHYs if
the PHYs are optional, creating a device link between the PHY device
and the controller device and disable PHY on error cases here.
Also invoke phy_reset() as part of initializing PHY.
Signed-off-by: Kishon Vijay Abraham I
---
dr
No functional change. Some function names begin with ks_dw_pcie_*
and some function names begin with ks_pcie_*. Modify it so that
all function names begin with ks_pcie_*.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/controller/dwc/pci-keystone.c | 221 +++---
1 file chan
No functional change. Cleanup macros defined in pci-keystone.c
by removing unused macros, grouping the macros and aligning
it properly.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/controller/dwc/pci-keystone.c | 41 +--
1 file changed, 16 insertions(+), 25 deletions
commit 886bc5ceb5cc3ad4b219502d72 ("PCI: designware: Add generic
dw_pcie_wait_for_link()") while adding a generic dw_pcie_wait_for_link()
performed a special handling (initiate link training multiple times) for
keystone which is not required. This also resulted in unncessarily waiting
for more time
This series was sent as part of RFC series [1]
The PCIe controller in AM654 uses Synopsys core revision 4.90a and uses
the same TI wrapper as used in keystone2 with certain modification.
Hence AM654 will use the same pci wrapper driver pci-keystone.c
In preparation for adding AM654 support, clean
Instead of having a fixed outbound window count, get the number of
outbound windows from device tree. Also cleanup memory space configuration
here by adding macros for constants.
While at that also use BIT() macro for OB_XLAT_EN_VAL.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/control
No functional change. Use BIT() macro for DBI_CS2 and cleanup
set_dbimode and get_dbi_mode
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/controller/dwc/pci-keystone.c | 12 +++-
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/drivers/pci/controller/dwc/pci-keystone.
No functional change. Having two different files for keystone PCI driver
doesn't serve any purpose. Merge pci-keystone-dw.c and pci-keystone.c
into a single pci-keystone.c file and remove pci-keystone.h
Signed-off-by: Kishon Vijay Abraham I
---
MAINTAINERS | 2
Cleanup configuration space access by removing ks_pcie_cfg_setup
which has an unncessary check of "if (bus == 0)" which will never be the
case of *_other_conf() and adding macros for configuring the CFG_SETUP
register required for accessing the configuration space of the device.
Signed-off-by: Kis
No functional change. Reorder header file in alphabetical order.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/controller/dwc/pci-keystone.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/pci/controller/dwc/pci-keystone.c
b/drivers/pci/controller/dwc
ks_pcie_link_up() uses registers from the designware core to get the
status of the link. Move the register defines to pcie-designware.h
and cleanup ks_pcie_link_up().
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/controller/dwc/pci-keystone.c| 11 +++
drivers/pci/controller/d
On 13.10.18 17:12, Andy Lutomirski wrote:
On Sat, Oct 13, 2018 at 3:02 AM Jan Kiszka wrote:
From: Jan Kiszka
Even if we are not on an entry stack, we have to initialize the CS high
bits because we are unconditionally evaluating them
PARANOID_EXIT_TO_KERNEL_MODE. Failing to do so broke the bo
From: Jan Kiszka
> Sent: 15 October 2018 14:09
...
> > Those fields are genuinely 16 bit. So the comment should say
> > something like "Those high bits are used for CS_FROM_ENTRY_STACK and
> > CS_FROM_USER_CR3".
>
> /*
> * The high bits of the CS dword (__csh) are used for
> * CS_FROM_ENTRY_S
On 12 October 2018 at 16:57, Masahiro Yamada
wrote:
> Once DMA is enabled, it is not possible to disable it because
> uniphier_sd_dma_endisable() always sets the DMA_ENABLE_DMASDRW bit
> regardless of the argument 'enable'. It should disable DMA when
> 'enable' is false.
>
> Signed-off-by: Masahir
On 10 October 2018 at 05:51, Masahiro Yamada
wrote:
> CTL_SDIO_REGS is a register specific to tmio_mmc.c
>
> Currently, we handle it in tmio_mmc_core.c, hence need
> TMIO_MMC_HAVE_HIGH_REG flag to prevent the other platforms
> from accessing to it.
>
> We can just move CTL_SDIO_REGS to tmio_mmc.c
On 12 October 2018 at 16:57, Masahiro Yamada
wrote:
> host->chan_rx is NULL when UNIPHIER_SD_CAP_BROKEN_DMA_RX quirk flag
> is set. In this case, it should not set up DMA.
>
> Signed-off-by: Masahiro Yamada
Applied for next, thanks!
Kind regards
Uffe
> ---
>
> drivers/mmc/host/uniphier-sd.c
On 13 October 2018 at 09:20, Chaotian Jing wrote:
> this series of patch include below changes:
> 1. Add MT8183 SoC support in Mediatek MMC DT bindings
> 2. Fill mmc->actual_clock
> 3. Fix cannot receive new request issue
> 4. Tune CMD/DATA together to save tuning time
> 5. Add MT8183 MMC driver s
On 15.10.18 15:14, David Laight wrote:
From: Jan Kiszka
Sent: 15 October 2018 14:09
...
Those fields are genuinely 16 bit. So the comment should say
something like "Those high bits are used for CS_FROM_ENTRY_STACK and
CS_FROM_USER_CR3".
/*
* The high bits of the CS dword (__csh) are used
On Tue, Oct 9, 2018 at 3:34 AM, Theodore Y. Ts'o wrote:
> On Mon, Oct 08, 2018 at 06:29:54PM +0200, Dmitry Vyukov wrote:
>>
>> The program that triggered it did the following:
>>
>> 05:23:28 executing program 5:
>> r0 = creat(&(0x7f0001c0)='./file0\x00', 0x0)
>> socketpair$unix(0x1, 0x1, 0x0,
On Mon, Oct 15, 2018 at 02:31:09PM +0200, Marek Szyprowski wrote:
> To get ARM Architected Timers working on Samsung Exynos SoCs, one has to
> first configure and enable Exynos Multi-Core Timer, because they both
> share some common hardware blocks.
Could you please elaborate on what exactly is sh
On Wed, Oct 10, 2018 at 08:21:38PM +0530, Vinod Koul wrote:
> From: Shefali Jain
>
> Add the clocks supported in global clock controller which clock the
> peripherals like BLSPs, SDCC, USB, MDSS etc. Register all the clocks
> to the clock framework for the clients to be able to request for them.
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