On 09/27/2018 11:24 AM, Michal Vokáč wrote:
> The reset signal can be produced by GPIO expander that can sleep.
> In that case the probe function fails. Allow using GPIO expanders for
> the reset signal by using the non-atomic gpiod_set_value_cansleep()
> function.
>
> Signed-off-by: Michal Voká
On Mon, Oct 08, 2018 at 09:17:11AM +0300, Alexey Budankov wrote:
SNIP
> static int record__mmap_read_evlist(struct record *rec, struct perf_evlist
> *evlist,
> bool overwrite)
> {
> @@ -520,7 +644,10 @@ static int record__mmap_read_evlist(struct record *rec,
On 09/27/2018 11:24 AM, Michal Vokáč wrote:
> The SSD130x OLED display reset signal is active low. Now the reset
> sequence is implemented in such a way that users are forced to
> define reset-gpios as GPIO_ACTIVE_HIGH in DT to make the reset work.
>
> Do not hard code the active-low sequence in
On Mon, Oct 08, 2018 at 09:19:17AM +0300, Alexey Budankov wrote:
SNIP
> #ifdef HAVE_AIO_SUPPORT
> } else {
> + int idx;
> /*
>* Call record__aio_sync() to wait till
> map->data buffer
On Mon, Oct 8, 2018 at 6:48 AM Stephen Rothwell wrote:
>
> Hi all,
>
> Today's linux-next merge of the drivers-x86 tree got a conflict in:
>
> drivers/platform/x86/intel_mid_powerbtn.c
>
> between commit:
>
> f2c4db1bd807 ("x86/cpu: Sanitize FAM6_ATOM naming")
>
> from the tip tree and commit:
On Mon, Oct 8, 2018 at 6:44 AM Stephen Rothwell wrote:
>
> Hi all,
>
> Today's linux-next merge of the drivers-x86 tree got a conflict in:
>
> drivers/platform/x86/intel_int0002_vgpio.c
>
> between commit:
>
> f2c4db1bd807 ("x86/cpu: Sanitize FAM6_ATOM naming")
>
> from the tip tree and commit
On Mon, Oct 08, 2018 at 09:17:11AM +0300, Alexey Budankov wrote:
SNIP
> static int record__mmap_read_evlist(struct record *rec, struct perf_evlist
> *evlist,
> bool overwrite)
> {
> @@ -520,7 +644,10 @@ static int record__mmap_read_evlist(struct record *rec,
On Mon, Oct 08, 2018 at 09:17:11AM +0300, Alexey Budankov wrote:
SNIP
> static int record__mmap_read_evlist(struct record *rec, struct perf_evlist
> *evlist,
> bool overwrite)
> {
> @@ -520,7 +644,10 @@ static int record__mmap_read_evlist(struct record *rec,
On Mon, 8 Oct 2018 at 05:02, Liran Alon wrote:
>
>
>
> > On 28 Sep 2018, at 9:12, Wanpeng Li wrote:
> >
> > From: Wanpeng Li
> >
> > In cloud environment, lapic_timer_advance_ns is needed to be tuned for
> > every CPU
> > generations, and every host kernel versions(the
> > kvm-unit-tests/tscde
On Sat, Oct 6, 2018 at 8:04 AM Andrei Vagin wrote:
> On Thu, Oct 04, 2018 at 12:50:22AM +0200, Laurent Vivier wrote:
> > This patch allows to have a different binfmt_misc configuration
> > for each new user namespace. By default, the binfmt_misc configuration
> > is the one of the host, but if the
On 10/8/2018 4:08 PM, Niklas Cassel wrote:
On Mon, Oct 08, 2018 at 03:29:52PM +0530, Viresh Kumar wrote:
On 08-10-18, 10:40, Niklas Cassel wrote:
+ ret = of_parse_phandle_with_args(cpu_np, "qcom,freq-domain",
+ "#freq-domain-cells", 0, &args);
He
Support for "%pCr" was removed, but a reference in a comment was
forgotten.
Fixes: 666902e42fd8344b ("lib/vsprintf: Remove atomic-unsafe support for %pCr")
Signed-off-by: Geert Uytterhoeven
---
Probably this wasn't noticed due to commit 5e4ee7b13b522d07 ("printk:
synchronize %p formatting documen
Linux next build for arm64 failed due to
numa.c:34:10: fatal error: asm/kaslr.h: No such file or directory
On Wed, 3 Oct 2018 at 19:52, tip-bot for Peter Zijlstra (Intel)
wrote:
>
> Commit-ID: 3a387c6d96e69f1710a3804eb68e1253263298f2
> Gitweb:
> https://git.kernel.org/tip/3a387c6d96e69f1710
Hi Miquel,
On Mon, 8 Oct 2018 09:53:34 +0200 Miquel Raynal
wrote:
>
> Stephen Rothwell wrote on Mon, 8 Oct 2018
> 11:38:42 +1100:
>
> > Hi Boris,
>
> Boris is still there but I'm in charge of the NAND tree these days (and
> the one to blame too for this one :) ).
I'll add you as a contact
Add binding file for NXP FlexSPI controller
Signed-off-by: Yogesh Gaur
---
Changes for v4:
- Incorporated Rob review comments.
Changes for v3:
- Removed node property 'big-endian'.
Changes for v2:
- Incorporated Rob review comments.
.../devicetree/bindings/spi/spi-nxp-fspi.txt | 39 ++
Calling of_node_put() decreases the reference count of a device tree
object, and may free some data.
However, the of_phandle_args structure embedding it is passed to
reset_controller_dev.of_xlate() after that, so it may still be accessed.
Move the call to of_node_put() down to fix this.
Signed-o
Enable driver support of NXP FlexSPI controller.
Signed-off-by: Yogesh Gaur
---
Changes for v4:
- None
Changes for v3:
- None
Changes for v2:
- None
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index
- Add driver for NXP FlexSPI host controller
(0) What is the FlexSPI controller?
FlexSPI is a flexsible SPI host controller which supports two SPI
channels and up to 4 external devices. Each channel supports
Single/Dual/Quad/Octal mode data transfer (1/2/4/8 bidirectional
data lines) i.e. Flex
Add maintainers for the NXP FlexSPI driver
Signed-off-by: Yogesh Gaur
---
Changes for v4:
- None
Changes for v3:
- None
Changes for v2:
- None
MAINTAINERS | 6 ++
1 file changed, 6 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 9d5eeff..2696898 100644
--- a/MAINTAINERS
+++ b/MA
- Add driver for NXP FlexSPI host controller
FlexSPI is a flexsible SPI host controller [1], Chapter 30 page 1475,
which supports two SPI channels and up to 4 external devices.
Each channel supports Single/Dual/Quad/Octal mode data transfer (1/2/4/8
bidirectional data lines)
i.e. FlexSPI acts
Add fspi node property for LX2160A SoC for FlexSPI driver.
Property added for the FlexSPI controller and for the connected
slave device for the LX2160ARDB target.
This is having two SPI-NOR flash device, mt35xu512aba, connected
at CS0 and CS1.
Signed-off-by: Yogesh Gaur
---
Changes for v4:
- None
Grammar and indentation fixes.
Signed-off-by: Geert Uytterhoeven
---
include/linux/reset.h | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/include/linux/reset.h b/include/linux/reset.h
index 29af6d6b2f4b8103..d01ea059e2beee6e 100644
--- a/include/linux/reset.h
+++ b/i
Signed-off-by: Geert Uytterhoeven
---
include/linux/interrupt.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/linux/interrupt.h b/include/linux/interrupt.h
index eeceac3376fc83ec..1d6711c282715a59 100644
--- a/include/linux/interrupt.h
+++ b/include/linux/interrupt.h
Hi Boris,
> -Original Message-
> From: Boris Brezillon [mailto:boris.brezil...@bootlin.com]
> Sent: Saturday, September 29, 2018 9:10 PM
> To: Yogesh Narayan Gaur
> Cc: linux-...@lists.infradead.org; marek.va...@gmail.com; linux-
> s...@vger.kernel.org; devicet...@vger.kernel.org; r...@ke
tree: https://git.kernel.org/pub/scm/linux/kernel/git/paulmck/linux-rcu.git
dev.2018.10.03a
head: ef44a26c8418f97e5d7b3f8e4f8c0decd248
commit: 813f47a94e3b61439bba90340b532f3a6319d4f5 [44/73] rcu: Print per-CPU
callback counts for forward-progress failures
config: x86_64-randconfig-x006-1
On Sat, Oct 6, 2018 at 9:36 PM Laurent Vivier wrote:
> This patch allows to have a different binfmt_misc configuration
> for each new user namespace. By default, the binfmt_misc configuration
> is the one of the previous level, but if the binfmt_misc filesystem is
> mounted in the new namespace a
On 06/10/2018 22:43, Guenter Roeck wrote:
>>
Maybe this works as well? I haven't tested it yet:
>>> I am sure there are many possible solutions. I would personally
>>> prefer one
>>> that enforces KVM_AMD=m with CRYPTO_DEV_CCP_DD=m, but that is just me.
>>
>> Well, KVM_AMD=y is a relativ
On 6 October 2018 at 15:39, Steven Rostedt wrote:
> On Sat, 6 Oct 2018 14:12:11 +0200
> Peter Zijlstra wrote:
>
>> On Fri, Oct 05, 2018 at 09:51:11PM -0400, Steven Rostedt wrote:
>> > +#define arch_dynfunc_trampoline(name, def) \
>> > + asm volatile ( \
>> > + ".globl
[...]
> +Host controller node:
> +
> + sdhci1: sdhci@0 {
> + compatible = "ti,am654-sdhci-5.1";
> + reg = <0x0 0x1000>;
> + power-domains = <&k3_pds 48>;
> +
On 4 October 2018 at 13:14, Faiz Abbas wrote:
> Add driver support for the MMC physical layer present
> on TI's AM654 devices.
>
> Signed-off-by: Faiz Abbas
> Signed-off-by: Sekhar Nori
I assume Kishon would like to pick up this through his tree? If not,
please tell and I can do it, with his ac
Randy Dunlap writes:
> Hi,
> one small typo/spello below...
>
>> +If the protocol name is omitted, the STM class will chose whichever
>
> s/chose/choose/
Aw shucks, me can has spelling good. Do you mind if I fix it in later
rcs?
Thanks,
--
Alex
On 27.9.2018 11:24, Michal Vokáč wrote:
> The reset signal of the SSD1306 OLED display is actually active-low.
> Adapt the DT to reflect the real world.
>
> Signed-off-by: Michal Vokáč
> ---
> v2 changes: New patch in the series
Bartlomiej just queued the first two patches for v4.20.
Will somebo
Hi,
On 08.10.2018 13:55, Jiri Olsa wrote:
> On Mon, Oct 08, 2018 at 09:19:17AM +0300, Alexey Budankov wrote:
>> +#ifdef HAVE_AIO_SUPPORT
>> +if (!strcmp(var, "record.aio-cblocks"))
>> +rec->opts.nr_cblocks = strtol(value, NULL, 0);
>> +#endif
>>
>> return 0;
>> }
>> @@ -18
On 27 September 2018 at 16:07, Anand Moon wrote:
> This is series v4 since my previous patches were incomplete with driver
> changes missing.
>
> v5 changes.
> drop the cd-gpios wp-gpio gpio pin setting, just add the pinctrl
> configration to support write protect.
>
> v4 changes.
> squash cd-gpio
On 29 September 2018 at 04:29, Chaotian Jing wrote:
> On MT2712 MSDC0/3, HCLK/bus-clk need gate/ungate together,
> or will hang when access MSDC register.
>
> Signed-off-by: Chaotian Jing
Applied for next, thanks!
Kind regards
Uffe
> ---
> Documentation/devicetree/bindings/mmc/mtk-sd.txt | 1
On 29 September 2018 at 04:29, Chaotian Jing wrote:
> when gate MSDC0_HCLK, access register will hang, even the MSDC driver
> will never accessing register after HCLK was gated, but for safety, need
> gate the bus_clk(which used to access register) too.
>
> Signed-off-by: Chaotian Jing
Applied f
"Alharthi, Mansour A" writes:
> Hello all,
Hi,
> Assume this test code:
>
> thread_start(){
> ...
> test();
> ...
> }
>
> test(){
> printf("test");
> }
>
> main(){
> ...
> pthread_create(.., thread_start,);
> }
Can you include the complete test case code?
> Tracing the above program w
Hi,
On 08.10.2018 13:50, Jiri Olsa wrote:
> On Mon, Oct 08, 2018 at 09:14:29AM +0300, Alexey Budankov wrote:
>>
>> diff --git a/tools/perf/Makefile.config b/tools/perf/Makefile.config
>> index f6d1a03c7523..2e90f4ce9214 100644
>> --- a/tools/perf/Makefile.config
>> +++ b/tools/perf/Makefile.confi
From: Yue Wang
The Amlogic Meson PCIe host controller is based on the Synopsys DesignWare
PCI core. This patch adds documentation for the DT bindings in Meson PCIe
controller.
Signed-off-by: Yue Wang
Signed-off-by: Hanjie Lin
Reviewed-by: Rob Herring
---
.../devicetree/bindings/pci/amlogic,m
The Amlogic Meson PCIe host controller is based on the Synopsys DesignWare
PCI core. This patchset add the driver and dt-bindings of the controller.
Changes since v3: [2]
- modify subject format
- update Kconfig
- update MAINTAINER file
- add comment and error handle for meson_pcie_get_mem_sha
From: Yue Wang
The Amlogic Meson PCIe host controller is based on the Synopsys DesignWare
PCI core. This patch adds the driver support for Meson PCIe controller.
Signed-off-by: Yue Wang
Signed-off-by: Hanjie Lin
---
MAINTAINERS| 7 +
drivers/pci/controller/dwc/Kc
Fix english spelling in of_alias_get_alias_list().
Reported-by: Geert Uytterhoeven
Reported-by: Randy Dunlap
Fixes: b1078c355d76 ("of: base: Introduce of_alias_get_alias_list() to check
alias IDs")
Signed-off-by: Michal Simek
---
Changes in v2:
- Fix 2 more issues reported by Randy Dunlap
- A
On Sun, Oct 07, 2018 at 04:35:14AM -0700, Josh Triplett wrote:
> On Sun, Oct 07, 2018 at 10:51:02AM +0200, Geert Uytterhoeven wrote:
> > Providing an explicit list of discrimination factors may give the false
> > impression that discrimination based on other unlisted factors would be
> > allowed.
> On 8 Oct 2018, at 13:59, Wanpeng Li wrote:
>
> On Mon, 8 Oct 2018 at 05:02, Liran Alon wrote:
>>
>>
>>
>>> On 28 Sep 2018, at 9:12, Wanpeng Li wrote:
>>>
>>> From: Wanpeng Li
>>>
>>> In cloud environment, lapic_timer_advance_ns is needed to be tuned for
>>> every CPU
>>> generations
Hi,
On 08.10.2018 13:51, Jiri Olsa wrote:
> On Mon, Oct 08, 2018 at 09:14:29AM +0300, Alexey Budankov wrote:
>
> could you please separate those in struct, maybe anonymous like:
>
> ...
> struct {
> void *data;
> struct aiocb cblock;
>
Hi,
On 08.10.2018 13:50, Jiri Olsa wrote:
> On Mon, Oct 08, 2018 at 09:14:29AM +0300, Alexey Budankov wrote:
>>
>> +#ifdef HAVE_AIO_SUPPORT
>> +static void perf_mmap__aio_munmap(struct perf_mmap *map)
>> +{
>> +if (map->data)
>> +zfree(&map->data);
>> +}
>
> if we really need t
From: Ludovic Barre
All variants don't pretend to have a startbiterr.
-While data error check, if status register return an error
(like MCI_DATACRCFAIL) we must avoid to check MCI_STARTBITERR
(if not desired).
-expand start_err to MCI_IRQENABLE to avoid to set this bit by default.
Signed-off-by
From: Ludovic Barre
This patch adds stm32 sdmmc specific registers.
Signed-off-by: Ludovic Barre
---
drivers/mmc/host/mmci.h | 56 +
1 file changed, 56 insertions(+)
diff --git a/drivers/mmc/host/mmci.h b/drivers/mmc/host/mmci.h
index a962cfa..e
From: Ludovic Barre
The goal of this serie is to add support of sdmmc for stm32.
Be to able to add this new variant it is needed to do some changes in
mmci core:
-Internalize specific needs of legacy dmaengine.
-Create and setup dma_priv pointer.
-Create generic callbacks which share some feature
--
Greetings,
I am Mrs. Nadesh aging widow of 64 years old suffering from long time
illness.I have some funds I inherited from my late husband, the sum of
($15,500,000.00 Million Dollars) and I needed a very honest and God
fearing who can withdraw this money this funds use it for Charity wo
From: Ludovic Barre
-Introduces dma_priv pointer to define specific
needs for each dma engine. This patch is needed to prepare
sdmmc variant with internal dma which not use dmaengine API.
-Moves next cookie to mmci host structure to share same cookie
management between all variants.
Signed-off-b
From: Ludovic Barre
This patch adds dma_start callback to mmci_host_ops.
Create a generic mmci_dma_start function which regroup
common action between variant.
Signed-off-by: Ludovic Barre
---
drivers/mmc/host/mmci.c | 69 +++-
drivers/mmc/host/mmci.
From: Ludovic Barre
This patch adds set_clkreg and set_pwrreg callbacks
at mmci_host_ops to allow to call specific variant.
extends visibility of mmci_write_clk/pwrreg functions
to be used into specific file variant.
Signed-off-by: Ludovic Barre
---
drivers/mmc/host/mmci.c | 16 ---
From: Ludovic Barre
This patch adds prepare/unprepare callbacks to mmci_host_ops.
Like this mmci_pre/post_request can be generic, mmci_prepare_data
and mmci_unprepare_data provide common next_cookie management.
Signed-off-by: Ludovic Barre
---
drivers/mmc/host/mmci.c | 101 +++
From: Ludovic Barre
This patch allows to define a datactrl block size
by variant, requested by STM32 sdmmc variant.
Signed-off-by: Ludovic Barre
---
drivers/mmc/host/mmci.c | 13 +++--
drivers/mmc/host/mmci.h | 2 ++
2 files changed, 13 insertions(+), 2 deletions(-)
diff --git a/driv
From: Ludovic Barre
This patch adds get_next_data callback to mmci_host_ops.
Generic mmci_get_next_data factorizes next_cookie check and
the host ops call.
Signed-off-by: Ludovic Barre
---
drivers/mmc/host/mmci.c | 16 ++--
drivers/mmc/host/mmci.h | 2 ++
drivers
From: Ludovic Barre
This patch adds a stm32 sdmmc variant, rev 1.1.
Introduces a new Manufacturer id "0x53, ascii 'S' to define
new stm32 sdmmc family with clean range of amba
revision/configurations bits (corresponding to sdmmc_ver
register with major/minor fields).
Add 2 variants properties:
-d
From: Ludovic Barre
This patch adds validate_data callback at mmci_host_ops
to check specific constraints of variant.
Move mmci_validate_data function to regroup mmci_host_ops interfaces.
Signed-off-by: Ludovic Barre
---
drivers/mmc/host/mmci.c | 39 +--
dri
From: Ludovic Barre
This patch adds command variant properties to define
cpsm enable bit and responses.
Needed to support the STM32 variant (shift of cpsm bit,
specific definition of commands response).
Signed-off-by: Ludovic Barre
---
drivers/mmc/host/mmci.c | 47 +
From: Ludovic Barre
This patch adds dma_error callback at mmci_host_ops
to allow to call specific variant.
Signed-off-by: Ludovic Barre
---
drivers/mmc/host/mmci.c | 26 +++---
drivers/mmc/host/mmci.h | 2 ++
drivers/mmc/host/mmci_qcom_dml.c | 1 +
3 fil
From: Ludovic Barre
This patch adds a boolean property to not read datacnt register.
Needed to support the STM32 sdmmc variant. MMCIDATACNT
register should be read only after the data transfer is completed.
When reading after an error event the read data count value may be
different from the real
From: Ludovic Barre
This patch adds datactrl variant property to define
dpsm enable bit. Needed to support the STM32 variant
(STM32 has no dpsm enable bit).
Signed-off-by: Ludovic Barre
---
drivers/mmc/host/mmci.c | 15 ---
drivers/mmc/host/mmci.h | 2 ++
2 files changed, 14 inser
From: Ludovic Barre
This patch adds properties for stm32 sdmmc variant.
Signed-off-by: Ludovic Barre
Acked-by: Rob Herring
---
Documentation/devicetree/bindings/mmc/mmci.txt | 10 ++
1 file changed, 10 insertions(+)
diff --git a/Documentation/devicetree/bindings/mmc/mmci.txt
b/Docum
From: Ludovic Barre
This patch adds a optional reset management.
Signed-off-by: Ludovic Barre
Acked-by: Rob Herring
---
Documentation/devicetree/bindings/mmc/mmci.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/mmc/mmci.txt
b/Documentation/devicetree
From: Ludovic Barre
This patch allows to define specific pio mask for variants.
Needed to support the STM32 sdmmc variant which has some bits
with different meaning (bits: 21,20,13,12,9)
Signed-off-by: Ludovic Barre
---
drivers/mmc/host/mmci.c | 13 +++--
drivers/mmc/host/mmci.h | 5 +
From: Ludovic Barre
This patch adds a optional reset management.
STM32 sdmmc variant needs to reset hardware block
during the power cycle procedure (for re-initialization).
Signed-off-by: Ludovic Barre
---
drivers/mmc/host/mmci.c | 7 +++
drivers/mmc/host/mmci.h | 2 ++
2 files changed, 9
From: Ludovic Barre
This patch adds dma_finalize callback at mmci_host_ops
to allow to call specific variant.
Signed-off-by: Ludovic Barre
---
drivers/mmc/host/mmci.c | 19 ---
drivers/mmc/host/mmci.h | 3 ++-
drivers/mmc/host/mmci_qcom_dml.c | 1 +
3 files
From: Ludovic Barre
This patch adds a boolean property to allow to write datactrl
before to send command, whatever the command type (read or write).
Needed to support the STM32 sdmmc variant.
Signed-off-by: Ludovic Barre
---
drivers/mmc/host/mmci.c | 6 --
drivers/mmc/host/mmci.h | 2 ++
2
From: Ludovic Barre
This patch creates a common mmci_dma_setup/release which calls
dma_setup/release callbacks of mmci_host_ops and manages
common features like use_dma... If there is a fallbacks to
pio mode, dma functions must check use_dma.
error management:
-mmci_dmae_setup fail if Tx and Rx
From: Ludovic Barre
The STM32 sdmmc variant has a different clock divider.
Signed-off-by: Ludovic Barre
---
drivers/mmc/host/mmci.c | 2 ++
drivers/mmc/host/mmci.h | 2 ++
2 files changed, 4 insertions(+)
diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c
index d636a0e..ad2f62f 10
From: Ludovic Barre
This patch merges the prepare data functions.
This allows to define a single access to prepare data service.
This prepares integration for mmci host ops.
Signed-off-by: Ludovic Barre
---
drivers/mmc/host/mmci.c | 19 +++
1 file changed, 7 insertions(+), 12 d
Hi,
On 08.10.2018 13:57, Jiri Olsa wrote:
> On Mon, Oct 08, 2018 at 09:17:11AM +0300, Alexey Budankov wrote:
>
> SNIP
>
>> static int record__mmap_read_evlist(struct record *rec, struct perf_evlist
>> *evlist,
>> bool overwrite)
>> {
>> @@ -520,7 +644,10 @@ st
Notice that in this particular case, I replaced the
"--v-- fall through --v--" comment with a proper
"fall through", which is what GCC is expecting to
find.
This fix is part of the ongoing efforts to enabling
-Wimplicit-fallthrough
Signed-off-by: Gustavo A. R. Silva
---
drivers/isdn/gigaset/iso
Aliases >= MAX_UART_INSTANCES is no problem to find out and use but in
error path is necessary skip clearing bits in bitmap to ensure that only
bits in allocated bitmap are handled and nothing beyond that.
Without this patch when for example serial90 alias is used then in error
patch bit 90 is clea
Hi,
On 08.10.2018 13:50, Jiri Olsa wrote:
> On Mon, Oct 08, 2018 at 09:17:11AM +0300, Alexey Budankov wrote:
>
> SNIP
>
>> -
>> +#ifdef HAVE_AIO_SUPPORT
>> +lseek(trace_fd, off, SEEK_SET);
>> +#endif
>> /*
>> * Mark the round finished in case we wrote
>> * at least one event
Hello my dear.
Did you receive my email message to you? Please, get back to me ASAP as the
matter is becoming late. Expecting your urgent response.
Sean.
Check compatible string first before setting up bit in bitmap to also
cover cases that allocated bitfield is not big enough.
Show warning about it but let driver to continue to work with allocated
bitfield to keep at least some devices (included console which
is commonly close to serial0) to work.
Hi,
On 08.10.2018 13:51, Jiri Olsa wrote:
> On Mon, Oct 08, 2018 at 09:17:11AM +0300, Alexey Budankov wrote:
>
> SNIP
>
>> struct option;
>> diff --git a/tools/perf/util/mmap.c b/tools/perf/util/mmap.c
>> index db8f16f8a363..ecaa5b5eb3ed 100644
>> --- a/tools/perf/util/mmap.c
>> +++ b/tools/per
Hi Geert,
On 27.9.2018 09:22, Michal Simek wrote:
> On 27.9.2018 09:19, Geert Uytterhoeven wrote:
>> Hi Michal,
>>
>> On Wed, Sep 26, 2018 at 1:01 PM Michal Simek wrote:
>>> On 24.9.2018 09:41, Geert Uytterhoeven wrote:
On Thu, Sep 20, 2018 at 1:42 PM Michal Simek
wrote:
> The fun
Dear All,
> The NXP's Vybryd vf610 can work as a SPI slave device (the CS and
> clock signals are provided by master).
>
> It is possible to specify a single device to work in that mode. As we
> do use DMA for transferring data, the RX channel must be prepared for
> incoming data.
> Moreover, in
On Mon, 8 Oct 2018 09:40:09 +0200
Ricardo Ribalda Delgado wrote:
> Hi Boris
> On Fri, Oct 5, 2018 at 9:32 PM Boris Brezillon
> wrote:
> >
> > On Fri, 5 Oct 2018 20:12:43 +0200
> > Ricardo Ribalda Delgado wrote:
> >
> > >
> > > I think I know what might be the issue. on cfi_cmdset_002.c
> > >
Hi,
On 08.10.2018 13:52, Jiri Olsa wrote:
> On Mon, Oct 08, 2018 at 09:17:11AM +0300, Alexey Budankov wrote:
>> +#ifdef HAVE_AIO_SUPPORT
>> +off = lseek(trace_fd, 0, SEEK_CUR);
>> +#endif
>
> I'm still little puzzled why we need to do this,
> when the aio write takes the offset value, but
p
Pavel
On 10/07/2018 08:46 AM, Pavel Machek wrote:
> On Wed 2018-09-26 08:09:21, Dan Murphy wrote:
>> Add the dedicated TI LM3632 LED driver. This
>> LED device is capable of driving a backlight display.
>>
>> In addition to the backlight the device has control
>> of a strobe and torch output.
>
Dear All,
> This commit adds DTS support for BK4 device from Liebherr. It
> uses vf610 SoC from NXP.
>
Gentle ping on this patch...
> Signed-off-by: Lukasz Majewski
> ---
> Changes for v2:
>
> - Rename enet_ext and audio_ext oscillator names
> - Move regulators from simple-bus (and rename to
Hi,
On 08.10.2018 13:58, Jiri Olsa wrote:
> On Mon, Oct 08, 2018 at 09:17:11AM +0300, Alexey Budankov wrote:
>>
>> +#ifdef HAVE_AIO_SUPPORT
>> +off = lseek(trace_fd, 0, SEEK_CUR);
>> +#endif
>> for (i = 0; i < evlist->nr_mmaps; i++) {
>> struct perf_mmap *map = &maps[i];
>
Dear All,
> Add Device Tree binding document for Liebherr's BK4 external SPI bus.
>
Gentle ping...
> Signed-off-by: Lukasz Majewski
> ---
> Documentation/devicetree/bindings/misc/lwn-bk4.txt | 26
> ++ 1 file changed, 26 insertions(+)
> create mode 100644 Documentation/dev
On Mon, 8 Oct 2018 11:21:13 +
Yogesh Narayan Gaur wrote:
> > > +static void nxp_fspi_read_ahb(struct nxp_fspi *f, const struct
> > > +spi_mem_op *op) {
> > > + u32 len = op->data.nbytes;
> > > +
> > > + /* Read out the data directly from the AHB buffer. */
> > > + memcpy_fromio(op->data.buf.i
On Mon, Oct 08, 2018 at 02:55:13PM +0300, Alexey Budankov wrote:
> Hi,
>
> On 08.10.2018 13:50, Jiri Olsa wrote:
> > On Mon, Oct 08, 2018 at 09:14:29AM +0300, Alexey Budankov wrote:
> >>
>
> >> diff --git a/tools/perf/Makefile.config b/tools/perf/Makefile.config
> >> index f6d1a03c7523..2e90f4ce9
On Mon, Oct 08, 2018 at 03:03:18PM +0300, Alexey Budankov wrote:
> Hi,
>
> On 08.10.2018 13:50, Jiri Olsa wrote:
> > On Mon, Oct 08, 2018 at 09:14:29AM +0300, Alexey Budankov wrote:
>
> >>
> >> +#ifdef HAVE_AIO_SUPPORT
> >> +static void perf_mmap__aio_munmap(struct perf_mmap *map)
> >> +{
> >>
On Mon, Oct 08, 2018 at 02:47:13PM +0300, Alexey Budankov wrote:
> Hi,
>
> On 08.10.2018 13:55, Jiri Olsa wrote:
> > On Mon, Oct 08, 2018 at 09:19:17AM +0300, Alexey Budankov wrote:
>
> >> +#ifdef HAVE_AIO_SUPPORT
> >> + if (!strcmp(var, "record.aio-cblocks"))
> >> + rec->opts.nr_cblock
Dear All,
This patchset is an attempt to submit the last piece of missing code
to have proper support for Exynos5433 SoCs based TM2(e) boards. It
performs a cleanup of timer configuration, which so far needed various
out-of-tree workarounds. The fixes provided by this patchset are also
needed for
Exynos MCT driver is required even if ARM Architected Timer driver
is used to properly configure common timer hardware.
Signed-off-by: Marek Szyprowski
---
arch/arm64/Kconfig.platforms | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
TM2(e) boards use old firmware, which some PCSI requirements and doesn't
properly configure arch virtual timers, so add property indicating this
state. This enables respective workarounds in the timer driver.
Signed-off-by: Marek Szyprowski
---
arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dt
Move ARM architected timer device-tree node to the beginning of 'soc'
node, to group it together with other ARM CPU core devices (like PMU).
Signed-off-by: Marek Szyprowski
---
arch/arm64/boot/dts/exynos/exynos5433.dtsi | 23 +++---
1 file changed, 12 insertions(+), 11 deletions(
Exynos Multi-Core Timer driver is used only on device-tree based
systems, so remove non-dt related code.
Signed-off-by: Marek Szyprowski
---
drivers/clocksource/exynos_mct.c | 4
1 file changed, 4 deletions(-)
diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_mct.c
To get ARM Architected Timers working on Samsung Exynos SoCs, one has to
first configure and enable Exynos Multi-Core Timer, because they both
share some common hardware blocks. This patch adds a mode of cooperation
with arch_timer driver, so kernel can use CP15 based timer interface via
arch_timer
Exynos Multi-Core Timer driver (exynos_mct) must be started before
ARM Architected Timers (arch_timer), because both timers share common
hardware block and turning on MCT is needed to get ARM Architected
Timer working properly.
Signed-off-by: Marek Szyprowski
---
include/linux/cpuhotplug.h | 2 +
Use common infrastructure for ARM Architected Timers erratum to enable
support for systems with broken CPU firmware (timer registers not
properly configured). This mode has been already availabled on ARM
(32bits) architecture. This enables to run Linux kernel on ARM64 boards
using physical architec
On Fri, Oct 5, 2018 at 9:30 PM Li Yang wrote:
>
>
> NXP/FSL SoC drivers updates for v4.20 take 2
>
> - Update qbman driver to better work with CPU hotplug
> - Add Kconfig dependency of 64-bit DMA addressing for qbman driver
> - Use l
On Mon, Oct 08, 2018 at 03:24:31PM +0300, Alexey Budankov wrote:
> Hi,
>
> On 08.10.2018 13:52, Jiri Olsa wrote:
> > On Mon, Oct 08, 2018 at 09:17:11AM +0300, Alexey Budankov wrote:
>
> >> +#ifdef HAVE_AIO_SUPPORT
> >> + off = lseek(trace_fd, 0, SEEK_CUR);
> >> +#endif
> >
> > I'm still little
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