As a step towards ensuring the atomic* APIs are consistent, let's switch
to wrappers generated by gen-atomic-long.h, using the same table that
gen-atomic-fallbacks.h uses to fill in gaps in the atomic_* and
atomic64_* APIs.
These are checked in rather than generated with Kbuild, since:
* This all
As a step towards ensuring the atomic* APIs are consistent, let's switch
to wrappers generated by gen-atomic-instrumented.h, using the same table
used to generate the fallbacks and atomic-long wrappers.
These are checked in rather than generated with Kbuild, since:
* This allows inspection of the
Hi Ingo,
As previously requested, this is a (trivial) rebase of the remaining generated
atomic patches atop of v4.19-rc2, avoiding any potential conflict with Peter's
ldsem atomic cleanup patch that got taken through the tty tree.
Are you still happy to pick this up? Full blurb below.
This serie
On Tue, 2018-09-04 at 13:42 +0800, 焦晓冬 wrote:
> Hi,
>
> After reading several writeback error handling articles from LWN, I
> begin to be upset about writeback error handling.
>
> Jlayton's patch is simple but wonderful idea towards correct error
> reporting. It seems one crucial thing is still h
On 09/04/2018 12:38 PM, Hans Holmberg wrote:
From: Hans Holmberg
On 1.2-devices, the mapping-out of remaning sectors in the
failed-write's block can result in an infinite loop,
stalling the write pipeline, fix this.
Fixes: 6a3abf5beef6 ("lightnvm: pblk: rework write error recovery path")
Sign
The function dot11d_init() was previously renamed to clear a style
issue. Unfortunately the new name used, dot11d_init(), clashes with
a sybmol which is exported with the same name. To correct this
problem the function has been renamed to rtl8192u_dot11d_init().
Signed-off-by: John Whitmore
---
Not sure of the procedure having made a mess of the build, (by reusing the name
of an exported symbol). I hope that given the obscurity of rtl1892u this doesn't
cause people issues. Obviously given the fact that I renamed an exported symbol
I should have checked the name. Newbie mistake, I can only
On Monday 20 Aug 2018 at 10:44:19 (+0100), Quentin Perret wrote:
> Energy Aware Scheduling (EAS) is designed with the assumption that
> frequencies of CPUs follow their utilization value. When using a CPUFreq
> governor other than schedutil, the chances of this assumption being true
> are small, if
This patch adds one new led trigger that LED device can configure
the software or hardware pattern and trigger it.
Consumers can write 'pattern' file to enable the software pattern
which alters the brightness for the specified duration with one
software timer.
Moreover consumers can write 'hw_pat
This patch implements the 'pattern_set'and 'pattern_clear'
interfaces to support SC27XX LED breathing mode.
Signed-off-by: Baolin Wang
---
Changes from v7:
- Add its own ABI documentation file.
Changes from v6:
- None.
Changes from v5:
- None.
Changes from v4:
- None.
Changes from v3:
-
On Sat, Aug 18, 2018 at 03:16:21PM +0200, Rasmus Villemoes wrote:
> It's not clear what's so horrible about emitting a function call to
> handle a run-time sized bitmap. Moreover, gcc also emits a function call
> for a compile-time-constant-but-huge nbits, so the comment isn't even
> accurate.
>
>
On Tue, 2018-09-04 at 16:58 +0800, 焦晓冬 wrote:
> On Tue, Sep 4, 2018 at 3:53 PM Rogier Wolff wrote:
>
> ...
> > >
> > > Jlayton's patch is simple but wonderful idea towards correct error
> > > reporting. It seems one crucial thing is still here to be fixed. Does
> > > anyone have some idea?
> > >
On Mon, Sep 03, 2018 at 06:01:26PM +0300, Andy Shevchenko wrote:
> On Mon, Aug 27, 2018 at 9:58 PM Jarkko Sakkinen
> wrote:
> >
> > Add wrappers for Intel(R) SGX ENCLS opcode leaf functions except
> > ENCLS(EINIT). ENCLS invokes privileged functions for managing (creation,
> > initialization and s
Remove unnecessary parentheses from conditionals.
Also clears 'Alignment should match open parenthesis'
checkpatch issue.
Signed-off-by: Michael Straube
---
drivers/staging/rtl8188eu/core/rtw_led.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/staging/rtl818
Remove empty if statement from 'if - else if' and replace the
else if with if. Remove the now unused variable pmlmepriv.
Also clears line over 80 characters and CamelCase checkpatch
issues.
Signed-off-by: Michael Straube
---
drivers/staging/rtl8188eu/core/rtw_led.c | 5 +
1 file changed, 1 i
From: Radu Pirea
This is the driver for at91-usart in spi mode. The USART IP can be configured
to work in many modes and one of them is SPI.
The driver was tested on sama5d3-xplained and sama5d4-xplained boards with
enc28j60 ethernet controller as slave.
Signed-off-by: Radu Pirea
Reviewed-by:
From: Radu Pirea
This mfd driver is just a wrapper over atmel_serial driver and
spi-at91-usart driver. Selection of one of the drivers is based on a
property from device tree. If the property is not specified, the default
driver is atmel_serial.
Signed-off-by: Radu Pirea
Reviewed-by: Andy Shevc
From: Radu Pirea
Added entry for at91 usart mfd driver.
Signed-off-by: Radu Pirea
Acked-by: Nicolas Ferre
---
MAINTAINERS | 7 +++
1 file changed, 7 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 8aeaa2cc3e14..1bb477aab33b 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -9363,6
From: Radu Pirea
Added entry for at91 usart mfd driver.
Signed-off-by: Radu Pirea
Acked-by: Nicolas Ferre
Acked-for-MFD-by: Lee Jones
---
MAINTAINERS | 9 +
1 file changed, 9 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 544cac829cf4..8aeaa2cc3e14 100644
--- a/MAINTAINE
From: Radu Pirea
This patch modifies the place where resources and device tree properties
are searched.
Signed-off-by: Radu Pirea
Reviewed-by: Andy Shevchenko
Acked-by: Richard Genoud
Acked-by: Nicolas Ferre
Acked-by: Greg Kroah-Hartman
---
drivers/tty/serial/Kconfig| 1 +
drivers
Hi,
Well, this is the 12th version of this patch series.
In this version I fixed a warning from kbuild-robot and I have no idea
how I forgot to add static in declaration of that functions. Also I
fixed the example for the SPI driver in bindings.
Currently I am not working for Microchip, but I wil
From: Radu Pirea
This patch moves the bindings for serial from serial/atmel-usart.txt to
mfd/atmel-usart.txt and adds bindings for USART in SPI mode.
Signed-off-by: Radu Pirea
Reviewed-by: Rob Herring
Acked-for-MFD-by: Lee Jones
Acked-by: Nicolas Ferre
---
.../bindings/{serial => mfd}/atmel
To prevent warning "kernfs: can not remove '(null)', no directory", if an
overlay isn't applied to the active devicetree.
Using of_remove_property and than of_add_property don't show the warning.
---
drivers/of/kobj.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/of
Hello,
This series allows the ipu3-cio2 driver to properly expose a subset of the
media graph even if some drivers for the pending subdevices fail to probe.
Currently the driver exposes a non-functional graph since the pad links are
created and the subdev dev nodes are registered in the v4l2 asyn
On Tue, Sep 04, 2018 at 02:08:59PM +0300, Yury Norov wrote:
> On Sat, Aug 18, 2018 at 03:16:21PM +0200, Rasmus Villemoes wrote:
> > It's not clear what's so horrible about emitting a function call to
> > handle a run-time sized bitmap. Moreover, gcc also emits a function call
> > for a compile-time
On 2018-09-04 13:30, Andy Shevchenko wrote:
> On Tue, Sep 04, 2018 at 02:08:59PM +0300, Yury Norov wrote:
>> On Sat, Aug 18, 2018 at 03:16:21PM +0200, Rasmus Villemoes wrote:
>>> It's not clear what's so horrible about emitting a function call to
>>> handle a run-time sized bitmap. Moreover, gcc al
The inner workings of the mmu_gather-based TLB invalidation mechanism
are not relevant to nommu configurations, so guard them with an #ifdef.
This allows us to implement future functions using static inlines
without breaking the build.
Acked-by: Nicholas Piggin
Acked-by: Peter Zijlstra (Intel)
S
From: Peter Zijlstra
Some architectures require different TLB invalidation instructions
depending on whether it is only the last-level of page table being
changed, or whether there are also changes to the intermediate
(directory) entries higher up the tree.
Add a new bit to the flags bitfield in
Hi all,
This series builds on the core changes I previously posted here:
rfc:
http://lists.infradead.org/pipermail/linux-arm-kernel/2018-August/597821.html
v1:
http://lists.infradead.org/pipermail/linux-arm-kernel/2018-August/598919.html
The main changes are:
* Move the mmu_gather bi
We recently had to debug a TLB invalidation problem on the munmap()
path, which was made more difficult than necessary because:
(a) The MMU gather code had changed without people realising
(b) Many people subtly misunderstood the operation of the MMU gather
code and its interactions with
From: Peter Zijlstra
In preparation for maintaining the mmu_gather code as its own entity,
move the implementation out of memory.c and into its own file.
Cc: "Kirill A. Shutemov"
Cc: Andrew Morton
Cc: Michal Hocko
Signed-off-by: Peter Zijlstra
---
include/asm-generic/tlb.h | 1 +
mm/Makef
It is common for architectures with hugepage support to require only a
single TLB invalidation operation per hugepage during unmap(), rather than
iterating through the mapping at a PAGE_SIZE increment. Currently,
however, the level in the page table where the unmap() operation occurs
is not stored
From: Sunil Goutham
Scan all RVU blocks to find any 'LF to RVU PF/VF' mapping done by
low level firmware. If found any, mark them as used in respective
block's LF bitmap and also save mapped PF/VF's PF_FUNC info.
This is done to avoid reattaching a block LF to a different RVU PF/VF.
Signed-off-
From: Sunil Goutham
This patch adds basic template for Marvell OcteonTX2's
resource virtualization unit (RVU) admin function (AF)
driver. Just the driver registration and probe.
Signed-off-by: Sunil Goutham
---
drivers/soc/Kconfig| 1 +
drivers/soc/Makefile
From: Sunil Goutham
This patch gathers NPA/NIX/SSO/SSOW/TIM/CPT RVU blocks's
HW info like number of LFs. Important register offsets
saved for later use to avoid code duplication for each block.
A bitmap is allocated for each of the blocks which later
on will be used to allocate a LF for a RVU PF/
From: Sunil Goutham
Resource virtualization unit (RVU) on Marvell's OcteonTX2 SOC supports
multiple PCIe SRIOV physical functions (PFs) and virtual functions (VFs).
PF0 is called administrative / admin function (AF) and has privilege access
to registers to provision different RVU functional block
From: Aleksey Makarov
With 10's of mailbox messages expected to be handled in future,
checking for message id could become a lengthy switch case. Hence
added a macro to auto generate the switch case for each msg id.
Signed-off-by: Aleksey Makarov
---
drivers/soc/marvell/octeontx2/rvu.c | 44 ++
From: Sunil Goutham
Go through all BLKADDRs and check which ones are implemented
on this silicon and do a HW reset of each implemented block.
Also added all RVU AF and PF register offsets.
Signed-off-by: Sunil Goutham
---
drivers/soc/marvell/octeontx2/rvu.c| 78
d
From: Aleksey Makarov
This patch adds mailbox support infrastructure APIs.
Each RVU device has a dedicated 64KB mailbox region
shared with it's peer for communication. RVU AF has
a separate mailbox region shared with each of RVU PFs
and a RVU PF has a separate region shared with each of
it's VF.
From: Sunil Goutham
This patch adds support for mailbox interrupt and message
handling. Mapped mailbox region and registered a workqueue
for message handling. Enabled mailbox IRQ of RVU PFs
and registered a interrupt handler. When IRQ is triggered
work is added to the mbox workqueue for msgs to g
From: Sunil Goutham
Added support for a RVU PF/VF to request AF via mailbox
to attach or detach NPA/NIX/SSO/SSOW/TIM/CPT block LFs.
Also supports partial detachment and modifying current
LF attached count of a certian block type.
Signed-off-by: Sunil Goutham
---
drivers/soc/marvell/octeontx2/m
From: Geetha sowjanya
HW interprets RVU_AF_MSIXTR_BASE address as an IOVA, hence
create a IOMMU mapping for the physcial address configured by
firmware and reconfig RVU_AF_MSIXTR_BASE with IOVA.
Signed-off-by: Geetha sowjanya
Signed-off-by: Sunil Goutham
---
drivers/soc/marvell/octeontx2/rvu.
From: Sunil Goutham
Firmware configures a certain number of MSIX vectors to each of
enabled RVU PF/VF. When a block LF is attached to a PF/VF, number
of MSIX vectors needed by that LF are set aside (out of PF/VF's
total MSIX vectors) and LF's msix_offset is configured in HW.
Also added support f
From: Sunil Goutham
This patch adds basic template for Marvell OcteonTX2's
CGX ethernet interface driver. Just the probe.
RVU AF driver will use APIs exported by this driver
for various things like PF to physical interface mapping,
loopback mode, interface stats etc. Hence marged both
drivers int
From: Linu Cherian
CGX LMAC initialization, link status polling etc is done
by low level secure firmware. For link management this patch
adds a interface or communication mechanism between firmware
and this kernel CGX driver.
- Firmware interface specification is defined in cgx_fw_if.h.
- Suppor
On Fri, Aug 31, 2018 at 11:36 AM Benjamin Tissoires
wrote:
>
> This partially reverts commit f07b3c1da92db108662f99417a212fc1eddc44d1.
>
> It looks like some mice are not correctly treated by
> HID_QUIRK_INPUT_PER_APP. Those mice have the following
> report descriptor:
>
> 0x05, 0x01,
From: Sunil Goutham
Added maintainers entry for Marvell OcteonTX2 SOC's RVU
admin function driver.
Signed-off-by: Sunil Goutham
---
MAINTAINERS | 10 ++
1 file changed, 10 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index e178f2b..38f874c 100644
--- a/MAINTAINERS
+++ b/MAINTA
From: Linu Cherian
Each of the enabled CGX LMAC is considered a physical
interface and RVU PFs are mapped to these. VFs of these
SRIOV PFs will be virtual interfaces and share CGX LMAC
along with PF.
This mapping info will be used later on for Rx/Tx pkt steering.
Signed-off-by: Linu Cherian
Si
From: Linu Cherian
Added support in RVU AF driver to register for
CGX LMAC link status change events from firmware
and managing them. Processing part will be added
in followup patches.
- Introduced eventqueue for posting events from cgx lmac.
Queueing mechanism will ensure that events can be p
The map->data buffers are used to preserve map->base profiling data
for writing to disk. AIO map->cblocks are used to queue corresponding
map->data buffers for asynchronous writing. map->cblocks objects are
located in the last page of every map->data buffer.
Signed-off-by: Alexey Budankov
--
record__aio_sync() allocates index of free map->data buffer for
a cpu buffer or blocks till completion of any started operation
and then proceeds.
Trace file offset is calculated and updated linearly prior
enqueuing aio write at record__pushfn().
record__mmap_read_sync() implements a barrier
On 9/4/2018 12:03 PM, Neeraj Upadhyay wrote:
If takedown_cpu() fails during _cpu_down(), st->state is reset,
by calling cpuhp_reset_state(). This results in an additional
increment of st->state, which results in CPUHP_AP_SMPBOOT_THREADS
state being skipped during rollback. Fix this by not call
On 04/09/2018 11:49:22+0200, Linus Walleij wrote:
> This driver depends on the deleted AT91 architecture and cause
> me headaches from a GPIO point of view. It is unused so delete
> it.
>
While AVR32 is gone, AT91 is alive and well.
Also, get_maintainers is correct (for once):
Nicolas Ferre (s
On Tue, 21 Aug 2018, Bin Yang wrote:
>
> +static inline bool
> +overlap(unsigned long start1, unsigned long end1,
> + unsigned long start2, unsigned long end2)
> +{
> + /* Is 'start2' within area 1? */
> + if (start1 <= start2 && end1 > start2)
> + return true;
> +
On 09/03/2018 04:26 AM, Shawn Guo wrote:
> Add Sébastien for a cross check.
>
> Shawn
>
> On Thu, Aug 30, 2018 at 01:20:05PM +0800, Anson Huang wrote:
>> Update i.MX6ULL iomux header according to latest reference
>> manual Rev.1, 11/2017.
>>
>> Signed-off-by: Anson Huang
Reviewed-by: Sébastien
As we augmented the regulator core to accept a GPIO descriptor instead
of a GPIO number, we can augment the fixed GPIO regulator to look up
and pass that descriptor directly from device tree or board GPIO
descriptor look up tables.
Some boards just auto-enumerate their fixed regulator platform dev
On Tue, Sep 4, 2018 at 2:15 PM Alexandre Belloni
wrote:
> On 04/09/2018 11:49:22+0200, Linus Walleij wrote:
>
> > This driver depends on the deleted AT91 architecture and cause
> > me headaches from a GPIO point of view. It is unused so delete
> > it.
> >
>
> While AVR32 is gone, AT91 is alive and
Hi Yogesh,
On Fri, 31 Aug 2018 15:59:57 +0530
Yogesh Gaur wrote:
> - Add a driver for NXP FlexSPI host controller
>
> FlexSPI is a flexsible SPI host controller [1], Chapter 30 page 1475,
> which supports two SPI channels and up to 4 external devices.
> Each channel supports Single/Dual/Quad
On 2018/9/4 16:02, Borislav Petkov wrote:
shows only old mails so I'm going to assume this got fixed, finally! And
you probably have received a *fixed* BIOS even, allegedly.
So what's up?
I tested the function on Hygon Dhyana platforms with the latest BIOS,
found that this problem is indeed fi
On Tue, Sep 04, 2018 at 05:24:35PM +0530, sunil.kovv...@gmail.com wrote:
> From: Sunil Goutham
>
> Resource virtualization unit (RVU) on Marvell's OcteonTX2 SOC supports
> multiple PCIe SRIOV physical functions (PFs) and virtual functions (VFs).
> PF0 is called administrative / admin function (AF
Instead of directly calling RISC-V timer interrupt handler from
RISC-V local interrupt conntroller driver, this patch implements
RISC-V timer interrupt as a per-CPU interrupt using per-CPU APIs
of Linux IRQ subsystem.
Signed-off-by: Anup Patel
---
arch/riscv/include/asm/irq.h | 2 -
driver
The scause is already part of pt_regs so no need to pass
scause as separate arg to do_IRQ().
Signed-off-by: Anup Patel
---
arch/riscv/kernel/entry.S | 1 -
arch/riscv/kernel/irq.c | 4 ++--
2 files changed, 2 insertions(+), 3 deletions(-)
diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/ke
This patchset provides a new RISC-V Local Interrupt Controller Driver
for managing per-CPU local interrupts. The overall approach is inspired
from the way per-CPU local interrupts are handled by Linux ARM64 and
ARM GICv3 driver.
Few advantages of having this new driver are as follows:
1. It regist
The mechanism to trigger IPI is generally part of interrupt-controller
driver for various architectures. On RISC-V, we have an option to trigger
IPI using SBI or SOC vendor can implement RISC-V CPU where IPI will be
triggered using SOC interrupt-controller (e.g. custom PLIC).
This patch makes IPI
This patch selects following GENERIC_IRQ kconfig options:
GENERIC_IRQ_MULTI_HANDLER
GENERIC_IRQ_PROBE
GENERIC_IRQ_SHOW_LEVEL
HANDLE_DOMAIN_IRQ
Signed-off-by: Anup Patel
---
arch/riscv/Kconfig | 4
1 file changed, 4 insertions(+)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index a3
The RISC-V local interrupt controller manages software interrupts,
timer interrupts, external interrupts (which are routed via the
platform level interrupt controller) and per-HART local interrupts.
This patch add a driver for RISC-V local interrupt controller. It's
a major re-write over perviousl
On Mon, 3 Sep 2018 09:54:08 +
Prabhakar Kushwaha wrote:
> Dear Yogesh,
>
> > -Original Message-
> > From: linux-kernel-ow...@vger.kernel.org > ow...@vger.kernel.org> On Behalf Of Yogesh Gaur
> > Sent: Friday, August 31, 2018 4:00 PM
> > To: linux-...@lists.infradead.org; boris.bre
Hi Stephen,
On Tue, 4 Sep 2018 09:19:50 +1000, Stephen Rothwell wrote:
> Today's linux-next merge of the dmi tree got a conflict in:
>
> drivers/acpi/bus.c
>
> between commit:
>
> ae976358cd7b ("Revert "ACPI / bus: Parse tables as term_list for Dell XPS
> 9570 and Precision M5530"")
>
> f
On Mon, Aug 27, 2018 at 04:44:44PM +0200, Ulf Hansson wrote:
> On 27 August 2018 at 10:21, Johan Hovold wrote:
> > Use the new of_get_compatible_child() helper to lookup the slot child
> > node instead of using of_find_compatible_node(), which searches the
> > entire tree from a given start node a
Calling dmi_check_system() early only works on X86. Other
architectures initialize the DMI subsystem later so it's not
ready yet when ACPI itself gets initialized.
In the best case it results in a useless call to a function which
will do nothing. But depending on the dmi implementation, it could
a
On Thu, Aug 30, 2018 at 05:47:33PM -0700, Florian Fainelli wrote:
> On 08/27/2018 01:21 AM, Johan Hovold wrote:
> > Use the new of_get_compatible_child() helper to lookup the mdio child
> > node instead of using of_find_compatible_node(), which searches the
> > entire tree from a given start node a
Hi all,
On Mon, Aug 27, 2018 at 10:21:44AM +0200, Johan Hovold wrote:
> Several drivers currently use of_find_compatible_node() to lookup child
> nodes while failing to notice that the of_find_ functions search the
> entire tree depth-first (from a given start node) and therefore can
> match unrel
On Tue, Aug 28, 2018 at 12:11:13PM -0700, Andrey Smirnov wrote:
> On Tue, Aug 28, 2018 at 3:58 AM Abel Vesa wrote:
> >
> > On Fri, Aug 24, 2018 at 09:40:11AM +0200, Sascha Hauer wrote:
> > > +Cc Andrey Smirnov who made me aware of this issue.
> > >
> > > On Wed, Aug 22, 2018 at 04:48:21PM +0300, A
> -Original Message-
> From: Borislav Petkov
> Sent: Tuesday, September 4, 2018 1:29 AM
> To: Fan Wu
> Cc: mche...@kernel.org; james.mo...@arm.com; baicar.ty...@gmail.com;
> linux-e...@vger.kernel.org; linux-kernel@vger.kernel.org; linux-arm-
> ker...@lists.infradead.org; john.ga...@hu
On Tue, Aug 28, 2018 at 04:05:11PM +0100, Punit Agrawal wrote:
> Hi Bjorn,
>
> As discussed before[0], here are a couple of patches to drop
> node-local allocations during host contoller initialisation. This set
> covers both arm64 and x86.
>
> I'm posting early to give the patches time on the li
For platforms whose firmwares provide valid module handles
(SMBIOS type 17) in error records, this patch uses the module
handles to locate corresponding DIMMs and enables per-DIMM
error counter update.
Signed-off-by: Fan Wu
Reviewed-by: Tyler Baicar
Tested-by: Toshi Kani
---
Changes from v3:
*
Hi Jiri,
there is no real link between those 4 commit but the fact that I wrote
them today ;)
2 patches should at least be scheduled for v4.19: 1/4 and 3/4
Both are stable fixes for mistakes I made in v4.18.
Patch 2 and 4 are just nice to have, so v4.20 should be fine.
Cheers,
Benjamin
Benjami
commit f07b3c1da92d ("HID: generic: create one input report per
application type") was effectively the same as MULTI_INPUT:
hidinput->report was never set, so hidinput_match_application()
always returned null.
Fix that by testing against the real application.
Note that this breaks some old eGalax
Or it creates some weird input names like:
"MI Dongle MI Wireless Mouse Mouse"
Signed-off-by: Benjamin Tissoires
---
drivers/hid/hid-input.c | 14 ++
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/drivers/hid/hid-input.c b/drivers/hid/hid-input.c
index ac201817a2dd..1
When implementing commit 7f81c8db5489 ("HID: multitouch: simplify
the settings of the various features"), I wrongly removed a test
that made sure we never try to set the second InputMode feature
to something else than 0.
This broke badly some recent Elan panels that now forget to send the
click bu
Now that the application is simply stored in struct hid_input, we can
overwrite it in mt_input_mapping() for the faulty egalax and have a
simpler suffix processing in mt_input_configured()
Signed-off-by: Benjamin Tissoires
---
drivers/hid/hid-multitouch.c | 72 ---
On 03-09-18, 13:34, Srinivas Kandagatla wrote:
> This patch adds board specific bindings required for dais, In particular
> for compressed dais and dai direction.
>
> Board specific setup involves setting up some of dais as compressed dais
> and also specify direction of any dai. Some of the dais
On 2018/9/4 18:48, Borislav Petkov wrote:
On Wed, Aug 29, 2018 at 08:43:54PM +0800, Pu Wen wrote:
Hygon PMU arch is similar to AMD Family 17h. To support Hygon PMU, the
initialization flow for it just call amd_pmu_init() and change PMU name
That sentence reads funny.
Will rewrite this senten
On Tue, Sep 4, 2018 at 1:55 PM Benjamin Tissoires
wrote:
>
> On Fri, Aug 31, 2018 at 11:36 AM Benjamin Tissoires
> wrote:
> >
> > This partially reverts commit f07b3c1da92db108662f99417a212fc1eddc44d1.
> >
> > It looks like some mice are not correctly treated by
> > HID_QUIRK_INPUT_PER_APP. Those
On 09/02/2018 11:54 PM, Shawn Guo wrote:
> On Fri, Aug 31, 2018 at 02:17:31PM -0500, Andrew F. Davis wrote:
>> The correct DT property for specifying a GPIO used for reset
>> is "reset-gpios", fix this here.
>>
>> Fixes: d763762e3b58 ("ARM: dts: imx6: add ZII RDU2 boards")
>
> This Fixes tag and w
On 15:22-20180903, Kishon Vijay Abraham I wrote:
> AM65 has two PCIe controllers and each PCIe controller has '2' address
> spaces one within the 4GB address space of the SoC and the other above
> the 4GB address space of the SoC (cbass_main) in addition to the
> register space. The size of the ad
Em Tue, Sep 04, 2018 at 09:10:49AM +0200, Peter Zijlstra escreveu:
> On Mon, Sep 03, 2018 at 07:45:48PM -0700, Stephane Eranian wrote:
> > A few weeks ago, you had asked if I had more requests for the perf tool.
> I have one long standing one; that is IP based data structure
> annotation.
> Whe
On Mon, Sep 03, 2018 at 11:33:05AM +0200, Peter Zijlstra wrote:
> On Mon, Sep 03, 2018 at 10:54:23AM +0200, Peter Zijlstra wrote:
> > On Mon, Sep 03, 2018 at 09:38:15AM +0200, Thomas Gleixner wrote:
> > > On Mon, 3 Sep 2018, Peter Zijlstra wrote:
> > > > On Sat, Sep 01, 2018 at 11:51:26AM +0930, Ke
Hi,
On 28/08/18 14:53, Patrick Bellasi wrote:
> The number of clamp groups supported is limited and defined at compile
> time. However, a malicious user can currently ask for many different
Even if not malicious.. :-)
> clamp values thus consuming all the available clamp groups.
>
> Since on pr
On Fri, Aug 10, 2018 at 09:09:40PM +0530, Bharat Kumar Gogada wrote:
> Add nwl_setup_service_irqs hook to setup_platform_service_irq IRQs to
> register platform provided IRQ number to kernel AER service.
>
> Signed-off-by: Bharat Kumar Gogada
> ---
> drivers/pci/controller/pcie-xilinx-nwl.c |
On Tue, Sep 04, 2018 at 10:42:18AM -0300, Arnaldo Carvalho de Melo wrote:
> So, use 'c2c record' to get the samples:
IIRC that uses numa events and is completely useless.
On 03-09-18, 13:34, Srinivas Kandagatla wrote:
> +static void compress_event_handler(uint32_t opcode, uint32_t token,
> +uint32_t *payload, void *priv)
> +{
> + struct q6asm_dai_rtd *prtd = priv;
> + struct snd_compr_stream *substream = prtd->cstream;
> +
On 09/03/2018 06:26 AM, Mark Brown wrote:
> On Fri, Aug 31, 2018 at 01:05:07PM -0500, Andrew F. Davis wrote:
>> Leaving microphone bias off is a valid setting and even used in the DT
>> binding document example. Add this setting here and document the same.
>> Although it may not make much sense to
On Tue, Sep 04, 2018 at 03:53:25PM +0200, Peter Zijlstra wrote:
> On Tue, Sep 04, 2018 at 10:42:18AM -0300, Arnaldo Carvalho de Melo wrote:
> > So, use 'c2c record' to get the samples:
>
> IIRC that uses numa events and is completely useless.
I guess perf record on any other event would work
in A
On 4 Sep 2018, at 4:01, Kirill A. Shutemov wrote:
> On Tue, Sep 04, 2018 at 03:55:10PM +0800, Peter Xu wrote:
>> When splitting a huge page, we should set all small pages as dirty if
>> the original huge page has the dirty bit set before. Otherwise we'll
>> lose the original dirty bit.
>
> We don
On Mon, Sep 03, 2018 at 07:56:54AM +0200, Michal Hocko wrote:
> On Thu 30-08-18 14:39:44, Jerome Glisse wrote:
> > On Thu, Aug 30, 2018 at 11:05:16AM -0700, Mike Kravetz wrote:
> > > On 08/30/2018 09:57 AM, Jerome Glisse wrote:
> > > > On Thu, Aug 30, 2018 at 06:19:52PM +0200, Michal Hocko wrote:
>
On Wed, Aug 29, 2018 at 08:44:07PM +0800, Pu Wen wrote:
> The ideal_nops for Dhyana processors should be p6_nops.
>
> Signed-off-by: Pu Wen
> ---
> arch/x86/kernel/alternative.c | 4
> 1 file changed, 4 insertions(+)
>
> diff --git a/arch/x86/kernel/alternative.c b/arch/x86/kernel/alternat
Hi!
Any other comment before I resubmit v2 tomorrow from
https://github.com/ribalda/linux/tree/gpio-addr-flash-v2
So far the diff for v2 I have
>From Boris Brezillon:
-Add Fixes and cc:stable
>From kbuild:
- Fix warnings
- Rebase
Thanks!
On Tue, Aug 21, 2018 at 4:31 PM Ricardo Ribalda Delga
Access to GICR_WAKER is restricted on msm8996 SoC in Hypervisor.
Its been more than 2 years of wait for this to be fixed, which has
no hopes to be fixed. This change was introduced for the "lead device"
on msm8996 platform. It looks like all publicly available msm8996
devices have this implementati
Em Tue, Sep 04, 2018 at 03:58:35PM +0200, Jiri Olsa escreveu:
> On Tue, Sep 04, 2018 at 03:53:25PM +0200, Peter Zijlstra wrote:
> > On Tue, Sep 04, 2018 at 10:42:18AM -0300, Arnaldo Carvalho de Melo wrote:
> > > So, use 'c2c record' to get the samples:
> > IIRC that uses numa events and is complet
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