On Tue, Jun 12, 2018 at 02:44:29PM +0200, Daniel Lezcano wrote:
> On 12/06/2018 14:30, Peter Zijlstra wrote:
> > On Tue, Jun 12, 2018 at 02:00:11PM +0200, Daniel Lezcano wrote:
> >> +static void __idle_injection_wakeup(struct idle_injection_device *ii_dev)
> >> +{
> >> + struct idle_injection_thre
On Tue, Jun 12, 2018 at 12:29:50PM +0200, Ulf Hansson wrote:
> On 12 June 2018 at 10:42, Feng Tang wrote:
> > Hi Ulf,
> >
> > Thanks for the review.
> >
> > On Tue, Jun 12, 2018 at 08:25:44AM +0200, Ulf Hansson wrote:
> >> On 8 June 2018 at 11:51, Feng Tang wrote:
> >> > When doing some boot time
On Tue, Jun 12, 2018 at 02:00:11PM +0200, Daniel Lezcano wrote:
> +struct idle_injection_device {
remove this:
> + cpumask_var_t cpumask;
> + struct hrtimer timer;
> + struct completion stop_complete;
> + unsigned int idle_duration_ms;
> + unsigned int run_duration_ms;
> +
On 12/06/2018 14:52, Peter Zijlstra wrote:
> On Tue, Jun 12, 2018 at 02:44:29PM +0200, Daniel Lezcano wrote:
>> On 12/06/2018 14:30, Peter Zijlstra wrote:
>>> On Tue, Jun 12, 2018 at 02:00:11PM +0200, Daniel Lezcano wrote:
+static void __idle_injection_wakeup(struct idle_injection_device *ii_d
On Tue, Jun 12, 2018 at 08:05:25PM +0800, Shawn Lin wrote:
> On 2018/6/12 18:29, Ulf Hansson wrote:
> > On 12 June 2018 at 10:42, Feng Tang wrote:
> > > Hi Ulf,
> > >
> > > Thanks for the review.
> > >
> > > On Tue, Jun 12, 2018 at 08:25:44AM +0200, Ulf Hansson wrote:
> > > > On 8 June 2018 at 1
Am Dienstag, 12. Juni 2018, 03:04:34 CEST schrieb Linus Torvalds:
> On Mon, Jun 11, 2018 at 5:02 PM Olof Johansson wrote:
> >
> > - Qualcomm:
> > + SDM845, a.k.a Snapdragon 845, an 4+4-core Kryo 385/845
> > (Cortex-A75/A55 derivative) SoC that's one of the current high-end
> > mobile SoCs.
> >
> >
On Sat, Jun 09, 2018 at 10:34:43PM +0300, Andy Shevchenko wrote:
> On Sat, Jun 9, 2018 at 7:58 PM, wrote:
> > On 2018-06-09 12:38, Anton Vasilyev wrote:
> >>
> >> If rtsx_probe fails to allocate dev->chip, then NULL pointer
> >> dereference occurs at rtsx_release_resources().
> >>
> >> Patch adds
Hi Marc
thanks for the review.
On 2018/6/9 20:40, Marc Zyngier wrote:
> On Fri, 08 Jun 2018 20:48:40 +0100,
> Dongjiu Geng wrote:
>>
>> For the migrating VMs, user space may need to know the exception
>> state. For example, in the machine A, KVM make an SError pending,
>> when migrate to B, KVM
On Wed, Jun 6, 2018 at 11:18 AM, Keerthy wrote:
> Currently IRQ resource fetching is done at the very end of probe.
> In case the of IRQ resource not being ready, we defer probe
> and need to revert prior changes. Hence move it to the beginning of
> the probe so as to avoid reverting.
>
> Signed-
On 06/11/2018 10:04 PM, Mathieu Desnoyers wrote:
- On Jun 11, 2018, at 3:55 PM, Florian Weimer fwei...@redhat.com wrote:
On 06/11/2018 09:49 PM, Mathieu Desnoyers wrote:
It should be noted that there can be only one rseq TLS area registered per
thread,
which can then be used by many librar
From: Ludovic Barre
This patch allows to define specific pio mask for variants.
Needed to support the STM32 sdmmc variant which has some bits
with different meaning (bits: 21,20,13,12,9)
Signed-off-by: Ludovic Barre
---
drivers/mmc/host/mmci.c | 13 +++--
drivers/mmc/host/mmci.h | 5 +
From: Ludovic Barre
All variants don't pretend to have a startbiterr.
-While data error check, if status register return an error
(like MCI_DATACRCFAIL) we must avoid to check MCI_STARTBITERR
(if not desired).
-expand start_err to MCI_IRQENABLE to avoid to set this bit by default.
Signed-off-by
From: Ludovic Barre
This patch adds stm32 sdmmc specific registers.
Signed-off-by: Ludovic Barre
---
drivers/mmc/host/mmci.h | 56 +
1 file changed, 56 insertions(+)
diff --git a/drivers/mmc/host/mmci.h b/drivers/mmc/host/mmci.h
index 227927e..c
From: Ludovic Barre
This patch adds specific clock and power ios for stm32 sdmmc variant.
power ios: stm32 dedicated procedure must be done to perform power
off/on procedures. To power off, the sdmmc must be reset and set
to power cycle state before to disabling vqmmc. This drives low
SDMMC_D[7:0
From: Ludovic Barre
A specific variant could have different power or clock procedures.
This patch allows to overwrite the default mmci_set_clkreg and
mmci_set_pwrreg for a specific variant.
Signed-off-by: Ludovic Barre
---
drivers/mmc/host/mmci.c | 96 +-
From: Ludovic Barre
This patch adds a boolean property to read remaining data.
Needed to support the STM32 sdmmc variant. MMCIDATACNT
register should be read only after the data transfer is complete.
When reading after an error event the read data count value may be
different from the real number
From: Ludovic Barre
This patch adds support of Internal DMA (IDMA) for
STM32 sdmmc variant. Direct memory access (DMA) is used to provide
high-speed transfer between the SDMMC FIFO and the memory.
The SDMMC internal DMA (IDMA) provides one channel to be used either
for transmit or receive.
The I
From: Ludovic Barre
The STM32 sdmmc variant has a different clock divider.
Signed-off-by: Ludovic Barre
---
drivers/mmc/host/mmci.c | 2 ++
drivers/mmc/host/mmci.h | 2 ++
2 files changed, 4 insertions(+)
diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c
index 9af7db8..e24fd1e 10
From: Ludovic Barre
This patch adds a stm32 sdmmc variant, rev 1.1.
Introduces a new Manufacturer id "0x53, ascii 'S' to define
new stm32 sdmmc familly with clean range of amba
revision/configurations bits (corresponding to sdmmc_ver
register with major/minor fields).
Signed-off-by: Ludovic Barr
From: Ludovic Barre
STM32 sdmmc variant has support to:
-Indicate signal directions (only one property
for d0dir, d123dir, cmd_dir)
-Select command and data phase relation.
-Select "clock in" from an external driver.
Signed-off-by: Ludovic Barre
---
Documentation/devicetree/bindings/mmc/mmci.t
From: Ludovic Barre
This patch adds a boolean property to allow to write datactrl
before to send command, whatever the command type (read or write).
Needed to support the STM32 sdmmc variant.
Signed-off-by: Ludovic Barre
---
drivers/mmc/host/mmci.c | 6 --
drivers/mmc/host/mmci.h | 2 ++
2
From: Ludovic Barre
This patch adds a function pointer to check specific data constraint
follow hardware variant. Needed to support the STM32 sdmmc variant
which has alignment constraint.
Signed-off-by: Ludovic Barre
---
drivers/mmc/host/mmci.c | 5 +
drivers/mmc/host/mmci.h | 2 ++
2 file
From: Ludovic Barre
Some variants could require a reset.
STM32 sdmmc variant needs to reset hardware block
during the power cycle procedure (for re-initialization)
Signed-off-by: Ludovic Barre
---
Documentation/devicetree/bindings/mmc/mmci.txt | 2 ++
drivers/mmc/host/mmci.c
From: Ludovic Barre
The mmc framework follows the requirement of SD_Specification:
the STOP_TRANSMISSION is sent on multiple write/read commands
and the stop command (alone), not needed on other ADTC commands.
But, some variants require a stop command "STOP_TRANSMISION" to clear
the DPSM "Data P
From: Ludovic Barre
This patch integrates qcom dml feature into mmci_dma file.
Qualcomm Data Mover lite/local is already a variant of mmci dmaengine.
Signed-off-by: Ludovic Barre
---
drivers/mmc/host/Makefile| 1 -
drivers/mmc/host/mmci.c | 1 -
drivers/mmc/host/mmci.h
From: Ludovic Barre
This patch adds datactrl variant property to define
dpsm enable bit. Needed to support the STM32 variant
(STM32 has no dpsm enable bit).
Signed-off-by: Ludovic Barre
---
drivers/mmc/host/mmci.c | 15 ---
drivers/mmc/host/mmci.h | 2 ++
2 files changed, 14 inser
From: Ludovic Barre
This patch series adapts mmci driver to add support for stm32
sdmmc variant. stm32h7 SoC integrates the first revision of
stm32 sdmmc.
This series is composed of 3 parts:
-Prepare mmci driver to manage dma interfaces by adding property.
New mmci dma API is defined according
From: Ludovic Barre
Prepare mmci driver to manage dma interface by new property.
This patch defines and regroups dma operations for mmci drivers.
mmci_dma_XX prototypes are added to call member of mmci_dma_ops
if not null. Based on legacy need, a mmci dma interface has been
defined with:
-mmci_dm
From: Ludovic Barre
This patch allows to define a datactrl block size
by variant, requested by STM32 sdmmc variant.
Signed-off-by: Ludovic Barre
---
drivers/mmc/host/mmci.c | 13 +++--
drivers/mmc/host/mmci.h | 2 ++
2 files changed, 13 insertions(+), 2 deletions(-)
diff --git a/driv
From: Ludovic Barre
This patch adds command variant properties to define
cpsm enable bit and responses.
Needed to support the STM32 variant (shift of cpsm bit,
specific definition of commands response).
Signed-off-by: Ludovic Barre
---
drivers/mmc/host/mmci.c | 47 +
Add a dummy qcom_scm_assign_mem() to enable building drivers when
CONFIG_COMPILE_TEST=y && CONFIG_QCOM_SCM=n.
All other qcom_scm_* functions already have a dummy version.
Signed-off-by: Niklas Cassel
---
include/linux/qcom_scm.h | 4
1 file changed, 4 insertions(+)
diff --git a/include/li
This commit provides support for HSC and DDC boards from
Kieback&Peter GmbH vendor.
Signed-off-by: Lukasz Majewski
Reviewed-by: Fabio Estevam
---
Changes for v3:
- Add Reviewed-by tag
- The &fec label moved to proper position
- Newline between property list and child node
- Remove not needed bl
Hi Linus,
The following changes since commit 786b71f5b754273ccef6d9462e52062b3e1f9877:
Merge tag 'nds32-for-linus-4.17-fixes' of
git://git.kernel.org/pub/scm/linux/kernel/git/greentime/linux (2018-05-28
05:25:57 -0700)
are available in the Git repository at:
git://git.linux-nfs.org/projec
Hi Shawn,
On Mon, Jun 11, 2018 at 2:26 AM, Shawn Guo wrote:
>> diff --git a/arch/arm/boot/dts/imx51-zii-rdu1.dts
>> b/arch/arm/boot/dts/imx51-zii-rdu1.dts
>> index 0c99ac04ad08..98cc107098e0 100644
>> --- a/arch/arm/boot/dts/imx51-zii-rdu1.dts
>> +++ b/arch/arm/boot/dts/imx51-zii-rdu1.dts
>> @@
On 25/05/18 11:48, Julien Thierry wrote:
On 25/05/18 11:41, Suzuki K Poulose wrote:
On 25/05/18 11:39, Julien Thierry wrote:
On 25/05/18 11:36, Suzuki K Poulose wrote:
On 25/05/18 11:17, Julien Thierry wrote:
On 25/05/18 11:04, Suzuki K Poulose wrote:
On 25/05/18 10:49, Julien Thier
On Mon, May 14, 2018 at 11:12 AM, Dmitry Vyukov wrote:
> On Sun, May 6, 2018 at 10:30 PM, Theodore Y. Ts'o wrote:
>> On Sun, May 06, 2018 at 11:40:10PM +0900, Tetsuo Handa wrote:
>>> > We could add a full kernel-mode fsck which gets run before mount ---
>>> > the question is how much complexity w
Linus,
The following changes since commit 73fcb1a370c76b202d406e95d9dabb76eaccf484:
Merge branch 'akpm' (patches from Andrew) (2018-05-18 21:24:26 -0700)
are available in the git repository at:
git://git.kernel.org/pub/scm/virt/kvm/kvm.git tags/for-linus
for you to fetch changes up to 766
On Tue, Jun 12, 2018 at 03:02:14PM +0200, Daniel Lezcano wrote:
> On 12/06/2018 14:52, Peter Zijlstra wrote:
> > In this case, you can do:
>
> That is what we had before but we change the code to set the count
> before waking up the task, so compute the cpumask_weight of the
> resulting AND right
On 06/12/2018 03:46 AM, Michal Hocko wrote:
> On Mon 11-06-18 12:23:58, Jason Baron wrote:
>> On 06/11/2018 11:03 AM, Michal Hocko wrote:
>>> So can we start discussing whether we want to allow MADV_DONTNEED on
>>> mlocked areas and what downsides it might have? Sure it would turn the
>>> strong
Hi,
On Tue, Jun 12, 2018 at 6:04 AM, Heiko Stuebner wrote:
> Am Dienstag, 12. Juni 2018, 03:04:34 CEST schrieb Linus Torvalds:
>> On Mon, Jun 11, 2018 at 5:02 PM Olof Johansson wrote:
>> >
>> > - Qualcomm:
>> > + SDM845, a.k.a Snapdragon 845, an 4+4-core Kryo 385/845
>> > (Cortex-A75/A55 derivat
On Tue, Jun 12, 2018 at 02:00:11PM +0200, Daniel Lezcano wrote:
> +static void idle_injection_last_man(struct idle_injection_device *ii_dev)
> +{
> + unsigned int run_duration_ms;
> +
> + run_duration_ms = READ_ONCE(ii_dev->run_duration_ms);
> + if (run_duration_ms) {
> + hr
On Tuesday, June 12, 2018 2:44:23 PM CEST Marek Szyprowski wrote:
> Hi Rafael,
Hi,
> On 2018-06-12 13:00, Rafael J. Wysocki wrote:
> > From: Rafael J. Wysocki
> >
> > If a device link is added via device_link_add() by the driver of the
> > link's consumer device, the supplier's runtime PM usage
On Tue, Jun 12, 2018 at 02:00:11PM +0200, Daniel Lezcano wrote:
> +void idle_injection_stop(struct idle_injection_device *ii_dev)
> +{
> + pr_debug("Stopping injecting idle cycles on CPUs '%*pbl'\n",
> + cpumask_pr_args(ii_dev->cpumask));
> +
> + idle_injection_set_duration(ii_
-directional type codes have been defined so they can be used as
inferred values
for the Input and Output terminals for this adapter profile.
--
Based on tag: next-20180612
Jorge Sanjuan (2):
ALSA: usb-audio: Add bi-directional terminal types.
ALSA: usb-audio: UAC3. Add insertion control for
Define the bi-directional USB terminal types for audio devices.
Signed-off-by: Jorge Sanjuan
---
include/uapi/linux/usb/audio.h | 8
1 file changed, 8 insertions(+)
diff --git a/include/uapi/linux/usb/audio.h b/include/uapi/linux/usb/audio.h
index 13d98e6e0db1..74e520fb944f 100644
---
The HEADSET ADAPTER profile for BADD devices is meant to support
Insertion Control for the Input and Output Terminals of the headset.
Furthermore, this profile may also include the interrupt status pipe
to report changes on these terminals.
This patch creates the jack-detect controls for the Heads
Hi Chengguang,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on tip/x86/core]
[also build test ERROR on v4.17 next-20180612]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day-ci/linux
On Tuesday, June 12, 2018 2:42:12 PM CEST Oleksij Rempel wrote:
> This is an OpenPGP/MIME signed message (RFC 4880 and 3156)
> --Sj2PRcQlY7eZybdA0sq9wWzJEO8fKS924
> Content-Type: multipart/mixed; boundary="d6BZYFRi4L3iCmOh3nm6wjii3dWC9QFDg";
> protected-headers="v1"
> From: Oleksij Rempel
> To:
On Tue, Jun 12, 2018 at 07:59:42AM +0300, jackm wrote:
> On Mon, 11 Jun 2018 10:19:18 -0600
> Jason Gunthorpe wrote:
>
> > On Mon, Jun 11, 2018 at 09:19:14AM +0300, jackm wrote:
> > > On Sun, 10 Jun 2018 22:42:03 -0600
> > > Jason Gunthorpe wrote:
> > >
> > > > Er, the spec has nothing to do
On 11/06/2018 18:53, Christophe JAILLET wrote:
> If 'platform_get_resource_byname()' fails, we should release some resources
> before leaving, as already done in the other error handling path of the
> function.
>
> Fixes: acaa3f13b8dd ("drm/meson: Fix potential NULL dereference in
> meson_drv_bin
On 6/12/2018 6:39 PM, Linus Walleij wrote:
On Wed, Jun 6, 2018 at 11:18 AM, Keerthy wrote:
Currently IRQ resource fetching is done at the very end of probe.
In case the of IRQ resource not being ready, we defer probe
and need to revert prior changes. Hence move it to the beginning of
the pr
> On 12 Jun 2018, at 03.30, Matias Bjørling wrote:
>
> For devices that does not specify a limit on its transfer size, the
> get_chk_meta command may send down a single I/O retrieving the full
> chunk metadata table. Resulting in large 2-4MB I/O requests. Instead,
> split up the I/Os to a maximum
On 12/06/2018 16:06, Peter Zijlstra wrote:
> On Tue, Jun 12, 2018 at 03:02:14PM +0200, Daniel Lezcano wrote:
>> On 12/06/2018 14:52, Peter Zijlstra wrote:
>>> In this case, you can do:
>>
>> That is what we had before but we change the code to set the count
>> before waking up the task, so compute
On 6/11/2018 9:01 AM, Konrad Rzeszutek Wilk wrote:
> On Fri, Jun 08, 2018 at 04:30:15PM -0500, Tom Lendacky wrote:
>> On 6/1/2018 9:59 AM, Konrad Rzeszutek Wilk wrote:
>>> Both AMD and Intel can have SPEC CTRL MSR for SSBD.
>>>
>>> However AMD also has two more other ways of doing it - which
>>> ar
Per-KeyID direct mappings require changes into how we find the right
virtual address for a page and virt-to-phys address translations.
Signed-off-by: Kirill A. Shutemov
---
arch/x86/include/asm/mktme.h | 3 +++
arch/x86/include/asm/page_64.h | 2 +-
2 files changed, 4 insertions(+), 1 deletion
Add new config option to enabled/disable Multi-Key Total Memory
Encryption support.
MKTME uses MEMORY_PHYSICAL_PADDING to reserve enough space in per-KeyID
direct mappings for memory hotplug.
Signed-off-by: Kirill A. Shutemov
---
arch/x86/Kconfig | 19 ++-
1 file changed, 18 ins
Kernel need to have a way to access encrypted memory. We are going to
use per-KeyID direct mapping to facilitate the access with minimal
overhead.
Direct mapping for each KeyID will be put next to each other in the
virtual address space. We need to have a way to find boundaries of
direct mapping f
For encrypted memory, we need to allocated pages for a specific
encryption KeyID.
There are two cases when we need to allocate a page for encryption:
- Allocation for an encrypted VMA;
- Allocation for migration of encrypted page;
The first case can be covered within alloc_page_vma().
The se
For MKTME we use per-KeyID direct mappings. This allows kernel to have
access to encrypted memory.
sync_direct_mapping() sync per-KeyID direct mappings with a canonical
one -- KeyID-0.
The function tracks changes in the canonical mapping:
- creating or removing chunks of the translation tree;
-
mktme_nr_keyids holds number of KeyIDs available for MKTME, excluding
KeyID zero which used by TME. MKTME KeyIDs start from 1.
mktme_keyid_shift holds shift of KeyID within physical address.
mktme_keyid_mask holds mask to extract KeyID from physical address.
Signed-off-by: Kirill A. Shutemov
--
We store KeyID in upper bits for vm_page_prot that match position of
KeyID in PTE. vma_keyid() extracts KeyID from vm_page_prot.
VMA is encrypted if KeyID is non-zero. vma_is_encrypted() checks that.
Signed-off-by: Kirill A. Shutemov
---
arch/x86/include/asm/mktme.h | 9 +
arch/x86/mm/
Store KeyID in bits 31:16 of extended page flags. These bits are unused.
We don't yet set KeyID for the page. It will come in the following
patch that implements prep_encrypted_page(). All pages have KeyID-0 for
now.
Signed-off-by: Kirill A. Shutemov
---
arch/x86/include/asm/mktme.h | 6 ++
VMAs with different KeyID do not mix together. Only VMAs with the same
KeyID are compatible.
Signed-off-by: Kirill A. Shutemov
---
include/linux/mm.h | 7 +++
mm/mmap.c | 3 ++-
2 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/include/linux/mm.h b/include/linux/mm.h
ind
Hi,
On Thu, Jun 07, 2018 at 09:56:48AM -0400, Agustin Vega-Frias wrote:
> Selection of these events can be envisioned as indexing them from
> a 3D matrix:
> - the first index selects a Region Event Selection Register (PMRESRx_EL0)
> - the second index selects a group from which only one event at a
Encrypted VMA will have KeyID stored in vma->vm_page_prot. This way we
don't need to do anything special to setup encrypted page table entries
and don't need to reserve space for KeyID in a VMA.
This patch changes _PAGE_CHG_MASK to include KeyID bits. Otherwise they
are going to be stripped from v
Rename the option to CONFIG_MEMORY_PHYSICAL_PADDING. It will be used
not only for KASLR.
Signed-off-by: Kirill A. Shutemov
---
arch/x86/Kconfig| 2 +-
arch/x86/mm/kaslr.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 4992598a
Pages for encrypted VMAs have to be allocated in a special way:
we would need to propagate down not only desired NUMA node but also
whether the page is encrypted.
It complicates not-so-trivial routine of huge page allocation in
khugepaged even more. It also puts more pressure on page allocator:
we
Separate MKTME enumaration from enabling. We need to postpone enabling
until initialization is complete.
The new helper mktme_disable() allows to disable MKTME even if it's
enumerated successfully. MKTME initialization may fail and this
functionallity allows system to boot regardless of the failur
We need to know number of KeyIDs before KALSR is initialized. Number of
KeyIDs would determinate how much address space would be needed for
per-KeyID direct mapping.
KALSR initialization happens before full CPU initizliation is complete.
Move detect_tme() call to early_init_intel().
Signed-off-by
MKTME claims several upper bits of the physical address in a page table
entry to encode KeyID. It effectively shrinks number of bits for
physical address. We should exclude KeyID bits from physical addresses.
For instance, if CPU enumerates 52 physical address bits and number of
bits claimed for K
The hardware/CPU does not enforce coherency between mappings of the same
physical page with different KeyIDs or encryption keys.
We are responsible for cache management.
Flush cache on allocating encrypted page and on returning the page to
the free pool.
prep_encrypted_page() also takes care abou
Multikey Total Memory Encryption (MKTME)[1] is a technology that allows
transparent memory encryption in upcoming Intel platforms. See overview
below.
Here's updated version of my patchset that brings support of MKTME.
Please review and consider applying.
The patchset provides in-kernel infrastru
Pages encrypted with different encryption keys are not subject to KSM
merge. Otherwise it would cross security boundary.
Signed-off-by: Kirill A. Shutemov
---
include/linux/mm.h | 7 +++
mm/ksm.c | 3 +++
2 files changed, 10 insertions(+)
diff --git a/include/linux/mm.h b/include/
On 12/06/2018 16:23, Peter Zijlstra wrote:
> On Tue, Jun 12, 2018 at 02:00:11PM +0200, Daniel Lezcano wrote:
>> +static void idle_injection_last_man(struct idle_injection_device *ii_dev)
>> +{
>> +unsigned int run_duration_ms;
>> +
>> +run_duration_ms = READ_ONCE(ii_dev->run_duration_ms);
>
On 12/06/2018 16:26, Peter Zijlstra wrote:
> On Tue, Jun 12, 2018 at 02:00:11PM +0200, Daniel Lezcano wrote:
>> +void idle_injection_stop(struct idle_injection_device *ii_dev)
>> +{
>> +pr_debug("Stopping injecting idle cycles on CPUs '%*pbl'\n",
>> + cpumask_pr_args(ii_dev->cpumask
On Tue 12-06-18 12:16:04, Zhouyang Jia wrote:
> When kmem_cache_create fails, the lack of error-handling code may
> cause unexpected results.
>
> This patch adds error-handling code after calling kmem_cache_create.
>
> Signed-off-by: Zhouyang Jia
> ---
> fs/notify/dnotify/dnotify.c | 3 +++
> 1
Access to UART0 is disabled by bootloaders. By leaving it enabled by
default would reboot the board.
Disable this for now, this would alteast give a board which boots.
Signed-off-by: Srinivas Kandagatla
---
arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 de
On Sun, 10 Jun 2018, Srinivas Pandruvada wrote:
> From: Even Xu
>
> Current ish driver only register resume/suspend PM callbacks which
> don't support hibernation (suspend to disk). Now use the
> SIMPLE_DEV_PM_OPS() MACRO instead of struct dev_pm_ops directly.
> The suspend and resume functions
Hi James,
thanks for the review.
On 2018/6/11 21:36, James Morse wrote:
> Hi Dongjiu Geng,
>
> Please only put 'RESEND' in the subject if the patch content is identical.
> This patch is not the same as v4.
Yes, it should
>
> On 08/06/18 20:48, Dongjiu Geng wrote:
>> For the migrating VMs, us
GICR_WAKER can be a secured register, check this before accessing it
as its done in power management code.
Without this patch Qualcomm DB820c board crashes.
Signed-off-by: Srinivas Kandagatla
---
drivers/irqchip/irq-gic-v3.c | 14 --
1 file changed, 8 insertions(+), 6 deletions(-)
On Thursday, May 31, 2018 12:59:54 PM CEST Ulf Hansson wrote:
> Changes in v3:
> - Drop patch 1->4 as they have already been applied.
> - Collected tags, for tests and reviews.
> - Minor update to function descriptions in patch 4 (earlier 8) and 5
> (earlier9).
> - Not
Alistair Strachan writes:
> On Mon, Jun 11, 2018 at 6:22 PM Eric W. Biederman
> wrote:
>>
>> Alistair Strachan writes:
>>
>> > In commit e94591d0d90c "proc: Convert proc_mount to use mount_ns"
>> > the parsing of mount parameters for the proc filesystem was broken.
>> >
>> > The SB_KERNMOUNT f
On 12.06.2018 17:39, Kirill A. Shutemov wrote:
> Kernel need to have a way to access encrypted memory. We are going to
> use per-KeyID direct mapping to facilitate the access with minimal
> overhead.
>
> Direct mapping for each KeyID will be put next to each other in the
> virtual address space.
On Monday, June 11, 2018 7:38:27 AM CEST Shawn Guo wrote:
> On Tue, May 22, 2018 at 08:28:51AM +0200, Sébastien Szymanski wrote:
> > Check the max speed supported from the fuses for i.MX6ULL and update the
> > operating points table accordingly.
> >
> > Signed-off-by: Sébastien Szymanski
>
> Ack
On Friday, June 1, 2018 12:21:42 AM CEST Suman Anna wrote:
> Hi Rafael,
>
> This is a repost of the v2 patches Ccing the proper linux-pm list.
> There are no code changes, I have picked up Viresh's acks and
> also added the stable kernel versions the first patch needs to be
> applied to.
>
> rega
On Monday, June 4, 2018 9:11:41 AM CEST Viresh Kumar wrote:
> On 01-06-18, 14:05, Colin King wrote:
> > From: Colin Ian King
> >
> > The function acpi_cpufreq_fast_switch is local to the source and does
> > not need to be in global scope, so make it static.
> >
> > Cleans up sparse warning:
> >
On Wednesday, June 6, 2018 6:09:29 AM CEST Viresh Kumar wrote:
> On 05-06-18, 13:44, Arnd Bergmann wrote:
> > Building the kryo cpufreq driver while QCOM_SMEM is a loadable module
> > results in a link error:
> >
> > drivers/cpufreq/qcom-cpufreq-kryo.o: In function `qcom_cpufreq_kryo_probe':
> > q
On Tuesday, June 5, 2018 11:42:38 PM CEST Srinivas Pandruvada wrote:
> v1 (Compared to RFC/RFT v3)
> - Minor suggestion for intel_pstate for coding
> - Add SKL desktop model used in some Xeons
>
> Tested-by: Giovanni Gherdovich
>
> This series has an overall positive performance impact on IO bot
Tianyu Lan writes:
> Register tlb_remote_flush callback for vmcs when hyperv capability of
> nested guest mapping flush is detected. The interface can help to reduce
> overhead when flush ept table among vcpus for nested VM. The tradition way
> is to send IPIs to all affected vcpus and executes I
On Friday, June 8, 2018 6:04:13 AM CEST Viresh Kumar wrote:
> On 08-06-18, 09:07, Chen Yu wrote:
> > According to current code implementation, detecting the long
> > idle period is done by checking if the interval between two
> > adjacent utilization update handers is long enough. Although
> > this
Michal Hocko writes:
> On Mon 11-06-18 08:43:03, Bjorn Helgaas wrote:
>> On Mon, Jun 11, 2018 at 08:32:10PM +0800, Xie XiuQi wrote:
>> > Hi Michal,
>> >
>> > On 2018/6/11 16:52, Michal Hocko wrote:
>> > > On Mon 11-06-18 11:23:18, Xie XiuQi wrote:
>> > >> Hi Michal,
>> > >>
>> > >> On 2018/6/7 2
On 11.6.2018 14:36, Michal Vokáč wrote:
Ahoj,
To configure individual pad's characteristics on i.MX6 SoC a
fsl,pins = property can be used. Is there any convenient
way to configure the pad group control registers?
The issue is that some bits (DDR_SEL and ODT) in the individual RGMII pad
contro
Tianyu Lan writes:
> Register tlb_remote_flush callback for vmcs when hyperv capability of
> nested guest mapping flush is detected. The interface can help to reduce
> overhead when flush ept table among vcpus for nested VM. The tradition way
> is to send IPIs to all affected vcpus and executes I
On Tue, 12 Jun 2018, Mikulas Patocka wrote:
>
>
> On Tue, 12 Jun 2018, Alan Stern wrote:
>
> > On Tue, 12 Jun 2018, Mikulas Patocka wrote:
> >
> > > I have a single-core machine with usb2 soundcard. When I increase mplayer
> > > priority (to real-time or high non-realtime priority), the sound
On Tue 12-06-18 16:08:03, Punit Agrawal wrote:
> Michal Hocko writes:
[...]
> > Well, the standard way to handle memory less NUMA nodes is to simply
> > fallback to the closest NUMA node. We even have an API for that
> > (numa_mem_id).
>
> CONFIG_HAVE_MEMORYLESS node is not enabled on arm64 which
On Tue, Jun 12, 2018 at 3:55 PM, Srinivas Kandagatla
wrote:
> GICR_WAKER can be a secured register, check this before accessing it
> as its done in power management code.
>
> Without this patch Qualcomm DB820c board crashes.
>
Are you sure this is the one causing the crash ?
As per GIC specifica
On 6/12/18 3:17 AM, Stefan Agner wrote:
> [also added Jens Axboe]
>
> On 12.06.2018 10:27, Boris Brezillon wrote:
>> On Tue, 12 Jun 2018 10:06:42 +0200
>> Stefan Agner wrote:
>>
>>> On 12.06.2018 02:03, Dmitry Osipenko wrote:
On Monday, 11 June 2018 23:52:22 MSK Stefan Agner wrote:
> Add
Hi,
On 06/12/2018 03:10 AM, Wu Hao wrote:
>
> diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
> index ee9c542..4052532 100644
> --- a/drivers/fpga/Kconfig
> +++ b/drivers/fpga/Kconfig
> @@ -130,4 +130,20 @@ config OF_FPGA_REGION
> Support for loading FPGA images by applying a De
Hi,
On 06/12/2018 03:10 AM, Wu Hao wrote:
> From: Zhang Yi
>
> diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
> index 4052532..5faab48 100644
> --- a/drivers/fpga/Kconfig
> +++ b/drivers/fpga/Kconfig
> @@ -146,4 +146,19 @@ config FPGA_DFL
> Gate Array (FPGA) solutions which imp
Hi,
On 06/12/2018 03:10 AM, Wu Hao wrote:
> From: Kang Luwei
>
>
> diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
> index 5faab48..45e9220 100644
> --- a/drivers/fpga/Kconfig
> +++ b/drivers/fpga/Kconfig
> @@ -146,6 +146,16 @@ config FPGA_DFL
> Gate Array (FPGA) solutions whic
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