This adds support for the GPIOs on Cirrus Logic Madera class codecs.
Any pins not used for special functions (see the pinctrl driver) can be
used as general single-bit input or output lines. The number of available
GPIOs varies between codecs.
Note that this is part of a composite MFD for these co
This is the binding description of the pinctrl driver for Cirrus Logic
Madera codecs. The binding uses the generic pinctrl binding so the main
purpose here is to describe the device-specific names for groups and
functions.
Signed-off-by: Richard Fitzgerald
Acked-by: Rob Herring
Acked-by: Linus
On Thu, 2017-08-03 at 12:59:34 UTC, Peter Rosin wrote:
> The sanctioned compatible is "nxp,pca9547".
>
> Signed-off-by: Peter Rosin
Applied to powerpc next, thanks.
https://git.kernel.org/powerpc/c/e4f2419fac381c5a7659834169dbe7
cheers
On Thu, 2018-05-10 at 21:59:18 UTC, =?utf-8?q?Jonathan_Neusch=C3=A4fer?= wrote:
> On the Wii, there is a secondary IRQ controller (hlwd-pic), so
> flipper-pic's match operation should not be hardcoded to return 1.
> In fact, the default matching logic is sufficient, and we can completely
> omit fli
On Tue, 2018-04-10 at 06:34:37 UTC, Christophe Leroy wrote:
> This reverts commit 6ad966d7303b70165228dba1ee8da1a05c10eefe.
>
> That commit was pointless, because csum_add() sums two 32 bits
> values, so the sum is 0x1fffe at the maximum.
> And then when adding upper part (1) and lower part (0
On Fri, 2018-05-18 at 01:18:33 UTC, Finn Thain wrote:
> My powerpc-linux-gnu-gcc v4.4.5 compiler can't build a 32-bit kernel
> any more:
>
> arch/powerpc/lib/sstep.c: In function 'do_popcnt':
> arch/powerpc/lib/sstep.c:1068: error: integer constant is too large for
> 'long' type
> arch/powerpc/li
On Wed, 2018-05-16 at 06:58:57 UTC, Christophe Leroy wrote:
> PMD_PAGE_SIZE() is nowhere used and _PMD_SIZE is only
> used by PMD_PAGE_SIZE().
>
> This patch removes them.
>
> Signed-off-by: Christophe Leroy
Applied to powerpc next, thanks.
https://git.kernel.org/powerpc/c/5279821a6f5ff75d7dce
On Fri, 2018-05-18 at 09:31:17 UTC, Colin King wrote:
> From: Colin Ian King
>
> Trivial fix to spelling mistake in battery_charging array
>
> Signed-off-by: Colin Ian King
Applied to powerpc next, thanks.
https://git.kernel.org/powerpc/c/ba01b058a52abcb0539d94ae976ef1
cheers
On Tue, 2018-04-17 at 17:08:16 UTC, Christophe Leroy wrote:
> Doing the test at exit of the function avoids an unnecessary
> test and branch inside longjmp()
>
> Signed-off-by: Christophe Leroy
Series applied to powerpc next, thanks.
https://git.kernel.org/powerpc/c/24c78586cc6798028205e12c34fe
On Fri, May 18, 2018 at 11:09:51PM +0200, Janusz Krzysztofik wrote:
> Now as the Amstrad Delta board provides GPIO lookup tables, switch from
> GPIO numbers to GPIO descriptors and use the table to locate required
> GPIO pins.
Acked-by: Mark Brown
signature.asc
Description: PGP signature
On Fri, May 18, 2018 at 02:51:54PM -0500, Bjorn Helgaas wrote:
> On Fri, May 04, 2018 at 01:47:33PM +0800, honghui.zh...@mediatek.com wrote:
> > From: Honghui Zhang
> >
> > Using irq_chip solution to setup IRQs in order to consist
> > with IRQ framework.
> >
> > Signed-off-by: Honghui Zhang
> >
Without this patch we cannot turn on the Bluethooth adapter on ASUS
E406MA.
T: Bus=01 Lev=01 Prnt=01 Port=00 Cnt=01 Dev#= 2 Spd=12 MxCh= 0
D: Ver= 1.10 Cls=e0(wlcon) Sub=01 Prot=01 MxPS=64 #Cfgs= 1
P: Vendor=2ff8 ProdID=b011 Rev= 2.00
S: Manufacturer=Realtek
S: Product=802.11n WLAN Adapte
i.MX6SLL has GPIO clock gates in CCM CCGR, need
to enable them before accessing registers, add
optional clock operation for GPIO driver.
Signed-off-by: Anson Huang
---
drivers/gpio/gpio-mxc.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/drivers/gpio/gpio-mxc.c b/drivers/gpi
From: Xiaofei Tan
This patch implements LED feature of directly attached disk
for v3 hw.
In fact, this hw has created an SGPIO component for LED
feature, and we can control LEDs just by internal registers.
Signed-off-by: Xiaofei Tan
Signed-off-by: John Garry
---
drivers/scsi/hisi_sas/hisi_sa
From: Xiang Chen
When issunig a nexus reset for directly attached device,
we want to ignore the PHY down events so libsas will not
deform and reform the port.
In the case that the attached SAS changes for the reset,
libsas will deform and form a port.
For scenario that the PHY does not come up
On 21-May 15:22, Viresh Kumar wrote:
> On 21-05-18, 09:51, Patrick Bellasi wrote:
> > diff --git a/kernel/sched/cpufreq_schedutil.c
> > b/kernel/sched/cpufreq_schedutil.c
> > +static void sugov_iowait_boost(struct sugov_cpu *sg_cpu, u64 time,
> > + unsigned int flags)
> >
From: Xiang Chen
When a SCSI host is registered, the SCSI mid-layer takes
a reference to a module in Scsi_host.hostt.module. In doing
this, we are prevented from removing the driver module for
the host in dangerous scenario, like when a disk is mounted.
Currently there is only one scsi_host_temp
From: Xiaofei Tan
This patch adds an force PHY function for internal ATA command for
v2 hw.
Because there is an SoC bug of v2 hw, and need send an IO through
each PHY of a port to workaround a bug which occurs after a
controller reset.
This force PHY function will be used in the later patch.
S
From: Xiaofei Tan
It is an step of executing task to get free slot. If the step
fails, we will cleanup LLDD resources and should return failure
to upper layer or internal caller to abort task execution of this
time.
But in the current code, the caller of get_free_slot() doesn't
return failure wh
From: Xiaofei Tan
In future scenarios we will want to use the TMF struct
for more task types than SSP.
As such, we can add struct hisi_sas_tmf_task directly into
struct hisi_sas_slot, and this will mean we can remove
the TMF parameters from the task prep functions.
Signed-off-by: Xiaofei Tan
S
The dwc2_get_ls_map() use ttport to reference into the
bitmap if we're on a multi_tt hub. But the bitmaps index
from 0 to (hub->maxchild - 1), while the ttport index from
1 to hub->maxchild. This will cause invalid memory access
when the number of ttport is hub->maxchild.
Without this patch, I can
From: Xiaofei Tan
For v2 hw, STP link from target is rejected after host reset
because of a SoC bug. The STP reject will be terminated after
we have sent IO from each PHY of a port.
This is not an problem before, as we don't need to setup STP
link from target immediately after host reset. But no
This patchset introduces some misc improvements, bugfixes,
and SoC workarounds for the driver, including:
- workaround for v2 hw reset with SATA disks attached
- LED SGPIO support for v3 hw
- Fix for error path in task_prep function
- change slot and disk allocation method to avoid
unknown SoC bu
From: Xiang Chen
Currently we find the lowest available empty bit in the
IPTT bitmap to allocate the IPTT for a command.
To reduce possibility of hitting unknown SoC bugs and
also aid in the debugging of those same bugs, change
the allocation mode.
The next allocation method is to use the next
From: Xiang Chen
When a disk is discovered, it may be in an error state,
or there may be residual commands remaining in the disk.
To ensure any disk is in good state after discovery,
reset via TMF (for SAS disk) or softreset (for a SATA
disk).
Signed-off-by: Xiang Chen
Signed-off-by: Xiaofei T
Hi Rob,
On Fri, May 18, 2018 at 10:35:52AM -0500, Rob Herring wrote:
> On Tue, May 15, 2018 at 06:12:59PM +0100, James Morse wrote:
> > Hi guys,
> >
> > (CC: +RobH, devicetree list)
>
> Thanks.
>
> > On 25/04/18 07:26, AKASHI Takahiro wrote:
> > > Enabling crash dump (kdump) includes
> > > * pr
From: Xiaofei Tan
After the controller is reset, it is possible that the
disks attached still have outstanding IO to complete.
Thus, when the PHYs come back up after controller reset, it
is possible that these IOs complete at some unknown point
later.
We want to ensure that all IOs are complete
From: Xiaofei Tan
We may reset the controller in many scenarios, such as SCSI EH
and HW errors. There should be no IO which returns from target
when SCSI EH is active. But for other scenarios, there may be.
It is not necessary to make such IOs failure.
This patch adds an function of trying to wa
From: Xiang Chen
To reduce possibility of hitting unknown SoC bugs and aid
debugging and test, change allocation mode of device id from
last used device id instead of lowest available index.
Signed-off-by: Xiang Chen
Signed-off-by: John Garry
---
drivers/scsi/hisi_sas/hisi_sas.h | 1 +
d
On 21/05/18 10:27, Sudeep Holla wrote:
>
>
> On 18/05/18 22:50, Andy Shevchenko wrote:
>> On Thu, May 17, 2018 at 6:47 PM, Sudeep Holla wrote:
>>
>>> Is below patch does what you were looking for ?
>>
>> Somewhat.
>> See below for some minors.
>>
>
> Thanks
>
>>> of_property_read_u64 searche
There is much common code and functionality between the
HW versions to set the PHY linkrate.
As such, this patch factors out the common code into
a generic function hisi_sas_phy_set_linkrate().
Signed-off-by: John Garry
---
drivers/scsi/hisi_sas/hisi_sas_main.c | 29 +++
In sparse_init(), two temporary pointer arrays, usemap_map and map_map
are allocated with the size of NR_MEM_SECTIONS. They are used to store
each memory section's usemap and mem map if marked as present. With
the help of these two arrays, continuous memory chunk is allocated for
usemap and memmap
It's used to record how many memory sections are marked as present
during system boot up, and will be used in the later patch.
Signed-off-by: Baoquan He
---
mm/sparse.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/mm/sparse.c b/mm/sparse.c
index 62eef264a7bd..48cf7b7982e2 100644
--
This is v4 post. V3 can be found here:
https://lkml.org/lkml/2018/2/27/928
V1 can be found here:
https://www.spinics.net/lists/linux-mm/msg144486.html
In sparse_init(), two temporary pointer arrays, usemap_map and map_map
are allocated with the size of NR_MEM_SECTIONS. They are used to store
each
It's used to pass the size of map data unit into alloc_usemap_and_memmap,
and is preparation for next patch.
Signed-off-by: Baoquan He
---
mm/sparse.c | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/mm/sparse.c b/mm/sparse.c
index 3d697292be08..4a58f8809542 100644
In sparse_init(), if CONFIG_SPARSEMEM_ALLOC_MEM_MAP_TOGETHER=y, system
will allocate one continuous memory chunk for mem maps on one node and
populate the relevant page tables to map memory section one by one. If
fail to populate for a certain mem section, print warning and its
->section_mem_map wi
On 20.05.2018 10:27, Vladimir Davydov wrote:
> On Fri, May 18, 2018 at 11:42:37AM +0300, Kirill Tkhai wrote:
>> Imagine a big node with many cpus, memory cgroups and containers.
>> Let we have 200 containers, every container has 10 mounts,
>> and 10 cgroups. All container tasks don't touch foreign
of_device_get_match_data calls of_match_device and fails if the latter
fails, so both calls aren't needed.
---
drivers/i2c/muxes/i2c-mux-pca954x.c |7 ++-
drivers/iio/adc/max1363.c |8 ++--
drivers/iio/potentiometer/max5481.c |7 ++-
drivers/iio/potentiometer/mc
Drop call to of_match_device, which is subsumed by the subsequent
call to of_device_get_match_data. The code becomes simpler, and a
temporary variable can be dropped.
The semantic match that makes this change is as follows:
(http://coccinelle.lip6.fr/)
//
@r@
local idexpression match;
identifie
Drop call to of_match_device, which is subsumed by the subsequent
call to of_device_get_match_data. The code becomes simpler, and a
temporary variable can be dropped.
The semantic match that makes this change is as follows:
(http://coccinelle.lip6.fr/)
//
@r@
local idexpression match;
identifie
In Certain QCOM SoCs like apq8096 and msm8996 that have KRYO processors,
the CPU frequency subset and voltage value of each OPP varies
based on the silicon variant in use. Qualcomm Process Voltage Scaling Tables
defines the voltage and frequency value based on the msm-id in SMEM
and speedbin blown
On 18-05-18, 16:50, Daniel Lezcano wrote:
> Initially, the cpu_cooling device for ARM was changed by adding a new
> policy inserting idle cycles. The intel_powerclamp driver does a
> similar action.
>
> Instead of implementing idle injections privately in the cpu_cooling
> device, move the idle in
of_property_read_u64 searches for a property in a device node and read
a 64-bit value from it. Instead of using of_get_property to get the
property and then read 64-bit value using of_read_number, we can
simplify it by using of_property_read_u64.
Cc: Greg Kroah-Hartman
Suggested-by: Andy Shevchen
On 21-05-18, 11:11, Patrick Bellasi wrote:
> On 21-May 15:22, Viresh Kumar wrote:
> > On 21-05-18, 09:51, Patrick Bellasi wrote:
> > > diff --git a/kernel/sched/cpufreq_schedutil.c
> > > b/kernel/sched/cpufreq_schedutil.c
> > > +static void sugov_iowait_boost(struct sugov_cpu *sg_cpu, u64 time,
>
This implements the support for position and pressure for the included
touchscreen support in the SAMA5D2 SOC ADC block.
Two position channels are added and one for pressure.
They can be read in raw format, or through a buffer.
A normal use case is for a consumer driver to register a callback buffe
Hello,
This patch series is a rework of my previous series named:
[PATCH 00/14] iio: triggers: add consumer support
This is the version 6 of the series, and addresses the received feedback
on the v2 series named:
[PATCH v2 00/10] Add support for SAMA5D2 touchscreen
and the v3 series named
[PATCH
Added bindings for generic resistive touchscreen ADC.
Signed-off-by: Eugen Hristev
Reviewed-by: Rob Herring
---
Changes in v5:
- changed property name touchscreen-threshold-pressure to
touchscreen-min-pressure
Changes in v3:
- renamed file and compatible to exclude "generic" keyword
- remove
Preparing the ADC device to connect channel consumer drivers
Signed-off-by: Eugen Hristev
---
arch/arm/boot/dts/sama5d2.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/boot/dts/sama5d2.dtsi b/arch/arm/boot/dts/sama5d2.dtsi
index 61f68e5..f06ba99 100644
--- a/arch/arm/boot/dts
Add new channel type for relative position on a pad.
These type of analog sensor offers the position of a pen
on a touchpad, and is represented as a voltage, which can be
converted to a position on X and Y axis on the pad.
The channel will hand the relative position on the pad in both directions.
Add generic resistive touch device which is connected to ADC block
inside the SAMA5D2 SoC
Signed-off-by: Eugen Hristev
---
Changes in v5:
- renamed touchscreen-threshold-pressure to touchscreen-min-pressure
arch/arm/boot/dts/sama5d2.dtsi | 10 ++
1 file changed, 10 insertions(+)
diff
This adds a generic resistive touchscreen (GRTS) driver, which is based
on an IIO device (an ADC). It must be connected to the channels of an ADC
to receive touch data. Then it will feed the data into the input subsystem
where it registers an input device.
It uses an IIO callback buffer to register
Added defines for channel consumer device-tree binding
Signed-off-by: Eugen Hristev
Reviewed-by: Rob Herring
---
.../devicetree/bindings/iio/adc/at91-sama5d2_adc.txt | 9 +
include/dt-bindings/iio/adc/at91-sama5d2_adc.h | 16
2 files changed, 25 insertion
Add a common touchscreen optional property that will specify
the minimum pressure applied to the screen that is needed
such that the driver will report the touch event.
Signed-off-by: Eugen Hristev
Reviewed-by: Rob Herring
---
Changes in v5:
- Modified property name to touchscreen-min-pressure
Add MAINTAINERS entry for generic resistive touchscreen adc
Signed-off-by: Eugen Hristev
---
Changes in v3:
- Changed source file name
MAINTAINERS | 6 ++
1 file changed, 6 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 3bdc260..ce9720f 100644
--- a/MAINTAINERS
+++ b/MAINTAINE
Hi Ganapat,
Sorry for the delay in replying; I was away most of last week.
On Tue, May 15, 2018 at 04:03:19PM +0530, Ganapatrao Kulkarni wrote:
> On Sat, May 5, 2018 at 12:16 AM, Ganapatrao Kulkarni
> wrote:
> > On Thu, Apr 26, 2018 at 4:29 PM, Mark Rutland wrote:
> >> On Wed, Apr 25, 2018 at
Would have been better if you would have updated the subject as:
[PATCH v10 10/15] cpufreq: Add Kryo CPU scaling driver
On 21-05-18, 13:31, Ilia Lin wrote:
> In Certain QCOM SoCs like apq8096 and msm8996 that have KRYO processors,
> the CPU frequency subset and voltage value of each OPP varies
>
On Mon, May 21, 2018 at 11:37:12AM +0100, Mark Rutland wrote:
> Hi Ganapat,
>
>
> Sorry for the delay in replying; I was away most of last week.
>
> On Tue, May 15, 2018 at 04:03:19PM +0530, Ganapatrao Kulkarni wrote:
> > On Sat, May 5, 2018 at 12:16 AM, Ganapatrao Kulkarni
> > wrote:
> > > On
Hello,
On Mon, May 21, 2018 at 3:27 AM, Masahiro Yamada
wrote:
> Hi.
>
>
> 2018-05-20 19:57 GMT+09:00 Martin Blumenstingl
> :
>> Hi,
>>
>> On Thu, May 10, 2018 at 11:16 AM, Masahiro Yamada
>> wrote:
>> [snip]
>>> I may be missing something, but
>>> one solution might be reset hogging on the
>>>
On 18/05/18 15:57, Robin Murphy wrote:
One more thing now that I've actually looked at the Arm ARM...
On 18/05/18 11:22, Suzuki K Poulose wrote:
[...]
+static inline void armv8pmu_write_event_type(struct perf_event *event)
+{
+ struct hw_perf_event *hwc = &event->hw;
+ int idx = hwc->idx;
On 18-May 11:55, Joel Fernandes (Google.) wrote:
> From: "Joel Fernandes (Google)"
>
> Currently there is a chance of a schedutil cpufreq update request to be
> dropped if there is a pending update request. This pending request can
> be delayed if there is a scheduling delay of the irq_work and t
On Mon, May 21, 2018 at 01:31:30PM +0300, Ilia Lin wrote:
> +#define SILVER_LEAD 0
> +#define GOLD_LEAD2
Okay, two different values here, but "GOLD_LEAD" appears unused.
> + cpu_dev_silver = get_cpu_device(SILVER_LEAD);
> + if (NULL == cpu_dev_silver)
> + return -ENODEV;
Hi Jacopo,
On Monday, 21 May 2018 12:57:05 EEST jacopo mondi wrote:
> On Fri, May 18, 2018 at 06:12:15PM +0300, Laurent Pinchart wrote:
> > On Friday, 18 May 2018 17:47:57 EEST Jacopo Mondi wrote:
> >> Describe CVBS video input through analog video decoder ADV7180
> >> connected to video input int
On Sat, May 05, 2018 at 12:16:13AM +0530, Ganapatrao Kulkarni wrote:
> On Thu, Apr 26, 2018 at 4:29 PM, Mark Rutland wrote:
> > On Wed, Apr 25, 2018 at 02:30:47PM +0530, Ganapatrao Kulkarni wrote:
> >> + *
> >> + * L3 Tile and DMC channel selection is through SMC call
> >> + * SMC call argument
You are right.
cpu_dev_silver != cpu_dev_gold, and I found this with my tests as well.
Thank you.
> -Original Message-
> From: Russell King - ARM Linux
> Sent: Monday, May 21, 2018 13:54
> To: Ilia Lin
> Cc: viresh.ku...@linaro.org; devicet...@vger.kernel.org; linux-
> p...@vger.kernel.o
On Mon, May 21, 2018 at 6:43 AM, Masahiro Yamada
wrote:
> Hi.
>
>
>
> 2018-05-21 0:46 GMT+09:00 Ulf Magnusson :
>
>> s/environments/environment variables/
>
> Will fix.
>
>
>>
>>> +* They will be written out to include/config/auto.conf.cmd
>>> +*/
>>> + env_add(name, value);
Add missing const qualifiers to the termios hw-change helper parameters,
which is used by few USB serial drivers. This specifically allows the
pl2303 driver to use const arguments in one of its helper as well.
Cc: Greg Kroah-Hartman
Cc: Jiri Slaby
Signed-off-by: Johan Hovold
---
Greg, are you
On Mon, May 21, 2018 at 1:06 PM, Ulf Magnusson wrote:
> On Mon, May 21, 2018 at 6:43 AM, Masahiro Yamada
> wrote:
>> Hi.
>>
>>
>>
>> 2018-05-21 0:46 GMT+09:00 Ulf Magnusson :
>>
>>> s/environments/environment variables/
>>
>> Will fix.
>>
>>
>>>
+* They will be written out to include
From: Rafael J. Wysocki
Two comments in pci_target_state() are outdated, as the function
doesn't set the target power state for the device any more, only
finds one for it, so fix them accordingly.
Reported-by: Bjorn Helgaas
Signed-off-by: Rafael J. Wysocki
---
drivers/pci/pci.c |6 ++
From: Rafael J. Wysocki
The message printed by pm_wakeup_pending() on wakeup detection is
not very useful if someone is not interested specifically in
debugging wakeup, so turn it into a pm_debug() one.
Signed-off-by: Rafael J. Wysocki
---
drivers/base/power/wakeup.c |2 +-
1 file changed,
Andi,
I have a K6 regression testing system. I think my K6 is a revision
C, but I probably can get an earlier cpu (with the bug) to test on.
Do you have any specific tests you would want me to do on the affected cpu?
- Matthew Whitehead
Since sampling events are rejected up-front by cci_pmu_event_init(), it
doesn't make much sense to go fiddling with the sampling period later.
This would seem to be just another leftover artefact of the arm_pmu
framwork, and as such can go.
Acked-by: Mark Rutland
Signed-off-by: Robin Murphy
---
On Thu, May 17, 2018 at 7:06 AM, Mark Brown wrote:
> On Mon, May 14, 2018 at 10:06:40AM +0200, Linus Walleij wrote:
>> From: Charles Keepax
>>
>> Rather than unconditionally registering the GPIO lookup table only do so
>> for devices that require it.
>>
>> Signed-off-by: Charles Keepax
>> [Fixed
[v9]
* Addressed comments from Viresh and Russel about the error handling
[v8]
* Reordered the patch series into 4 groups
* Addressed comments from Amit about the comments and commit messages
* Addressed comments from Amit and Viresh about the resourses deallocation
[v7]
* Addressed comments
From: Rajendra Nayak
Allow clk_alpha_pll_configure to be called from loadable
kernel modules.
Signed-off-by: Rajendra Nayak
Signed-off-by: Ilia Lin
---
drivers/clk/qcom/clk-alpha-pll.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-
The driver provides kernel level API for other drivers
to access the MSM8996 L2 cache registers.
Separating the L2 access code from the PMU driver and
making it public to allow other drivers use it.
The accesses must be separated with a single spinlock,
maintained in this driver.
Signed-off-by: Il
The PMUX for each duplex allows for selection of ACD clock source.
The DVM (Dynamic Variation Monitor) will flag an error
when a voltage droop event is detected. This flagged error
enables ACD to provide a div-by-2 clock, sourced from the primary PLL.
The duplex will be provided the divided clock
u
The CPU clock controller's primary PLL operates on a single VCO range,
between 600MHz and 3GHz. However the CPUs do support OPPs with
frequencies between 300MHz and 600MHz. In order to support running the
CPUs at those frequencies we end up having to lock the PLL at twice the
rate and drive the CPU
In Certain QCOM SoCs like apq8096 and msm8996 that have KRYO processors,
the CPU frequency subset and voltage value of each OPP varies
based on the silicon variant in use. Qualcomm Process Voltage Scaling Tables
defines the voltage and frequency value based on the msm-id in SMEM
and speedbin blown
Add support for SAW controlled regulators.
The regulators defined as SAW controlled in the device tree
will be controlled through special CPU registers instead of direct
SPMI accesses.
This is required especially for CPU supply regulators to synchronize
with clock scaling and for Automatic Voltage
1. Add NVMEM node for the speedbin
2. Add definitions for all possible MSM8996 CPU OPPs.
The qcom-cpufreq-kryo driver will select the appropriate subset.
Signed-off-by: Ilia Lin
Acked-by: Viresh Kumar
---
arch/arm64/boot/dts/qcom/apq8096-db820c.dts | 2 +-
arch/arm64/boot/dts/qcom/msm8996.dts
1. Add syscon node for the SAW CPU registers
2. Add SAW regulators gang definition for s8-s11
3. Add voltages to the OPP tables
4. Add the s11 SAW regulator as CPU regulator
Signed-off-by: Ilia Lin
Acked-by: Viresh Kumar
---
arch/arm64/boot/dts/qcom/msm8996.dtsi | 119 ++
Document the DT bindings for the SAW regulators.
The saw-leader is the only property that is configurable in DT.
The saw-slave property allows ganging (grouping) of
several regulators so that their outputs can be combined.
Signed-off-by: Ilia Lin
Reviewed-by: Rob Herring
---
.../bindings/regu
On Mon, May 14, 2018 at 1:03 PM, Andy Shevchenko
wrote:
> On Mon, 2018-05-14 at 10:06 +0200, Linus Walleij wrote:
>> The hunk hitting the x86 BCM43xx driver is especially tricky as the
>> number
>> comes out of SFI which is a mystery to me. I definately need someone
>> to
>> look at this. (Hi And
Hi Leo,
On 21/05/18 09:52, Leo Yan wrote:
Commit e573e978fb12 ("perf cs-etm: Inject capabilitity for CoreSight
traces") reworks the samples generation flow from CoreSight trace to
match the correct format so Perf report tool can display the samples
properly. But the change has side effect for p
The qcom-cpufreq-kryo driver reads the msm-id and efuse value from the SoC
to provide the OPP framework with required information.
This is used to determine the voltage and frequency value for each OPP of
operating-points-v2 table when it is parsed by the OPP framework.
This change adds documentat
Signed-off-by: Ilia Lin
Acked-by: Viresh Kumar
---
arch/arm64/boot/dts/qcom/msm8996.dtsi | 269 --
1 file changed, 260 insertions(+), 9 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi
b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index 37b7152c..e6cf29
Each of the CPU clusters (Power and Perf) on msm8996 are
clocked via 2 PLLs, a primary and alternate. There are also
2 Mux'es, a primary and secondary all connected together
as shown below
+---+
XO | |
+-->0
Each of the CPU clusters (Power and Perf) on msm8996 are
clocked via 2 PLLs, a primary and alternate. There are also
2 Mux'es, a primary and secondary all connected together
as shown below
+---+
XO | |
+-->0
From: Rajendra Nayak
Each of the CPU clusters on msm8996 are powered via a primary
PLL and a secondary PLL. The primary PLL is what drives the
CPU clk, except for times when we are reprogramming the PLL
itself, when we temporarily switch to an alternate PLL.
Use clock rate change notifiers to sup
Use devm_clk_hw_register instead of clk_hw_register
to simplify the usage of this API. This way drivers that call
the clk_hw_register_fixed_factor won't need to maintain
a data structure for further cleanup.
Signed-off-by: Ilia Lin
---
drivers/clk/clk-fixed-factor.c | 2 +-
1 file changed, 1 ins
On 16-05-18, 17:51, Srinivas Kandagatla wrote:
> This patch adds suppor to Qualcomm SLIMBus Non-Generic Device (NGD)
/s/suppor/support
> +/* NGD (Non-ported Generic Device) registers */
> +#define NGD_CFG 0x0
> +#define NGD_CFG_ENABLE BIT(0)
> +#define NGD_
This series is a continuation of the work started by Daniel [1]. The goal
is to use GICv3 interrupt priorities to simulate an NMI.
To achieve this, set two priorities, one for standard interrupts and
another, higher priority, for NMIs. Whenever we want to disable interrupts,
we mask the standard p
Drivers/subsystems creating scatterlists for DMA should be taking care
to respect the scatter-gather limitations of the appropriate device, as
described by dma_parms. A DMA API implementation cannot feasibly split
a scatterlist into *more* entries than originally passed, so it is not
well defined w
From: Daniel Thompson
Currently it is not possible to detect features of the boot CPU
until the other CPUs have been brought up.
This prevents us from reacting to features of the boot CPU until
fairly late in the boot process. To solve this we allow a subset
of features (that are likely to be co
arm64 does not provide native NMIs. Emulate the NMI behaviour using GIC
priorities.
Add the possibility to set an IRQ as an NMI and the handling of the NMI.
If the view of GIC priorities is the secure one
(i.e. SCR_EL3.FIQ == 0 && security enabled), do not allow the use of NMIs.
Emit a warning wh
Signed-off-by: Julien Thierry
Cc: Thomas Gleixner
Cc: Jason Cooper
Cc: Marc Zyngier
---
drivers/irqchip/irq-gic-common.c | 10 ++
drivers/irqchip/irq-gic-common.h | 2 ++
2 files changed, 12 insertions(+)
diff --git a/drivers/irqchip/irq-gic-common.c b/drivers/irqchip/irq-gic-common.
On 8 May 2018 at 20:46, Liming Sun wrote:
> This commit adds extension to the dw_mmc driver for Mellanox BlueField
> SoC. It updates the UHS_REG_EXT register to bring up the eMMC card on
> this SoC.
>
> Signed-off-by: Liming Sun
> Reviewed-by: David Woods
Thanks, applied for next!
Kind regards
On 15 May 2018 at 11:57, Jerome Brunet wrote:
> This patchset adds the optional reset of the meson-gx mmc controller and
> the related documentation.
>
> Changes since v1: [0]
> * Correct typo in the documentation
> * Separate code and documentation patches
> * Error on reset failure.
>
> [0]:
On 16 May 2018 at 21:20, Mathieu Malaterre wrote:
> In commit 97548575bef3 ("mmc: block: Convert RPMB to a character device") a
> new function `mmc_rpmb_ioctl` was added. The final return is simply
> returning a value of `0` instead of propagating the correct return code.
>
> Discovered during a c
On 8 May 2018 at 20:46, Liming Sun wrote:
> This patch updates arm64 defconfig to enable dw_mmc-bluefield,
> which is a driver extension of Synopsys Designware MMC for the
> Mellanox BlueField Soc.
>
> Signed-off-by: Liming Sun
> Reviewed-by: David Woods
I have applied the other parts in the se
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