This covers the differences between 1xx,3xx and 4xx.
Signed-off-by: Stanimir Varbanov
---
drivers/media/platform/qcom/venus/core.h | 4 ++
drivers/media/platform/qcom/venus/helpers.c | 37 +++
drivers/media/platform/qcom/venus/hfi_helper.h | 84 ++--
d
On 15 May 2018 at 06:46, Guenter Roeck wrote:
> On Thu, Apr 26, 2018 at 10:53:06AM +0200, Ulf Hansson wrote:
>> The limitation of being able to check only for -EPROBE_DEFER from
>> dev_pm_domain_attach() has been removed. Hence let's respect all error
>> codes and bail out accordingly.
>>
>
> AFAI
HFI version 4xx can pass more properties in the sequence change
event, extend the event structure with them.
Signed-off-by: Stanimir Varbanov
---
drivers/media/platform/qcom/venus/hfi.h | 9 ++
drivers/media/platform/qcom/venus/hfi_msgs.c | 46
2 files chan
Hello,
Here is v2 with following comments addressed:
* reworked venus suspend 3xx and reuse it for 4xx.
* drop 10/28 patch from v1, i.e. call of session_continue when
buffer requirements are not sufficient.
* fixed kbuild test robot warning in 11/28 by allocating instance
variable from heap.
Hi Bart,
On Mon, May 14, 2018 at 11:46:33AM -0700, Bart Van Assche wrote:
[...]
> diff --git a/Documentation/features/locking/cmpxchg64/arch-support.txt
> b/Documentation/features/locking/cmpxchg64/arch-support.txt
> new file mode 100644
> index ..65b3290ce5d5
> --- /dev/null
> +++
Hi Andy,
On Mon, 14 May 2018 20:18:37 +0300, Andy Shevchenko wrote:
> On Mon, May 14, 2018 at 12:33 PM, Anders Roxell
> wrote:
> > With CONFIG_PM, we get a harmless build warning:
> > drivers/i2c/busses/i2c-i801.c:1723:12: warning: ‘i801_resume’ defined but
> > not used [-Wunused-function]
> >
Hi Stanimir,
On 05/15/18 09:58, Stanimir Varbanov wrote:
> This is implementing a multi-stream decoder support. The multi
> stream gives an option to use the secondary decoder output
> with different raw format (or the same in case of crop).
You told me that multi-stream support is currently inte
On Mon, May 14, 2018 at 08:00:29PM +0200, Dominik Brodowski wrote:
> > +static void __invoke_syscall(struct pt_regs *regs, syscall_fn_t syscall_fn)
> > +{
> > + regs->regs[0] = syscall_fn(regs->regs[0], regs->regs[1],
> > + regs->regs[2], regs->regs[3],
> > +
Hi Stanimir,
On 05/15/18 09:58, Stanimir Varbanov wrote:
> Hello,
>
> Here is v2 with following comments addressed:
>
> * reworked venus suspend 3xx and reuse it for 4xx.
> * drop 10/28 patch from v1, i.e. call of session_continue when
> buffer requirements are not sufficient.
> * fixed kbuild
Mon, May 14, 2018 at 08:03:20PM CEST, j...@mojatatu.com wrote:
>On 14/05/18 10:27 AM, Vlad Buslov wrote:
>> Currently, all netlink protocol handlers for updating rules, actions and
>> qdiscs are protected with single global rtnl lock which removes any
>> possibility for parallelism. This patch set
On Mon, May 14, 2018 at 10:24:45PM +0200, Dominik Brodowski wrote:
> On Mon, May 14, 2018 at 12:41:10PM +0100, Mark Rutland wrote:
> > I agree it would be nicer if it had a wrapper that took a pt_regs, even
> > if it does nothing with it.
> >
> > We can't use SYSCALL_DEFINE0() due to the fault inj
Hi Leo, Daniel,
On 2018/5/15 3:53, Leo Yan wrote:
> From: Daniel Lezcano
>
> The current defconfig is inconsistent as it selects the mailbox and
> the clock for the hi6220 and the hi3660 without having their Kconfigs
> making sure the dependencies are correct. It ends up when selecting
> differe
Am Dienstag, den 15.05.2018, 13:51 +0800 schrieb Anson Huang:
> Add imx8mq-cpufreq driver for NXP i.MX8MQ SoC to support the
> hardware specific frequency and voltage scaling requirements.
>
> Signed-off-by: Anson Huang
Sorry, but NACK.
This just implements a specific reclocking sequence as a c
On Mon, May 14, 2018 at 03:31:06PM -0400, Waiman Long wrote:
> There are use cases where a rwsem can be acquired by one task, but
> released by another task. In thess cases, it may not be appropriate
> for the lock waiters to spin on the task that acquires the lock.
> One example will be the filesy
Hello,
On Tuesday, 15 May 2018 10:30:28 EEST Fabien DESSENNE wrote:
> On 14/05/18 12:39, Mauro Carvalho Chehab wrote:
> > Em Mon, 14 May 2018 07:35:03 -0300 Mauro Carvalho Chehab escreveu:
> >> Em Mon, 14 May 2018 08:00:37 + Fabien DESSENNE escreveu:
> >>> On 07/05/18 17:19, Mauro Carvalho Che
On 15/05/2018 10:10, Hans Verkuil wrote:
> On 05/15/18 09:25, Neil Armstrong wrote:
>> Hi Hans,
>>
>> Thanks for the extensive review.
>>
>> On 15/05/2018 08:58, Hans Verkuil wrote:
>>> On 05/15/2018 12:40 AM, Neil Armstrong wrote:
The Chrome OS Embedded Controller can expose a CEC bus, this p
==
ANNOUNCEMENT AND CALL FOR PARTICIPATION
LINUX SECURITY SUMMIT EUROPE 2018
25-26 October
On 05/15/18 10:28, Neil Armstrong wrote:
> + int ret;
> +
> + cros_ec_cec = devm_kzalloc(&pdev->dev, sizeof(*cros_ec_cec),
> +GFP_KERNEL);
> + if (!cros_ec_cec)
> + return -ENOMEM;
> +
> + platform_set_drvdata(pdev, cros_ec_cec);
>
On Mon, May 14, 2018 at 03:31:07PM -0400, Waiman Long wrote:
> The percpu_rwsem_release() is called when the ownership of the embedded
> rwsem is to be transferred to another task. The new owner, however, may
> take a while to get the ownership of the lock via percpu_rwsem_acquire().
> During that
* Peter Zijlstra wrote:
> And if we're going to do codegen, we might as well all generate this
> anyway, so all this mucking about is a complete waste of time.
I'm not yet convinced that it will be cleaner, but can be convinced in
principle,
but meanwhile the existing code is arguably butt-ug
Hi Simon,
On Fri, May 11, 2018 at 03:35:14PM +0200, Simon Horman wrote:
> On Fri, May 11, 2018 at 12:00:00PM +0200, Jacopo Mondi wrote:
> > Add compatible string for R-Car D3 R8A7795 to list of SoCs supported by
> > rcar-vin driver.
> >
> > Signed-off-by: Jacopo Mondi
>
> Reviewed-by: Simon Horma
Hi Jia
On 05/15/2018 03:03 AM, Jia He wrote:
Hi Suzuki
I will merge the other thread into this, and add the necessary CC list
That WARN_ON call trace is very easy to reproduce in my armv8a server
after I start 20 guests
and run memhog in the host. Of course, ksm should be enabled
For you
On Mon, May 14, 2018 at 10:57:44PM +0200, Dominik Brodowski wrote:
> On Mon, May 14, 2018 at 10:46:40AM +0100, Mark Rutland wrote:
> > Note that we play games with sys_ni_syscall(). It can't be defined with
> > SYSCALL_DEFINE0() because we must avoid the possibility of error
> > injection. Addition
On 2018-05-15 09:54, Vladimir Zapolskiy wrote:
> Hi Jan,
>
> On 05/15/2018 08:58 AM, Jan Kiszka wrote:
>> From: Jan Kiszka
>>
>> of_pci_get_host_bridge_resources() allocates the resource structures it
>> fills dynamically, but none of its callers care to release them so far.
>> Rather than requir
Hi Harini,
On 10.05.2018 13:37, Harini Katakam wrote:
> Hi Claudiu,
>
> On Fri, May 4, 2018 at 5:47 PM, Claudiu Beznea
> wrote:
>>
>>
>> On 22.03.2018 15:51, harinikatakamli...@gmail.com wrote:
>>> From: Harini Katakam
>>>
>>> This patch enables ARP wake event support in GEM through the followi
On 2018-05-15 09:58, Vladimir Zapolskiy wrote:
> Hi Jan,
>
> On 05/15/2018 08:58 AM, Jan Kiszka wrote:
>> Changes in v3:
>> - refactor series to be both bisectable and simpler while reworking
>>of_pci_get_host_bridge_resources()
>> - include of_pci_get_host_bridge_resources() removal
>> - i
On Mon, 2018-05-14 at 11:35 +0100, Marc Zyngier wrote:
> On 14/05/18 11:22, Erin Lo wrote:
> > From: Ben Ho
> >
> > Add basic chip support for Mediatek 8183
> >
> > Signed-off-by: Ben Ho
> > Signed-off-by: Erin Lo
> > ---
> > arch/arm64/boot/dts/mediatek/Makefile | 1 +
> > arch/arm64
2018-05-14 23:29 GMT+02:00 Geert Uytterhoeven :
> Hi Bartosz,
>
> On Fri, May 11, 2018 at 6:20 PM, Bartosz Golaszewski wrote:
>> From: Bartosz Golaszewski
>>
>> Provide a separate section in which pointers to early platform driver
>> structs will be stored.
>>
>> Signed-off-by: Bartosz Golaszewsk
On RDU1, imx51 usbh1 interface is either not used, or used via external
block that breaks USB2 signalling.
To keep things working if high-speed device gets connected to that
block, use ChipIdea feature to limit port to full speed.
Signed-off-by: Nikita Yushchenko
---
arch/arm/boot/dts/imx51-zii
On Mon, May 14, 2018 at 03:31:07PM -0400, Waiman Long wrote:
> The percpu_rwsem_release() is called when the ownership of the embedded
> rwsem is to be transferred to another task. The new owner, however, may
> take a while to get the ownership of the lock via percpu_rwsem_acquire().
> During that
From: Sean Wang
Adding an independent btuart.h header allows these essential definitions
can be reused in vendor driver. Also, struct btuart_vnd is extended with
additional callbacks such as .init initializing vendor data, .shtudown,
.recv and .send supporting SoC specific framing for that btuart
From: Marcel Holtmann
This is a from scratch written driver to run H:4 on serdev based system
with a Bluetooth controller attached via an UART. It is currently tested
on RPi3 and it has Broadcom integration. It is DT only and is missing
GPIO and runtime power management integration. Also Apple or
From: Sean Wang
v2 and changes since v1
- Dropped patches already being applied
- Rewirte the whole driver using btuart [1], and add slight extension
of btuart to fit into btmtkuart driver. Beware that [1] is also pulled
into one part of the series for avoiding any breakage when the patch
Am Dienstag, den 15.05.2018, 11:45 +0300 schrieb Nikita Yushchenko:
> On RDU1, imx51 usbh1 interface is either not used, or used via
> external
> block that breaks USB2 signalling.
>
> To keep things working if high-speed device gets connected to that
> block, use ChipIdea feature to limit port to
From: Sean Wang
Add a new quirk HCI_QUIRK_NON_PERSISTENT_SETUP allowing that a quirk that
runs setup() after every open() and not just after the first open().
Signed-off-by: Sean Wang
---
include/net/bluetooth/hci.h | 9 +
net/bluetooth/hci_core.c| 3 ++-
2 files changed, 11 insert
* Will Deacon wrote:
> With this patch, we're already seeing arch code (powerpc, risc-v) having
> to add what is basically boiler-plate code, and it seems like we're just
> doing this to make the generic code more readable! I'd much prefer we kept
> the arch code simple, and took on the complexi
From: Colin Ian King
Trivial fix to spelling mistake in DRM_INFO message.
Signed-off-by: Colin Ian King
---
drivers/gpu/drm/xen/xen_drm_front.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/xen/xen_drm_front.c
b/drivers/gpu/drm/xen/xen_drm_front.c
index 0
From: Sean Wang
Add an entry for the MediaTek Bluetooth driver.
Signed-off-by: Sean Wang
---
MAINTAINERS | 8
1 file changed, 8 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 0a1410d..3e9fa7c2 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -8874,6 +8874,14 @@ F: incl
From: Sean Wang
In order to open up the required power gate before any operation can be
effectively performed over the serial bus between CPU and serdev, it's
clearly essential to add common attach functions for PM domains to serdev
at the probe phase.
Similarly, the relevant dettach function fo
From: Sean Wang
This adds a driver to run on the top of btuart driver for the MediaTek
serial protocol based on running H:4, which can enable the built-in
Bluetooth device inside MT7622 SoC.
Signed-off-by: Sean Wang
---
drivers/bluetooth/Kconfig | 12 ++
drivers/bluetooth/Makefile|
On 15.05.2018 08:59, Vladimir Davydov wrote:
> On Thu, May 10, 2018 at 12:54:15PM +0300, Kirill Tkhai wrote:
>> To avoid further unneed calls of do_shrink_slab()
>> for shrinkers, which already do not have any charged
>> objects in a memcg, their bits have to be cleared.
>>
>> This patch introduces
From: Sean Wang
Add binding document for a SoC built-in device using MediaTek protocol.
Which could be found on MT7622 SoC or other similar MediaTek SoCs.
Signed-off-by: Sean Wang
Reviewed-by: Rob Herring
---
.../devicetree/bindings/net/mediatek-bluetooth.txt | 35 ++
1 fi
On Tue, May 15, 2018 at 09:46:01AM +0200, Martijn Coenen wrote:
< snip >
> >> About the unmap at runtime part, your commit message was a bit confusing.
> >> You
> >> said "every binder buffers should be mapped in advance by binder_mmap."
> >> but I
> >> think the new binder shrinker mechanism d
The following 3 issues are fixed in this patchset
1. In function flush_dacache_page and copy_user_highpage, the local irq is
enabled when the cache of the page at address page_address(page) is written
back to memory. It possibly causes data corruption. To fix this problem,
the local irq is disable
When reboot Linux, the PM domains attached to a device
are not shutdown. To SoCs which relys on reset the whole SoC,
there is no need to shutdown PM domains, but to Linux running
in a virtual machine with devices pass-through, we could not
reset the whole SoC. Currently we need Linux to shutdown it
On 14/05/18 20:18, Jolly Shah wrote:
> Hi Sudeep,
[..]
>>
>> As I mentioned in earlier patch, I don't see the need for this
>> debugfs interface. Clock lay has read-only interface in debugfs
>> already. Also if you want to debug clocks, you can do so using the
>> driver which uses these clocks
Mon, May 14, 2018 at 08:49:07PM CEST, vla...@mellanox.com wrote:
>
>On Mon 14 May 2018 at 16:23, Jiri Pirko wrote:
>> Mon, May 14, 2018 at 04:27:06PM CEST, vla...@mellanox.com wrote:
>>>Without rtnl lock protection it is no longer safe to use pointer to tc
>>>action without holding reference to it
On Tuesday, May 15, 2018 12:21:09 AM CEST Stephen Rothwell wrote:
>
> --Sig_/LKqNOwcm4.nPHJQHAB_CO6g
> Content-Type: text/plain; charset=US-ASCII
> Content-Transfer-Encoding: quoted-printable
>
> Hi Rafael,
Hi Stephen,
> Commit
>
> e689ba60f1f0 ("Merge branch 'opp/genpd-pstate-updates' of gi
In order to ensure that all data in source page has been written back
to memory before copy_page, the local irq shall be disabled before
calling cpu_dcache_wb_page(). In addition, removing unneeded page
invalidation for 'to' page.
Signed-off-by: Vincent Chen
---
arch/nds32/mm/cacheflush.c |4
1. Disable local irq before d-cache write-back and invalidate.
The cpu_dcache_wbinval_page function is composed of d-cache
write-back and invalidate. If the local irq is enabled when calling
cpu_dcache_wbinval_page, the content of d-cache is possibly updated
between write-back and invalidate. In
Hi Peter,
> >> In i2c_smbus_xfer_emulated(), the function i2c_transfer() is invoked to
> >> transfer i2c messages. The number of actual transferred messages is
> >> returned and saved to 'status'. If 'status' is negative, that means an
> >> error occurred during the transfer process. In that case,
According to Documentation/cachetlb.txt, the cache of the page at vmaddr
shall be flushed in flush_anon_page instead of the cache of the page at
page_address(page).
Signed-off-by: Vincent Chen
---
arch/nds32/mm/cacheflush.c |9 +++--
1 files changed, 7 insertions(+), 2 deletions(-)
diff
On Tue 15-05-18 10:35:25, Peter Zijlstra wrote:
> On Mon, May 14, 2018 at 03:31:07PM -0400, Waiman Long wrote:
> > The percpu_rwsem_release() is called when the ownership of the embedded
> > rwsem is to be transferred to another task. The new owner, however, may
> > take a while to get the ownershi
From: Colin Ian King
Trivial fix to spelling mistake in FAIL message.
Signed-off-by: Colin Ian King
---
scripts/dtc/checks.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/scripts/dtc/checks.c b/scripts/dtc/checks.c
index a2cc1036c915..9d253819e12c 100644
--- a/scripts/dtc
On Tue, 15 May 2018, Stephen Rothwell wrote:
> Hi all,
>
> Commits
>
> cb8ba171ae6c ("drm/i915/gvt: let force_to_nonpriv cmd handler only valid
> for LRI cmd")
> 0438a1059877 ("drm/i915/gvt: do not return error on handling
> force_to_nonpriv registers")
> 3d8b9e258b9d ("drm/i915/gvt: let N
Mon, May 14, 2018 at 09:07:06PM CEST, vla...@mellanox.com wrote:
>
>On Mon 14 May 2018 at 16:47, Jiri Pirko wrote:
>> Mon, May 14, 2018 at 04:27:07PM CEST, vla...@mellanox.com wrote:
>>
>> [...]
>>
>>
>>>+static int tcf_action_del_1(struct net *net, char *kind, u32 index,
>>>+
On Monday, May 14, 2018 5:35:41 PM CEST Srinivas Pandruvada wrote:
> On Sun, 2018-05-13 at 10:43 +0200, Rafael J. Wysocki wrote:
> > On Thursday, May 3, 2018 8:22:47 AM CEST Doug Smythies wrote:
> > > Allow use of the trace_pstate_sample trace function
> > > when the intel_pstate driver is in passi
From: Jan Kiszka
devm_pci_release_host_bridge_dev() failed to release the resource list.
Fixes: 5c3f18cce083 ("PCI: Add devm_pci_alloc_host_bridge() interface")
Signed-off-by: Jan Kiszka
---
drivers/pci/probe.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/
From: Jan Kiszka
Now that we have a device reference, make use of it for printing.
Signed-off-by: Jan Kiszka
---
drivers/pci/of.c | 22 --
1 file changed, 12 insertions(+), 10 deletions(-)
diff --git a/drivers/pci/of.c b/drivers/pci/of.c
index ac97491ba377..4f21514cb4e4 10
From: Jan Kiszka
of_pci_get_host_bridge_resources() allocates the resource structures it
fills dynamically, but none of its callers care to release them so far.
Rather than requiring everyone to do this explicitly, convert the
existing function to a managed version.
CC: Jingoo Han
CC: Joao Pint
From: Jan Kiszka
Particularly useful when working in virtual environments where the
controller may come and go, but possibly not only there.
CC: Will Deacon
CC: Lorenzo Pieralisi
Signed-off-by: Jan Kiszka
---
drivers/pci/host/pci-host-common.c | 13 +
drivers/pci/host/pci-host-g
From: Jan Kiszka
This controller is often instantiated by hypervisors, and they may add
multiple of them or add them in addition to a physical host controller
like the Jailhouse hypervisor is doing. Therefore allow for multiple
domains so that we can handle them all.
Signed-off-by: Jan Kiszka
-
From: Jan Kiszka
The only user of pci_get_new_domain_nr() is of_pci_bus_find_domain_nr().
Since they are defined in the same compilation unit,
pci_get_new_domain_nr() can be made static, which also simplifies
preprocessor conditionals.
No functional change intended.
Signed-off-by: Jan Kiszka
A
Changes in v4:
- restore pci_free_resource_list() in error path of
of_pci_get_host_bridge_resources()
Changes in v3:
- refactor series to be both bisectable and simpler while reworking
of_pci_get_host_bridge_resources()
- include of_pci_get_host_bridge_resources() removal
- include devm_
From: Jan Kiszka
We will add a real device parameter to this function soon.
Signed-off-by: Jan Kiszka
---
drivers/pci/of.c | 18 +-
include/linux/of_pci.h | 4 ++--
2 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/drivers/pci/of.c b/drivers/pci/of.c
index
From: Jan Kiszka
Another step towards a managed version of
of_pci_get_host_bridge_resources(): Feed in the underlying device,
rather than just the OF node. This will allow to use managed resource
allocation internally later on.
CC: Jingoo Han
CC: Joao Pinto
CC: Lorenzo Pieralisi
Signed-off-by
On Fri 11-05-18 10:17:55, Pavel Tatashin wrote:
> > Thanks that helped me to see the problem. On the other hand isn't this a
> > bit of an overkill? AFAICS this affects only NEED_PER_CPU_KM which is !SMP
> > and DEFERRED_STRUCT_PAGE_INIT makes only very limited sense on UP,
> > right?
>
> > Or do
On Fri, 4 May 2018, Rodrigo Rivas Costa wrote:
> > If noone has any objections (last chance to raise them), I'll be
> > queuing this for 4.18.
>
> That would be great, thanks!
>
> Now that my distro upgraded to 4.16, without the hid-quirks array, I've been
> testing it a bit more.
>
> It work
On 05/15/2018 11:54 AM, Colin King wrote:
From: Colin Ian King
Trivial fix to spelling mistake in DRM_INFO message.
Signed-off-by: Colin Ian King
Thank you,
Reviewed-by: Oleksandr Andrushchenko
Will apply to drm-misc-next
---
drivers/gpu/drm/xen/xen_drm_front.c | 2 +-
1 file changed,
On Mon, 14 May 2018 14:13:39 +0200
Boris Brezillon wrote:
> On Mon, 14 May 2018 14:00:19 +0200
> Geert Uytterhoeven wrote:
>
> > Hi Boris,
> >
> > On Mon, May 14, 2018 at 1:46 PM, Boris Brezillon
> > wrote:
> > > On Mon, 14 May 2018 13:32:30 +0200
> > > Geert Uytterhoeven wrote:
> > >>
fix below warning about PPI interrupts configuration:
"GIC: PPI13 is secure or misconfigured"
Signed-off-by: Jisheng Zhang
---
arch/arm/boot/dts/berlin2.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/berlin2.dtsi b/arch/arm/boot/dts/berlin2.dtsi
index
From: Rajendra Nayak
Allow clk_alpha_pll_configure to be called from loadable
kernel modules.
Signed-off-by: Rajendra Nayak
Signed-off-by: Ilia Lin
---
drivers/clk/qcom/clk-alpha-pll.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-
[v7]
* Addressed comments from Viresh about resourses deallocation
and DT compatible
[v6]
* Addressed comments from Viresh about:
** Comments style
** Kconfig bool instead of tristate
** DT and documentation style
** Resourses deallocation on an error
** Typos
[v5]
* Rebased
* Address
From: Rajendra Nayak
The CPU clock controller's primary PLL operates on a single VCO range,
between 600MHz and 3GHz. However the CPUs do support OPPs with
frequencies between 300MHz and 600MHz. In order to support running the
CPUs at those frequencies we end up having to lock the PLL at twice the
From: Rajendra Nayak
Each of the CPU clusters on msm8996 are powered via a primary
PLL and a secondary PLL. The primary PLL is what drives the
CPU clk, except for times when we are reprogramming the PLL
itself, when we temporarily switch to an alternate PLL.
Use clock rate change notifiers to sup
Each of the CPU clusters (Power and Perf) on msm8996 are
clocked via 2 PLLs, a primary and alternate. There are also
2 Mux'es, a primary and secondary all connected together
as shown below
+---+
XO | |
+-->0
Add support for SAW controlled regulators.
The regulators defined as SAW controlled in the device tree
will be controlled through special CPU registers instead of direct
SPMI accesses.
This is required especially for CPU supply regulators to synchronize
with clock scaling and for Automatic Voltage
In Certain QCOM SoCs like apq8096 and msm8996 that have KRYO processors,
the CPU ferequencies subset and voltage value of each OPP varies
based on the silicon variant in use. Qualcomm Process Voltage Scaling Tables
defines the voltage and frequency value based on the msm-id in SMEM
and speedbin blo
Signed-off-by: Ilia Lin
---
arch/arm64/boot/dts/qcom/apq8096-db820c.dts | 2 +-
arch/arm64/boot/dts/qcom/msm8996.dtsi | 311 +++-
2 files changed, 310 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c.dts
b/arch/arm64/boot/dts/qco
Add support for SAW controlled regulators.
The regulators defined as SAW controlled in the device tree
will be controlled through special CPU registers instead of direct
SPMI accesses.
This is required especially for CPU supply regulators to synchronize
with clock scaling and for Automatic Voltage
In Certain Qualcomm Technologies, Inc. SoCs like apq8096 and msm8996
that have KRYO processors, the CPU ferequencies subset and voltage value
of each OPP varies based on the silicon variant in use.
Qualcomm Technologies, Inc. Process Voltage Scaling Tables
defines the voltage and frequency value ba
On Tue 15 May 2018 at 09:03, Jiri Pirko wrote:
> Mon, May 14, 2018 at 09:07:06PM CEST, vla...@mellanox.com wrote:
>>
>>On Mon 14 May 2018 at 16:47, Jiri Pirko wrote:
>>> Mon, May 14, 2018 at 04:27:07PM CEST, vla...@mellanox.com wrote:
>>>
>>> [...]
>>>
>>>
+static int tcf_action_del_1(struct
On Wed, 9 May 2018, Dmitry Torokhov wrote:
> From: Dmitry Torokhov
>
> On many Chromebooks touch devices are multi-sourced; the components are
> electrically compatible and one can be freely swapped for another without
> changing the OS image or firmware.
>
> To avoid bunch of scary messages wh
1. Add syscon node for the SAW CPU registers
2. Add SAW regulators gang definition for s8-s11
3. Add voltages to the OPP tables
4. Add the s11 SAW regulator as CPU regulator
Signed-off-by: Ilia Lin
Acked-by: Viresh Kumar
---
arch/arm64/boot/dts/qcom/msm8996.dtsi | 75 +++
fix below warning about PPI interrupts configuration:
"GIC: PPI13 is secure or misconfigured"
Signed-off-by: Jisheng Zhang
---
arch/arm/boot/dts/berlin2q.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/berlin2q.dtsi b/arch/arm/boot/dts/berlin2q.dtsi
ind
Correct CPU supply name to meet cpufreq-dt driver's
requirement for voltage scaling.
Signed-off-by: Anson Huang
---
arch/arm/boot/dts/imx7d-cl-som-imx7.dts | 4 ++--
arch/arm/boot/dts/imx7d-nitrogen7.dts | 2 +-
arch/arm/boot/dts/imx7d-sdb.dts | 2 +-
3 files changed, 4 insertions(+),
Signed-off-by: Ilia Lin
Acked-by: Viresh Kumar
---
arch/arm64/boot/dts/qcom/msm8996.dtsi | 269 --
1 file changed, 260 insertions(+), 9 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi
b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index 37b7152c..e6cf29
On 14 May 2018 at 09:50, tip-bot for Hans de Goede wrote:
> Commit-ID: 1de3a1be8a9345fd0c7d9bb1009b21afe6b6b10f
> Gitweb:
> https://git.kernel.org/tip/1de3a1be8a9345fd0c7d9bb1009b21afe6b6b10f
> Author: Hans de Goede
> AuthorDate: Fri, 4 May 2018 08:00:01 +0200
> Committer: Ingo Molnar
The PMUX for each duplex allows for selection of ACD clock source.
The DVM (Dynamic Variation Monitor) will flag an error
when a voltage droop event is detected. This flagged error
enables ACD to provide a div-by-2 clock, sourced from the primary PLL.
The duplex will be provided the divided clock
u
On 15-05-18, 12:13, Ilia Lin wrote:
> Signed-off-by: Ilia Lin
> ---
> arch/arm64/boot/dts/qcom/apq8096-db820c.dts | 2 +-
> arch/arm64/boot/dts/qcom/msm8996.dtsi | 311
> +++-
> 2 files changed, 310 insertions(+), 3 deletions(-)
Acked-by: Viresh Kumar
--
vires
On 14/05/2018 7:41 PM, Qing Huang wrote:
On 5/13/2018 2:00 AM, Tariq Toukan wrote:
On 11/05/2018 10:23 PM, Qing Huang wrote:
When a system is under memory presure (high usage with fragments),
the original 256KB ICM chunk allocations will likely trigger kernel
memory management to enter sl
Each of the CPU clusters (Power and Perf) on msm8996 are
clocked via 2 PLLs, a primary and alternate. There are also
2 Mux'es, a primary and secondary all connected together
as shown below
+---+
XO | |
+-->0
On 15-05-18, 12:13, Ilia Lin wrote:
> In Certain QCOM SoCs like apq8096 and msm8996 that have KRYO processors,
> the CPU ferequencies subset and voltage value of each OPP varies
> based on the silicon variant in use. Qualcomm Process Voltage Scaling Tables
> defines the voltage and frequency value
The driver provides kernel level API for other drivers
to access the MSM8996 L2 cache registers.
Separating the L2 access code from the PMU driver and
making it public to allow other drivers use it.
The accesses must be separated with a single spinlock,
maintained in this driver.
Signed-off-by: Il
On Mon, 2018-05-14 at 20:38 +0300, Andy Shevchenko wrote:
> First of all, do not remove mailing lists from Cc and people if you
> are not sure they do not need your stuff.
>
Sorry. My mistake.
> On Mon, May 14, 2018 at 11:11 AM, Radu Pirea
> wrote:
> > On Sun, 2018-05-13 at 16:33 +0300, Andy She
i.MX7S does NOT support CPU frequency scaling, so no
need to specify the CPU regulator supply.
Signed-off-by: Anson Huang
---
arch/arm/boot/dts/imx7s-warp.dts | 4
1 file changed, 4 deletions(-)
diff --git a/arch/arm/boot/dts/imx7s-warp.dts b/arch/arm/boot/dts/imx7s-warp.dts
index 8a30b14.
Not related to the patch, but that's weird. I get that it's part of the
user API now, but why it u8 and can't it be changed?
regards,
dan carpenter
This adds the necessary data for handling io voltage domains on PX30.
As interesting tidbit, the PX30 contains two separate iodomain areas.
One in the regular General Register Files (GRF) and one in PMUGRF in the
pmu power domain.
Signed-off-by: David Wu
---
.../bindings/power/rockchip-io-domain
On Sun, 2018-05-13 at 16:33 +0300, Andy Shevchenko wrote:
> On Fri, May 11, 2018 at 1:38 PM, Radu Pirea > wrote:
> > This is the driver for at91-usart in spi mode. The USART IP can be
> > configured
> > to work in many modes and one of them is SPI.
> > +#include
> > +#include
>
> Here is someth
Modified dma pointer callback implementation.
hw ptr calculated based on System Memory to
ACP SRAM dma channel transfer count in case of playback.
In case of capture, hw ptr calculated based on dma transfer
count for ACP SRAM to System Memory Dma channel.
Added IOC Bit for Sysmem to ACP Dma channel
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