Hi Matheus,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on pinctrl/devel]
[also build test ERROR on v4.17-rc3 next-20180501]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day-ci
Hi Lorenzo,
On Thursday 26 April 2018 10:26 PM, Lorenzo Pieralisi wrote:
> On Tue, Apr 24, 2018 at 02:44:40PM +0100, Gustavo Pimentel wrote:
>> Adds a seconds entry on the pci_epf_test_ids structure that disables the
>
> "Add a second entry to..."
>
>> linkup_notifier parameter on driver for the
>From d54b2acf63191eba3d5052bf34fe6d26e3580ac2 Mon Sep 17 00:00:00 2001
From: Tetsuo Handa
Date: Tue, 1 May 2018 15:36:52 +0900
Subject: [PATCH] x86/kexec: avoid double free_page() upon do_kexec_load()
failure.
syzbot is reporting crashes after memory allocation failure inside
do_kexec_load() [1
On Monday 30 April 2018 10:17 PM, Boris Brezillon wrote:
> On Mon, 30 Apr 2018 18:45:06 +0200
> Bartosz Golaszewski wrote:
>
>> 2018-04-30 12:09 GMT+02:00 Boris Brezillon :
>>> Hi Bartosz,
>>>
>>> On Mon, 30 Apr 2018 10:24:41 +0200
>>> Bartosz Golaszewski wrote:
>>>
From: Bartosz Golaszewsk
On Sun 2018-04-29 16:37:37, Greg KH wrote:
> On Sun, Apr 29, 2018 at 10:07:26PM +0200, Ondrej Zary wrote:
> > On Sunday 29 April 2018 14:07:05 Greg KH wrote:
> > > On Thu, Apr 26, 2018 at 08:11:08AM +0200, Pavel Machek wrote:
> > > > On Wed 2018-04-25 08:46:02, Matthew Wilcox wrote:
> > > > > Recen
On 26/04/18 20:50, Thomas Gleixner wrote:
> On Mon, 23 Apr 2018, Marc Zyngier wrote:
>
>> Nobody would be insane enough to try and use level triggered
>> MSIs on PCI, but let's make sure it doesn't happen. Also,
>> let's mandate that the irqchip backing the platform MSI domain
>> is providing an i
This will be essentially same with below one.
ioctl(TIOCVHANGUP) versus ioctl(TCSETS) can race.
#syz dup: KASAN: user-memory-access Write in n_tty_set_termios
On Tue, May 01, 2018 at 01:20:26PM +0530, Kohli, Gaurav wrote:
> But In our older case, where we have seen failure below is the wake up path
> and ftraces, Wakeup occured and completed before schedule call only.
>
> So final state of CPUHP is running not parked. I have also pasted debug
> ftraces
commit ece1397cbc89c51914fae1aec729539cfd8bd62b upstream
Some variants of the Arm Cortex-55 cores (r0p0, r0p1, r1p0) suffer
from an erratum 1024718, which causes incorrect updates when DBM/AP
bits in a page table entry is modified without a break-before-make
sequence. The work around is to disable
Hi,
This patchset adds support for PUD hugepages at stage 2. This feature
is useful on cores that have support for large sized TLB mappings
(e.g., 1GB for 4K granule). Previous postings can be found at [0][1].
Support is added to code that is shared between arm and arm64. Dummy
helpers for arm ar
The code for operations such as marking the pfn as dirty, and
dcache/icache maintenance during stage 2 fault handling is duplicated
between normal pages and PMD hugepages.
Instead of creating another copy of the operations when we introduce
PUD hugepages, let's share them across the different page
Tejun, Jan, Jens,
Can you review this patch? syzbot has hit this bug for nearly 4000 times but
is still unable to find a reproducer. Therefore, the only way to test would be
to apply this patch upstream and test whether the problem is solved.
On 2018/04/24 21:19, Tetsuo Handa wrote:
>>From 39ed6b
KVM currently supports PMD hugepages at stage 2. Extend the stage 2
fault handling to add support for PUD hugepages.
Addition of pud hugepage support enables additional hugepage
sizes (e.g., 1G with 4K granule) which can be useful on cores that
support mapping larger block sizes in the TLB entries
In preparation for creating PUD hugepages at stage 2, add support for
write protecting PUD hugepages when they are encountered. Write
protecting guest tables is used to track dirty pages when migrating
VMs.
Also, provide trivial implementations of required kvm_s2pud_* helpers
to allow sharing of c
Introduce helpers to abstract architectural handling of the conversion
of pfn to page table entries and marking a PMD page table entry as a
block entry.
The helpers are introduced in preparation for supporting PUD hugepages
at stage 2 - which are supported on arm64 but do not exist on arm.
Signed
On Tuesday 01 May 2018 03:23 PM, Sekhar Nori wrote:
> On Tuesday 01 May 2018 02:55 PM, Sekhar Nori wrote:
>> On Monday 30 April 2018 01:54 PM, Bartosz Golaszewski wrote:
>>> From: Bartosz Golaszewski
>>>
>>> We have the 'ti,davinci-chipselect' property in the device tree, but
>>> when using platfo
On Thu, Apr 26, 2018 at 01:51:29PM +0200, Bartlomiej Zolnierkiewicz wrote:
> * Add dummy exynos4210_tmu_set_trip_hyst() helper.
>
> * Add ->tmu_set_trip_temp and ->tmu_set_trip_hyst methods to struct
> exynos_tmu_data and set them in exynos_map_dt_data().
>
> * Move trips setting to exynos_tmu_
On Monday 30 April 2018 03:39 PM, Boris Brezillon wrote:
> Hi Bartosz,
>
> On Mon, 30 Apr 2018 10:24:41 +0200
> Bartosz Golaszewski wrote:
>
>> From: Bartosz Golaszewski
>>
>> We have the 'ti,davinci-chipselect' property in the device tree, but
>> when using platform data the driver silently us
On Tue, 01 May 2018 19:48:58 +1000
Benjamin Herrenschmidt wrote:
> On Tue, 2018-05-01 at 00:55 +1000, Nicholas Piggin wrote:
> > The RAW console does not need writes to be atomic, so relax
> > opal_put_chars to be able to do partial writes, and implement an
> > _atomic variant which does not take
On 01/05/18 11:26, Punit Agrawal wrote:
Introduce helpers to abstract architectural handling of the conversion
of pfn to page table entries and marking a PMD page table entry as a
block entry.
The helpers are introduced in preparation for supporting PUD hugepages
at stage 2 - which are supported
With SDCC5, the MCI register space got removed and the offset/order of
several registers have changed. Based on SDCC version used and the register,
we need to pick the base address and offset.
Also power irq is a signal from controller to SW that it is ready for
voltage switch. So added support to
From: Sayali Lokhande
For SDCC version 5.0.0, MCI registers are removed from SDCC
interface and some registers are moved to HC. This change is
to support MCI register removal for msmfalcon. New compatible
string "qcom,sdhci-msm-v5" is added for msmfalcon to support
this change.
Change-Id: I0febf
On Tue, May 01, 2018 at 12:18:45PM +0200, Peter Zijlstra wrote:
> Aaaah... I think I've spotted a problem there. We clear SHOULD_PARK
> before we rebind, so if the thread lost the first PARKED store,
> does the completion, gets migrated, cycles through the loop and now
> observes !SHOULD_PARK and b
On Tuesday 01 May 2018 03:59 PM, Sekhar Nori wrote:
> On Tuesday 01 May 2018 03:23 PM, Sekhar Nori wrote:
>> On Tuesday 01 May 2018 02:55 PM, Sekhar Nori wrote:
>>> On Monday 30 April 2018 01:54 PM, Bartosz Golaszewski wrote:
From: Bartosz Golaszewski
We have the 'ti,davinci-chipsel
From: Sahitya Tummala
When the regulators are not managed by SDHCI host driver (i.e.,
when host->vmmc and host->vmmcq are absent), get the regulator
current capabilities through a new host op get_current_limit().
Signed-off-by: Sahitya Tummala
Signed-off-by: Sayali Lokhande
[vvisw...@codeauror
From: Sahitya Tummala
This is needed to get the current capabilities of vdd
regulator that is not managed by SDHCI driver.
Change-Id: I927c14b9890f1d672fe8a3e89d0b334f43463b36
Signed-off-by: Sahitya Tummala
Signed-off-by: Sayali Lokhande
Signed-off-by: Vijay Viswanath
---
drivers/mmc/host/sd
From: Asutosh Das
Some platforms require that the voltage switching happen only after
the register write occurs and controller is ready for the switch. When
the controller is ready, it will inform through power irq.
Add voltage regulator APIs and use them during power irq to switch
voltage inste
On 5/1/2018 3:48 PM, Peter Zijlstra wrote:
On Tue, May 01, 2018 at 01:20:26PM +0530, Kohli, Gaurav wrote:
But In our older case, where we have seen failure below is the wake up path
and ftraces, Wakeup occured and completed before schedule call only.
So final state of CPUHP is running not pa
On Thu, Apr 26, 2018 at 01:51:30PM +0200, Bartlomiej Zolnierkiewicz wrote:
> Check return values of ->get_trip_[temp,hyst] methods in
> exynos_tmu_initialize().
>
> Signed-off-by: Bartlomiej Zolnierkiewicz
> ---
> drivers/thermal/samsung/exynos_tmu.c | 10 +++---
> 1 file changed, 7 insertio
Good day,
Greetings. This is the second time I am sending this email to you.
Please confirm if this email is still in use for a confidential
discussion.
Best Regards,
On Tue, May 01, 2018 at 12:18:45PM +0200, Peter Zijlstra wrote:
> Aaaah... I think I've spotted a problem there. We clear SHOULD_PARK
> before we rebind, so if the thread lost the first PARKED store,
> does the completion, gets migrated, cycles through the loop and now
> observes !SHOULD_PARK and b
Looks good to me, thank you.
On 1 May 2018 at 11:01, Tetsuo Handa wrote:
>
> From 247cae4da0490c2e285e0a99e630ef963fabb6d5 Mon Sep 17 00:00:00 2001
> From: Tetsuo Handa
> Date: Tue, 1 May 2018 14:15:19 +0900
> Subject: [PATCH] bfs: add sanity check at bfs_fill_super().
>
> syzbot is reporting to
Hi Bartosz,
On Tuesday 17 April 2018 11:00 PM, Bartosz Golaszewski wrote:
> From: Bartosz Golaszewski
>
> This series converts the only user of the handcoded, mach-specific reset
> routines in the davinci platform to using the reset framework.
>
> Patches 1-2 add necessary lookups/DT-properties
Good point. But there are gid and uid fields in inode disc record.
https://ext4.wiki.kernel.org/index.php/Ext4_Disk_Layout#Inode_Table
I assume these can be use to ensure that the directory in which it is to
be placed has permissions to accept the inode. If that is not the case
then it would ha
Hello!
Mistave contacted me, because he has Dell Inspiron 15R SE (7520) on
which are not working 3 hotkeys located in the right upper corner.
After debugging we find out that this Dell Inspirion sends following WMI
event to dell-wmi.c driver:
=
On Thu, Apr 26, 2018 at 01:51:31PM +0200, Bartlomiej Zolnierkiewicz wrote:
> Cleanup code for enabling threshold interrupts in ->tmu_control
> method implementations.
>
> There should be no functional changes caused by this patch.
>
> Signed-off-by: Bartlomiej Zolnierkiewicz
> ---
> drivers/the
On Tue, May 1, 2018 at 12:58 PM, Tony Wallace wrote:
> Good point. But there are gid and uid fields in inode disc record.
>
> https://ext4.wiki.kernel.org/index.php/Ext4_Disk_Layout#Inode_Table
>
> I assume these can be use to ensure that the directory in which it is to
> be placed has permission
Michal Suchánek writes:
> Hello,
>
> On Tue, 24 Apr 2018 14:15:57 +1000
> Michael Ellerman wrote:
>
>> From: Michal Suchanek
>>
>> Check what firmware told us and enable/disable the barrier_nospec as
>> appropriate.
>>
>> We err on the side of enabling the barrier, as it's no-op on older
>> sy
On Thu, Apr 26, 2018 at 01:51:32PM +0200, Bartlomiej Zolnierkiewicz wrote:
> Remove unused defines for Exynos5433.
I agree to remove these macros but is there a place with the documentation for
those values if we need to put them back ?
> There should be no functional changes caused by this patc
From: Henk
Fn + left arrow hotkey combination is used for enabling/disabling automatic
display brigthness based on integrated ALS sensor. For this purpose there
is standard linux key KEY_BRIGHTNESS_AUTO so use it instead of KEY_UNKNOWN.
Tested on Dell Lattitude E6500.
Signed-off-by: Henk Vergon
On Thu, Apr 26, 2018 at 01:51:33PM +0200, Bartlomiej Zolnierkiewicz wrote:
> Remove trip reporting to user-space - I'm not aware of any user-space
> program which relies on it and there is a thermal user-space governor
> which does it in proper way nowadays.
>
> Signed-off-by: Bartlomiej Zolnierki
From: Boris Ostrovsky
> Sent: 30 April 2018 17:24
> To: linux-kernel@vger.kernel.org; xen-de...@lists.xenproject.org
> Cc: jgr...@suse.com; Boris Ostrovsky; sta...@vger.kernel.org
> Subject: [PATCH 1/4] xen/PVH: Replace GDT_ENTRY with explicit constant
>
> Latest binutils release (2.29.1) will no
On Tue, May 01, 2018 at 04:10:53PM +0530, Kohli, Gaurav wrote:
> Yes with loop, it will reset TASK_PARKED but that is not happening in the
> dumps we have seen.
But was that with or without the fixed wait-loop? I don't care about
stuff you might have seen with the current code, that is clearly bro
Hi,
On Mon, Apr 30, 2018 at 05:04:50PM +0100, Colin King wrote:
> From: Colin Ian King
>
> trivial fix to spelling mistake in dev_error message.
>
> Signed-off-by: Colin Ian King
> ---
Thanks, queued.
-- Sebastian
> drivers/power/supply/ab8500_charger.c | 2 +-
> 1 file changed, 1 insertio
Instead of just hogging the reset GPIO into deactivated state, activate and
then de-activate the reset. This allows for better recovery if the CPU was
reset halfway through an I2C transaction for example.
Signed-off-by: Mike Looijmans
---
drivers/i2c/muxes/i2c-mux-pca954x.c | 12 ++--
1
On 5/1/2018 5:01 PM, Peter Zijlstra wrote:
On Tue, May 01, 2018 at 04:10:53PM +0530, Kohli, Gaurav wrote:
Yes with loop, it will reset TASK_PARKED but that is not happening in the
dumps we have seen.
But was that with or without the fixed wait-loop? I don't care about
stuff you might have se
On Wed, Apr 25, 2018 at 03:26:41PM +0200, Thiebaud Weksteen wrote:
> Signed-off-by: Thiebaud Weksteen
> ---
> drivers/char/tpm/tpm_eventlog_of.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/char/tpm/tpm_eventlog_of.c
> b/drivers/char/tpm/tpm_eventlog_of.c
Hi Kim,
On Fri, Apr 27, 2018 at 11:56:25AM -0500, Kim Phillips wrote:
> On Fri, 27 Apr 2018 17:09:14 +0100
> Will Deacon wrote:
> > On Fri, Apr 27, 2018 at 10:46:29AM -0500, Kim Phillips wrote:
> > > On Fri, 27 Apr 2018 15:37:20 +0100
> > > Will Deacon wrote:
> > > > For anything under drivers/p
On Mon, Apr 30, 2018 at 4:12 PM, Jeremy Cline wrote:
> On 04/29/2018 06:05 PM, Theodore Y. Ts'o wrote:
>> On Sun, Apr 29, 2018 at 01:20:33PM -0700, Sultan Alsawaf wrote:
>>> On Sun, Apr 29, 2018 at 08:41:01PM +0200, Pavel Machek wrote:
Umm. No. https://www.youtube.com/watch?v=xneBjc8z0DE
>>>
On Tue, May 01, 2018 at 03:37:47PM +0530, Kishon Vijay Abraham I wrote:
> Hi Lorenzo,
>
> On Thursday 26 April 2018 10:26 PM, Lorenzo Pieralisi wrote:
> > On Tue, Apr 24, 2018 at 02:44:40PM +0100, Gustavo Pimentel wrote:
> >> Adds a seconds entry on the pci_epf_test_ids structure that disables the
On Thu, Apr 26, 2018 at 07:49:24PM +0200, Greg KH wrote:
> On Wed, Apr 25, 2018 at 10:53:32AM -0700, James Bottomley wrote:
> > On Wed, 2018-04-25 at 13:06 +0200, Greg KH wrote:
> > > On Wed, Apr 25, 2018 at 01:44:20PM +0300, Jarkko Sakkinen wrote:
> > > > "tpm: add retry logic" caused merge confli
> -Original Message-
> From: Wenwen Wang [mailto:wang6...@umn.edu]
> Sent: Tuesday, May 01, 2018 00:26
> To: Wenwen Wang
> Cc: Kangjie Lu ; Jon Maloy ; Ying
> Xue ; David S. Miller ;
> open list:TIPC NETWORK LAYER ; open list:TIPC
> NETWORK LAYER ; open list ker...@vger.kernel.org>
> Su
Thankyou everyone for providing feedback and testing v6 patchset.
This patchset aims to provide a basic version of QCOM DSP based
audio support which is available in downstream andriod kernels.
This patchset support audio playback on HDMI-RX, MI2S, SLIMBus and
will add support to other features as
This patch add DT bindings for AFE (Audio Frontend) DSP module.
Signed-off-by: Srinivas Kandagatla
Reviewed-and-tested-by: Rohit kumar
---
.../devicetree/bindings/sound/qcom,q6afe.txt | 104 +
include/dt-bindings/sound/qcom,q6afe.h | 31 ++
2 files cha
This patch adds support to memory map and unmap regions commands in
q6asm module.
Signed-off-by: Srinivas Kandagatla
Reviewed-and-tested-by: Rohit kumar
---
sound/soc/qcom/qdsp6/q6asm.c | 349 +++
sound/soc/qcom/qdsp6/q6asm.h | 5 +
2 files changed, 354
Add myself as co-maintainer of qcom audio drivers
Signed-off-by: Srinivas Kandagatla
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 4340b783ab80..527e2658cfe4 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -11531,6 +11531,7 @@ F: drivers/c
This patch adds support to DB820c machine driver.
Signed-off-by: Srinivas Kandagatla
---
sound/soc/qcom/Kconfig | 9 ++
sound/soc/qcom/Makefile | 2 +
sound/soc/qcom/apq8096.c | 238 +++
3 files changed, 249 insertions(+)
create mode 100644 sou
This patch adds support to Q6ADM (Audio Device Manager) module in
q6dsp. ADM performs routing between audio streams and AFE ports.
It does Rate matching for streams going to devices driven by
different clocks, it handles volume ramping, Mixing with channel
and bit-width. ADM creates and destroys dy
Add devicetree bindings documentation file for Qualcomm apq8096 sound card.
Signed-off-by: Srinivas Kandagatla
Reviewed-by: Rob Herring
---
.../devicetree/bindings/sound/qcom,apq8096.txt | 109 +
1 file changed, 109 insertions(+)
create mode 100644 Documentation/devicet
This patch adds support to q6asm dai driver which configures Q6ASM streams
to pass pcm data.
Signed-off-by: Srinivas Kandagatla
Reviewed-and-tested-by: Rohit kumar
---
sound/soc/qcom/Kconfig | 4 +
sound/soc/qcom/qdsp6/Makefile| 1 +
sound/soc/qcom/qdsp6/q6asm-dai.c | 628
This patch add support to MI2S mixers required to select path between
ASM stream and AFE ports.
Signed-off-by: Srinivas Kandagatla
Reviewed-and-tested-by: Rohit kumar
---
sound/soc/qcom/qdsp6/q6routing.c | 329 +++
1 file changed, 329 insertions(+)
diff --gi
This patch adds basic support to Q6 ASM (Audio Stream Manager) module on
Q6DSP. ASM supports up to 8 concurrent streams. each stream can be setup
as playback/capture. ASM provides top control functions like
Pause/flush/resume for playback and record. ASM can Create/destroy encoder,
decoder and also
This patch adds support to SLIMBus related mixers to control mux between
ASM stream and AFE port.
Signed-off-by: Srinivas Kandagatla
Reviewed-and-tested-by: Rohit kumar
---
sound/soc/qcom/qdsp6/q6routing.c | 261 +++
1 file changed, 261 insertions(+)
diff --
This patch adds support to q6afe backend dais driver.
Signed-off-by: Srinivas Kandagatla
Reviewed-and-tested-by: Rohit kumar
---
sound/soc/qcom/Kconfig | 4 +
sound/soc/qcom/qdsp6/Makefile| 1 +
sound/soc/qcom/qdsp6/q6afe-dai.c | 752 +++
3
This patch adds support to q6 routing driver which configures route
between ASM and AFE module using ADM apis.
This driver uses dapm widgets to setup the matrix between AFE ports and
ASM streams.
Signed-off-by: Srinivas Kandagatla
Reviewed-and-tested-by: Rohit kumar
---
sound/soc/qcom/Kconfig
This patch adds support to open, write and media format commands
in the q6asm module.
Signed-off-by: Srinivas Kandagatla
Reviewed-and-tested-by: Rohit kumar
---
sound/soc/qcom/qdsp6/q6asm.c | 839 ++-
sound/soc/qcom/qdsp6/q6asm.h | 49 +++
2 files change
This patch adds support to LPASS Bit clock, LPASS Digital
core clock and OSR clock. These clocks are required for both
MI2S and PCM setup.
Signed-off-by: Srinivas Kandagatla
Reviewed-and-tested-by: Rohit kumar
---
sound/soc/qcom/qdsp6/q6afe.c | 171 +--
s
This patch adds support to APR bus (Asynchronous Packet Router) driver.
APR driver is made as a bus driver so that the apr devices can added removed
more dynamically depending on the state of the services on the dsp.
APR is used for communication between application processor and QDSP to
use servic
This patch adds support to 4 MI2S ports on LPASS.
Signed-off-by: Srinivas Kandagatla
Reviewed-and-tested-by: Rohit kumar
---
sound/soc/qcom/qdsp6/q6afe.c | 224 +++
sound/soc/qcom/qdsp6/q6afe.h | 13 +++
2 files changed, 237 insertions(+)
diff --git a/s
This patch adds support to 6 SLIMBus AFE ports, which are used as
backend dais.
Signed-off-by: Srinivas Kandagatla
Reviewed-and-tested-by: Rohit kumar
---
sound/soc/qcom/qdsp6/q6afe.c | 129 +++
sound/soc/qcom/qdsp6/q6afe.h | 14 +
2 files changed, 1
On Wed, Apr 25, 2018 at 11:06 AM, Ganesh Goudar wrote:
> Hi,
>
> Kindly pull the new firmware from the following URL.
> git://git.chelsio.net/pub/git/linux-firmware.git for-upstream
>
> Thanks
> Ganesh
>
> The following changes since commit 0caed67f661bfa9552b636d1e4af379eda75ed67:
>
> cxgb4: up
This patch adds support to Q6AFE (Audio Front End) module on Q6DSP.
AFE module sits right at the other end of cpu where the codec/audio
devices are connected.
AFE provides abstraced interfaces to both hardware and virtual devices.
Each AFE tx/rx port can be configured to connect to one of the har
This patch add DT bindings for Q6CORE DSP module.
Signed-off-by: Srinivas Kandagatla
Reviewed-and-tested-by: Rohit kumar
Reviewed-by: Rob Herring
---
.../devicetree/bindings/sound/qcom,q6core.txt | 21 +
1 file changed, 21 insertions(+)
create mode 100644 Documentati
This patch adds some common helper functions like translating dsp error
to linux error codes and channel mappings etc.
These functions are used in all the following qdsp6 drivers.
Signed-off-by: Srinivas Kandagatla
Reviewed-and-tested-by: Rohit kumar
---
sound/soc/qcom/Kconfig | 1
This patch add DT bindings for ASM (Audio Stream Manager) DSP module.
Signed-off-by: Srinivas Kandagatla
Reviewed-and-tested-by: Rohit kumar
Reviewed-by: Rob Herring
---
.../devicetree/bindings/sound/qcom,q6asm.txt | 33 ++
include/dt-bindings/sound/qcom,q6asm.h
This patch adds support to core apr service, which is used to query
status of other static and dynamic services on the dsp.
Signed-off-by: Srinivas Kandagatla
Reviewed-and-tested-by: Rohit kumar
---
sound/soc/qcom/Kconfig| 4 +
sound/soc/qcom/qdsp6/Makefile | 1 +
sound/soc/qcom/qds
On 05/01/2018 03:53 AM, Roger Pau Monné wrote:
On Mon, Apr 30, 2018 at 02:07:43PM -0400, Boris Ostrovsky wrote:
On 04/30/2018 12:57 PM, Roger Pau Monné wrote:
On Mon, Apr 30, 2018 at 12:23:36PM -0400, Boris Ostrovsky wrote:
Latest binutils release (2.29.1) will no longer allow proper computa
vunmap does page table clear operations twice in the
case when DEBUG_PAGEALLOC_ENABLE_DEFAULT is enabled.
So, clean up the code as that is unintended.
As a perf gain, we save few us. Below ftrace data was
obtained while doing 1 MB of vmalloc/vfree on ARM64
based SoC *without* this patch applied.
This patch add DT bindings for ADM (Audio Device Manager) DSP module.
This module implements mixer controls to setup the connections between
AFE ports and ASM streams.
Signed-off-by: Srinivas Kandagatla
Reviewed-and-tested-by: Rohit kumar
Reviewed-by: Rob Herring
---
.../devicetree/bindings/so
This patch add dt bindings for Qualcomm APR (Asynchronous Packet Router)
bus driver. This bus is used for communicating with DSP which provides
audio and various other services to cpu.
Signed-off-by: Srinivas Kandagatla
Reviewed-by: Rob Herring
---
.../devicetree/bindings/soc/qcom/qcom,apr.txt
Two issues here:
1) Use case (which I have)
2) Permissions
1) Use case
I am trying to build a backup system. To avoid duplication of files
over multiple backups I take an Md5 check sum of file contents. Files
with the same sum are hardlinked together. Files are linked in to a
standard directo
Hi Enric,
On Mon, Apr 30, 2018 at 03:14:02PM +0200, Enric Balletbo i Serra wrote:
> From: Sameer Nanda
>
> This driver gets various bits of information about what is connected to
> USB PD ports from the EC and converts that into power_supply properties.
>
> Signed-off-by: Sameer Nanda
> Signed
Hi Lorenzo,
On Tuesday 01 May 2018 05:24 PM, Lorenzo Pieralisi wrote:
> On Tue, May 01, 2018 at 03:37:47PM +0530, Kishon Vijay Abraham I wrote:
>> Hi Lorenzo,
>>
>> On Thursday 26 April 2018 10:26 PM, Lorenzo Pieralisi wrote:
>>> On Tue, Apr 24, 2018 at 02:44:40PM +0100, Gustavo Pimentel wrote:
>>
Michal Suchánek writes:
> On Tue, 24 Apr 2018 14:15:55 +1000
> Michael Ellerman wrote:
>
>> From: Michal Suchanek
>>
>> Based on the RFI patching. This is required to be able to disable the
>> speculation barrier.
>
> why do you not patch the nospec barrier which is included as part of
> the RF
On Mon, Apr 30, 2018 at 11:08:42PM +0200, Paul Kocialkowski wrote:
> Hi,
>
> Le samedi 21 avril 2018 à 09:34 -0500, Bin Liu a écrit :
> > Okay, this came down to an argument that whether we should require
> > loading a gadget driver on a dual-role port to work in host mode,
> > which is currently
+static int
+parse_events__set_leader_for_uncore_aliase(char *name, struct list_head *list,
+ struct parse_events_state
*parse_state)
+{
+ struct perf_evsel *evsel, *leader;
+ uintptr_t *leaders;
+ bool is_leader = true;
+ int i,
From: Doug Berger
The constants defined in this file are equally useful in assembly and C
source files. The arm64 architecture version of this file allows
inclusion in both assembly and C source files, so this this commit adds
that capability to the arm architecture version so that the constants
Add the initialization of CNTVOFF for sun8i-a83t.
For boot CPU, create a new machine that handles this
function's call in an "init_early" callback. We need to initialize
CNTVOFF before the arch timer's initialization otherwise, it will
not be taken into account and fails to boot correctly.
Because
Add the use of enable-method property for SMP support which allows
to handle the SMP support for this specific SoC.
This commit adds enable-method properties to all CPU nodes.
Signed-off-by: Mylène Josserand
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 8
1 file changed, 8 insertions(+)
di
Hello everyone,
This is a V8 of my series that adds SMP support for Allwinner sun8i-a83t.
Based on sunxi's tree, sunxi/for-next branch.
Depends on a patch from Doug Berger that allows to include the "cpu-type"
header on assembly files that I included in my series (patch 01).
If you have any remar
To prepare the support of sun8i-a83t, add a field in the smp_data
structure to know if we are on sun9i-a80 or sun8i-a83t.
Add also a global variable to retrieve which architecture we are
having.
Signed-off-by: Mylène Josserand
---
arch/arm/mach-sunxi/mc_smp.c | 4
1 file changed, 4 inserti
Now that a common function is available for CNTVOFF's
initialization, let's convert shmobile-apmu code to use
this function.
Signed-off-by: Mylène Josserand
Reviewed-by: Geert Uytterhoeven
Tested-by: Geert Uytterhoeven
---
arch/arm/mach-shmobile/common.h | 1 -
arch/arm/mach-shmobile
Add the support for A83T.
A83T SoC has an additional register than A80 to handle CPU configurations:
R_CPUS_CFG. Information about the register comes from Allwinner's BSP
driver.
An important difference is the Power Off Gating register for clusters
which is BIT(4) in case of SUN9I-A80 and BIT(0) i
To prepare the support for sun8i-a83t, rename the macro that handles
the power-off of clusters because it is different from sun9i-a80 to
sun8i-a83t.
The power off register for clusters are different from a80 and a83t.
Signed-off-by: Mylène Josserand
Acked-by: Maxime Ripard
Reviewed-by: Chen-Yu
The R_CPUCFG is a collection of registers needed for SMP bringup
on clusters and cluster's reset.
For the moment, documentation about this register is found in
Allwinner's code only.
Signed-off-by: Mylène Josserand
Reviewed-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 5 +
1 fil
Move the assembly code for cluster cache enabling and resuming
into an assembly file instead of having it directly in C code.
Remove the CFLAGS because we are using the ARM directive "arch"
instead.
Signed-off-by: Mylène Josserand
---
arch/arm/mach-sunxi/Makefile | 2 +-
arch/arm/mach-sunxi/h
The CNTVOFF register from arch timer is uninitialized.
It should be done by the bootloader but it is currently not the case,
even for boot CPU because this SoC is booting in secure mode.
It leads to an random offset value meaning that each CPU will have a
different time, which isn't working very we
Add CCI-400 node and control-port on CPUs needed by SMP bringup.
Signed-off-by: Mylène Josserand
Reviewed-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 41 +++
1 file changed, 41 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi
b/arch
As we found in sun9i-a80, CPUCFG is a collection of registers that are
mapped to the SoC's signals from each individual processor core and
associated peripherals.
These registers are used for SMP bringup and CPU hotplugging.
Signed-off-by: Mylène Josserand
Reviewed-by: Chen-Yu Tsai
---
arch/ar
On 05/01/2018 04:00 AM, Roger Pau Monné wrote:
On Mon, Apr 30, 2018 at 12:23:39PM -0400, Boris Ostrovsky wrote:
And without it we can't use _BOOT_XX macros any longer so define new ones.
Not being that familiar with Linux internals I'm not sure I see the
benefit of this. Isn't there a risk t
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