On Tue, Apr 17, 2018 at 2:11 PM, Jiri Kosina wrote:
> On Mon, 16 Apr 2018, Dmitry Torokhov wrote:
>
>> So what is happening with this series? I think we should get it them
>> in; there is really no reason for bumping ABS_MISC till it gets into
>> ABS_MT_* range on some devices that are out there.
On Tue, Apr 17, 2018 at 04:02:33AM -0500, Vicentiu Galanopulo wrote:
> A search of the dev-addr property is done in of_mdiobus_register.
> If the property is found in the PHY node, of_mdiobus_register_vend_spec_phy()
> is called. This is a wrapper function for of_mdiobus_register_phy()
> which find
On Tue, Apr 17, 2018 at 10:54:37AM +0200, Thomas Gleixner wrote:
> The question was rather to have a list of PCI IDs for those chipsets which
> have the problem and set the 'disable' flag only for those. That makes a lot
> more sense than making a list of new chips which disable the disable flag.
RTC_LIB includes a generic function to convert
RTC data into struct rtc_time. Use it and remove to_tm().
Signed-off-by: Christophe Leroy
---
arch/powerpc/Kconfig| 1 +
arch/powerpc/include/asm/time.h | 1 -
arch/powerpc/kernel/rtas-proc.c | 4 +--
arch/powe
On Tue, Apr 17, 2018 at 7:42 AM, Phil Edworthy
wrote:
> The DesignWare GPIO IP can be configured for either 1 interrupt or 1
> per GPIO in port A, but the driver currently only supports 1 interrupt.
> See the DesignWare DW_apb_gpio Databook description of the
> 'GPIO_INTR_IO' parameter.
>
> This c
Store user space frame-pointer value (BP register) into Perf trace
on a sample for a process so the value becomes available when
unwinding call stacks for functions gaining event samples.
Test executable for the example below was compiled with frame pointer
support enabled:
g++ -o futex-fp -f
On Mon, Apr 16, 2018 at 5:52 PM, Eric Anholt wrote:
> The GPU subsystem node was a workaround to have a central device to
> bind V3D and display to. Following the lead of 246774d17fc0
> ("drm/etnaviv: remove the need for a gpu-subsystem DT node"), remove
> the subsystem node usage and just create
Hi!
I naively thought that since there was support for both nxp,tda19988 (in
the tda998x driver) and the atmel-hlcdc, things would be a smooth ride.
But it wasn't, so I started looking around, and found some missing
pieces in the tilcdc driver. I "stole" some things and made it work
for my use cas
With bus-type/bus-width properties in the endpoint nodes, the video-
interface of the connection can be specified for cases where the
heuristic fails to select the correct output mode. This can happen
e.g. if not all RGB pins are routed on the PCB; the driver has no
way of knowing this, and needs t
Hi thomas:
Sorry, i don't receive yesterday email, i think the ping email is lost,
so bad me.
Anyway，have you some suggestions for this little patch? i really need
your help.
Regards,
czou
On 2018/4/17 下午6:22, Thomas Gleixner wrote:
On Tue, 17 Apr 2018, zoucao-ipc wrote:
ping?
You already
Start list of actual chips compatible with "lvds-encoder".
Reviewed-by: Laurent Pinchart
Reviewed-by: Rob Herring
Signed-off-by: Peter Rosin
---
.../devicetree/bindings/display/bridge/lvds-transmitter.txt | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git
a/Documen
Add a central function to parse a node according to the video
interface binding and get a media bus format.
Start with only supporting a very limited set of a few basic media
bus formats.
Signed-off-by: Peter Rosin
---
drivers/gpu/drm/drm_of.c | 38 ++
includ
When the of-graph points to a tda998x-compatible HDMI encoder, register
as a component master and bind to the encoder/connector provided by
the tda998x driver.
Signed-off-by: Peter Rosin
---
drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c | 81 --
drivers/gpu/drm/atmel-hlcdc/atmel_
Bump the minor version while at it.
Signed-off-by: Peter Rosin
---
drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c
b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c
index 8523c40fac94.
This beats the heuristic that the connector is involved in what format
should be output for cases where this fails.
E.g. if there is a bridge that changes format between the encoder and the
connector, or if some of the RGB pins between the lcd controller and the
encoder are not routed on the PCB.
On 04/17/2018 05:47 AM, Arnd Bergmann wrote:
On Mon, Apr 16, 2018 at 11:06 AM, Greentime Hu wrote:
2018-04-16 11:58 GMT+08:00 Guenter Roeck :
This built failure is because the toolchain version you used is not
supported the latest intrinsic function/macro.
We are sending the latest patchset no
The TPM burstcount and status commands are supposed to return very
quickly [1][2]. This patch further reduces the TPM poll sleep time to usecs
in get_burstcount() and wait_for_tpm_stat() by calling usleep_range()
directly.
After this change, performance on a TPM 1.2 with an 8 byte burstcount for
1
The TPM polling code in tpm_transmit sleeps in each loop iteration for
5 msecs. However, the TPM might return earlier, and thus waiting for
5 msecs adds an unnecessary delay. This patch reduces the polling sleep
time in tpm_transmit() from 5 msecs to 1 msecs.
Additionally, this patch renames TPM_P
The existing TPM polling code sleeps in each loop iteration for time in
msecs ranging from 1 msecs to 5 msecs. However, many of the TPM commands
complete much faster, resulting in unnecessary delays.
This set of patches identifies such iterations and optimizes the sleep
time. The first patch repla
On Mon, Apr 16, 2018 at 6:12 PM, Jae Hyun Yoo
wrote:
> On 4/16/2018 11:10 AM, Rob Herring wrote:
>>
>> On Tue, Apr 10, 2018 at 11:32:06AM -0700, Jae Hyun Yoo wrote:
>>>
>>> This commit adds a dt-bindings document of PECI adapter driver for Aspeed
>>> AST24xx/25xx SoCs.
[...]
>>> +- clocks
It is not a good idea to try to fit all types of applications in the
same input report. There are a lot of devices that are needing
the quirk HID_MULTI_INPUT but this quirk doesn't match the actual HID
description as it is based on the report ID.
Given that most devices with MULTI_INPUT I can thin
Given that we create one input node per application, we should name
the input node accordingly to not lose userspace.
Signed-off-by: Benjamin Tissoires
---
drivers/hid/hid-input.c | 64 ++--
drivers/hid/hid-multitouch.c | 30 +++--
inc
FYI, these are the two patches I mentioned earlier.
checkpatch.pl still complains about them so do not merge them right away, but
this should give you a better idea.
Also, this is the tip of my local tree, so there is a high chance it doesn't
apply cleanly on your for-next branch.
Cheers,
Benjami
Hi James,
On 16/04/18 21:22, James Hogan wrote:
On Thu, Mar 29, 2018 at 10:28:23AM +0100, Matt Redfearn wrote:
@@ -260,6 +260,11 @@
jr ra
andiv1, a2, STORMASK
This patch looks good, well spotted!
But whats that v1 write about? Any ideas? Seems to go b
Hi James,
On 16/04/18 23:13, James Hogan wrote:
On Thu, Mar 29, 2018 at 10:28:24AM +0100, Matt Redfearn wrote:
The __clear_user function is defined to return the number of bytes that
could not be cleared. From the underlying memset / bzero implementation
this means setting register a2 to that n
On Sun, Apr 15, 2018 at 10:57:33AM -0500, Eric W. Biederman wrote:
>
> Call clear_siginfo to ensure every stack allocated siginfo is properly
> initialized before being passed to the signal sending functions.
>
> Note: It is not safe to depend on C initializers to initialize struct
> siginfo on t
On Tue, Apr 17, 2018 at 12:04:18PM +0100, Michel Pollet wrote:
> This documents the RZ/N1 bindings for the RZN1D-DB board.
>
> Signed-off-by: Michel Pollet
> ---
> Documentation/devicetree/bindings/arm/shmobile.txt | 5 -
> 1 file changed, 4 insertions(+), 1 deletion(-)
Please add acks/revi
On 04/17/2018 04:06 AM, Miroslav Benes wrote:
> On Mon, 16 Apr 2018, Petr Mladek wrote:
>
>> On Mon 2018-04-16 13:33:55, Miroslav Benes wrote:
>>> On Fri, 13 Apr 2018, Joe Lawrence wrote:
Thanks for reviewing. I'll hold off on posting v4 until Petr (and
others) get a chance to comment.
From: Joerg Roedel
The walk_pte_level() function just uses __va to get the
virtual address of the PTE page, but that breaks when
the PTE page is not in the direct mapping with HIGHPTE=y.
The result is an unhandled kernel paging request at some
random address when accessing the current_kernel or
On Tue, 2018-04-17 at 14:53 +0300, Kirill Tkhai wrote:
> Hi, Jeff,
>
> On 17.04.2018 14:42, Jeff Layton wrote:
> > On Thu, 2018-04-05 at 14:58 +0300, Kirill Tkhai wrote:
> > > I observed the following deadlock between them:
> > >
> > > [task 1] [task 2]
On 04/16/2018 08:11 AM, Cornelia Huck wrote:
On Mon, 16 Apr 2018 10:44:53 +0200
Pierre Morel wrote:
On 15/04/2018 23:22, Tony Krowiak wrote:
If the AP instructions are not available on the linux host, then
AP devices can not be interpreted by the SIE. The AP bus has a
function it uses to dete
On Tue, Apr 17, 2018 at 01:41:44PM +0200, Jan Kara wrote:
>On Mon 16-04-18 17:23:30, Sasha Levin wrote:
>> On Mon, Apr 16, 2018 at 07:06:04PM +0200, Pavel Machek wrote:
>> >On Mon 2018-04-16 16:37:56, Sasha Levin wrote:
>> >> On Mon, Apr 16, 2018 at 12:30:19PM -0400, Steven Rostedt wrote:
>> >> >On
> -Original Message-
> From: linux-edac-ow...@vger.kernel.org ow...@vger.kernel.org> On Behalf Of Johannes Hirte
> Sent: Monday, April 16, 2018 7:56 AM
> To: Ghannam, Yazen
> Cc: linux-e...@vger.kernel.org; linux-kernel@vger.kernel.org; b...@suse.de;
> tony.l...@intel.com; x...@kernel.org
On Tue, 17 Apr 2018, 'Christoph Hellwig' wrote:
> On Tue, Apr 17, 2018 at 10:54:37AM +0200, Thomas Gleixner wrote:
> > The question was rather to have a list of PCI IDs for those chipsets which
> > have the problem and set the 'disable' flag only for those. That makes a lot
> > more sense than maki
Hi Rob,
On 16/04/2018 22:43, Rob Herring wrote:
> On Mon, Apr 16, 2018 at 03:37:52PM +0100, Gustavo Pimentel wrote:
>> Add device tree binding documentation for the Endpoint in PCIe Designware
>> driver.
>>
>> Signed-off-by: Gustavo Pimentel
>> ---
>> Change v1->v2:
>> - Add a missing log descri
With commit ce88313069c36eef80f21fd7 ("arch/sh: make the DMA mapping
operations observe dev->dma_pfn_offset") the generic DMA allocation
function on which the SH 'dma_alloc_coherent()' function relies on,
access the 'dma_pfn_offset' field of struct device.
Unfortunately the 'dma_generic_alloc_cohe
Use new return type vm_fault_t for fault handler. For
now, this is just documenting that the function returns
a VM_FAULT value rather than an errno. Once all instances
are converted, vm_fault_t will become a distinct type.
Reference id -> 1c8f422059ae ("mm: change return type to
vm_fault_t")
Sign
The "generic" implementation of of_node_to_nid is only used by
arm64 and only in built-in code, so remove its export. Any
device with a struct device should be able to use dev_to_node()
instead. Also, exporting of_node_to_nid doesn't actually work if
we build a module on an arch that doesn't select
Just a drive-by nit:
On 10/04/18 19:32, Jae Hyun Yoo wrote:
[...]
+#define PECI_CTRL_SAMPLING_MASK GENMASK(19, 16)
+#define PECI_CTRL_SAMPLING(x) (((x) << 16) & PECI_CTRL_SAMPLING_MASK)
+#define PECI_CTRL_SAMPLING_GET(x) (((x) & PECI_CTRL_SAMPLING_MASK) >> 16)
FWIW, already provid
Enable pwm3 input capture on stm32f429i-eval, by using DMA.
Signed-off-by: Fabrice Gasnier
Reviewed-by: Benjamin Gaignard
---
arch/arm/boot/dts/stm32429i-eval.dts | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/boot/dts/stm32429i-eval.dts
b/arch/arm/boot/dts/stm32429i-eval.dts
This series adds support for capture to stm32-pwm driver.
Capture is based on DMAs.
- First two patches add support for requesting DMAs to MFD core
- Next three patches add support for capture to stm32-pwm driver
- This has been tested on stm32429i-eval board.
---
Changes in v5:
- update patch 2 (
Em Mon, Apr 16, 2018 at 10:04:53PM +, Stephane Eranian escreveu:
> Hi,
>
> I am trying to understand what the exclude_idle event attribute is supposed
> to accomplish.
> As per the definition in the header file:
>
> exclude_idle : 1, /* don't count when idle */
>
> Naively, I thought
The signatureValue field of a X.509 certificate is encoded as a BIT STRING.
For RSA signatures this BIT STRING is of so-called primitive subtype, which
contains a u8 prefix indicating a count of unused bits in the encoding.
We have to strip this prefix from signature data, just as we already do fo
On Tue, Apr 17, 2018 at 02:49:24PM +0200, Michal Hocko wrote:
>On Tue 17-04-18 14:24:54, Petr Mladek wrote:
>[...]
>> Back to the trend. Last week I got autosel mails even for
>> patches that were still being discussed, had issues, and
>> were far from upstream:
>>
>> https://lkml.kernel.org/r/dm5p
Using input prescaler, capture unit will trigger DMA once every
configurable /2, /4 or /8 events (rising edge). This helps improve
period (only) capture accuracy at high rates.
Signed-off-by: Fabrice Gasnier
Reviewed-by: Benjamin Gaignard
Acked-by: Thierry Reding
---
Changes in v2:
- Adopt DMA
Add support for PMW input mode on pwm-stm32. STM32 timers support
period and duty cycle capture as long as they have at least two PWM
channels. One capture channel is used for period (rising-edge), one
for duty-cycle (falling-edge).
When there's only one channel available, only period can be captur
Currently, capture is based on timeout window to configure prescaler.
PWM capture framework provides 1s window at the time of writing.
There's place for improvement, after input signal has been captured once:
- Finer tune counter clock prescaler, by using 1st capture result (with
arbitrary margin)
STM32 Timers can support up to 7 DMA requests:
- 4 channels, update, compare and trigger.
Optionally request part, or all DMAs from stm32-timers MFD core.
Also add routine to implement burst reads using DMA from timer registers.
This is exported. So, it can be used by child drivers, PWM capture
fo
Add support for DMAs to STM32 timers. STM32 Timers can support up to 7
dma requests: up to 4 channels, update, compare and trigger.
DMAs may be used to transfer data from pwm capture for instance.
DMA support is made optional, PWM capture support is also an option.
This is much more wise system-wid
Em Thu, Nov 23, 2017 at 04:15:36PM +0100, Peter Zijlstra escreveu:
> On Thu, Nov 23, 2017 at 11:42:20AM -0300, Arnaldo Carvalho de Melo wrote:
> > What is wrong with perf_event_attr.exclude_idle? :-)
>
> Neither task- nor cpu-clock actually implement that..
>
> Something like the _completely_unte
Use new return type vm_fault_t for fault handler. For
now, this is just documenting that the function returns
a VM_FAULT value rather than an errno. Once all instances
are converted, vm_fault_t will become a distinct type.
Reference id -> 1c8f422059ae ("mm: change return type to
vm_fault_t")
Prev
On Tue, Apr 17, 2018 at 02:24:54PM +0200, Petr Mladek wrote:
>Back to the trend. Last week I got autosel mails even for
>patches that were still being discussed, had issues, and
>were far from upstream:
>
> https://lkml.kernel.org/r/dm5pr2101mb1032ab19b489d46b717b50d4fb...@dm5pr2101mb1032.namprd21.
stm32mp157c evaluation board has following PWM pins available on GPIO
expansion connector:
- TIM2_CH4 (PA3)
- TIM8_CH4 (PI2)
- TIM12_CH1 (PH6)
Signed-off-by: Fabrice Gasnier
---
arch/arm/boot/dts/stm32mp157-pinctrl.dtsi | 27 +++
1 file changed, 27 insertions(+)
diff --g
Add PWM and trigger support to stm32mp157c.
Signed-off-by: Fabrice Gasnier
---
arch/arm/boot/dts/stm32mp157c.dtsi | 283 +
1 file changed, 283 insertions(+)
diff --git a/arch/arm/boot/dts/stm32mp157c.dtsi
b/arch/arm/boot/dts/stm32mp157c.dtsi
index bc3eddc..1
Commit-ID: d6ef1f194b7569af8b8397876dc9ab07649d63cb
Gitweb: https://git.kernel.org/tip/d6ef1f194b7569af8b8397876dc9ab07649d63cb
Author: Joerg Roedel
AuthorDate: Tue, 17 Apr 2018 15:27:16 +0200
Committer: Thomas Gleixner
CommitDate: Tue, 17 Apr 2018 15:43:01 +0200
x86/mm: Prevent kernel
This series adds support for STM32 timers to stm32mp157c. These
timers can act PWM, trigger and/or encoder.
Populate stm32mp157c SOC and ed1/ev1 boards.
Fabrice Gasnier (4):
ARM: dts: stm32: add timers support to stm32mp157c
ARM: dts: stm32: add PWM pins used on stm32mp157c-ev1 board
ARM: dt
Commit-ID: 1340ccfa9a9afefdbab90d7935d4ed19817e37c2
Gitweb: https://git.kernel.org/tip/1340ccfa9a9afefdbab90d7935d4ed19817e37c2
Author: Alison Schofield
AuthorDate: Fri, 6 Apr 2018 17:21:30 -0700
Committer: Thomas Gleixner
CommitDate: Tue, 17 Apr 2018 15:39:55 +0200
x86,sched: Allow to
Hi Vijendar,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on sound/for-next]
[also build test ERROR on v4.17-rc1 next-20180417]
[cannot apply to asoc/for-next]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url
On 2018-04-17 15:54, Lars-Peter Clausen wrote:
> On 04/17/2018 01:43 PM, Radhey Shyam Pandey wrote:
>> Hi Vinod,
>>
>>> -Original Message-
>>> From: Vinod Koul [mailto:vinod.k...@intel.com]
>>> Sent: Wednesday, April 11, 2018 2:39 PM
>>> To: Radhey Shyam Pandey
>>> Cc: dan.j.willi...@intel
Enable timer 6 on stm32mp157c-ed1 that can serve as trigger for
ADC for instance.
Signed-off-by: Fabrice Gasnier
---
arch/arm/boot/dts/stm32mp157c-ed1.dts | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/stm32mp157c-ed1.dts
b/arch/arm/boot/dts/stm32mp157c-ed1.dts
ind
stm32mp157c evaluation board has TIM2_CH4, TIM8_CH4 and TIM12_CH1
available on GPIO expansion connector.
Add PWM and associated triggers (for ADC/DAC) on these timers.
Keep them disabled so these pins can be used as GPIOs by default.
Signed-off-by: Fabrice Gasnier
---
arch/arm/boot/dts/stm32mp15
On 04/17/2018 07:34 AM, Cornelia Huck wrote:
On Sun, 15 Apr 2018 17:22:12 -0400
Tony Krowiak wrote:
Introduces a new function to reset the crypto attributes for all
vcpus whether they are running or not. Each vcpu in KVM will
be removed from SIE prior to resetting the crypto attributes in its
On Tue, 10 Apr 2018, zou...@linux.alibaba.com wrote:
> From: zoucao
Interesting from ... Please use your real mail address for this.
> Normally every BIOS reserved memory is used for some features, we can't
> use them, but in some conditions, users can ensure some BIOS memories
> are not used a
Hi Rob,
On 16/04/2018 22:39, Rob Herring wrote:
> On Mon, Apr 16, 2018 at 03:37:49PM +0100, Gustavo Pimentel wrote:
>> Replaces "ctrlreg" reg-name by "dbi" to be coherent with similar drivers,
>> however it still be compatible with any previous DT that uses the old
>> reg-name.
>>
>> Replaces the
On the db410c 96boards platform we have a TC7USB40MU on the board
to mux the D+/D- lines coming from the controller between a micro
usb "device" port and a USB hub for "host" roles[1]. During a
role switch, we need to toggle this mux to forward the D+/D-
lines to either the port or the hub. Add the
From: Rafal Ozieblo
Date: Tue, 17 Apr 2018 08:59:35 +
> If IP supports RSC and skb has 2B reserved for alignment we end up
> with none packets receive correctly (2B missing in the each skb).
> We can either leave few customers without support in Linux driver or
> let them use the driver with
The chipidea usb controller may be connected, in some platforms,
to an external mux to toggle between different usb ports for
different roles (host and device).
The mux-controller property, if set, binds the chipidea usb
controller with a mux for this use.
Signed-off-by: Yossi Mansharoff
---
Do
Hello,
On Tue, 17 Apr 2018 15:35:23 +0200, Jacopo Mondi wrote:
> With commit ce88313069c36eef80f21fd7 ("arch/sh: make the DMA mapping
> operations observe dev->dma_pfn_offset") the generic DMA allocation
> function on which the SH 'dma_alloc_coherent()' function relies on,
> access the 'dma_pfn_of
Use new return type vm_fault_t for fault handler. For
now, this is just documenting that the function returns
a VM_FAULT value rather than an errno. Once all instances
are converted, vm_fault_t will become a distinct type.
Reference id -> 1c8f422059ae ("mm: change return type to
vm_fault_t")
Sign
We currently have three device nodes for the same USB hardware
block, as evident by the reuse of the same reg address multiple
times. Now that the chipidea driver fully supports OTG with the
MSM wrapper we can collapse all these nodes into one USB device
node, reflecting the true nature of the hard
Whack-a-mole some more occurrences of status in examples.
Cc: Vinod Koul
Cc: Mark Rutland
Cc: Ralf Baechle
Cc: James Hogan
Cc: Ulf Hansson
Cc: David Woodhouse
Cc: Brian Norris
Cc: Boris Brezillon
Cc: Marek Vasut
Cc: Richard Weinberger
Cc: Matthias Brugger
Cc: Tanmay Inamdar
Cc: Bjorn H
On Tuesday 17 April 2018 03:59 PM, Bartosz Golaszewski wrote:
> From: Bartosz Golaszewski
>
> Currently aemif is supported in two places separately. By the platform
> driver in drivers/memory and by a hand crafted driver in mach-davinci.
>
> We want to drop the latter but also keep the legacy mo
Em Tue, Apr 17, 2018 at 09:57:50AM +0200, Jiri Olsa escreveu:
> On Tue, Apr 17, 2018 at 09:43:43AM +0530, Ravi Bangoria wrote:
> > First patch is a trivial error message fix. Second and third
> > adds new options --list and --purge-all to 'buildid-cache'
> > subcommand.
> >
> > v2 changes:
> > -
On 04/17/2018 03:46 PM, Peter Ujfalusi wrote:
> On 2018-04-17 15:54, Lars-Peter Clausen wrote:
>> On 04/17/2018 01:43 PM, Radhey Shyam Pandey wrote:
>>> Hi Vinod,
>>>
-Original Message-
From: Vinod Koul [mailto:vinod.k...@intel.com]
Sent: Wednesday, April 11, 2018 2:39 PM
>>>
From: Nicolas Dechesne
Date: Tue, 17 Apr 2018 14:03:26 +0200
> To ensure that qrtr can be loaded automatically, when needed, if it is
> compiled
> as module.
>
> Signed-off-by: Nicolas Dechesne
Applied.
2018-04-17 14:41 GMT+02:00 Bartosz Golaszewski :
> 2018-04-17 14:36 GMT+02:00 Bartosz Golaszewski :
>> 2018-04-17 12:53 GMT+02:00 Sekhar Nori :
>>> Hi Bartosz,
>>>
>>> On Tuesday 17 April 2018 03:59 PM, Bartosz Golaszewski wrote:
From: Bartosz Golaszewski
This is the first part of c
Hi Thomas,
On Tue, Apr 17, 2018 at 03:54:07PM +0200, Thomas Petazzoni wrote:
> Hello,
>
> On Tue, 17 Apr 2018 15:35:23 +0200, Jacopo Mondi wrote:
> > With commit ce88313069c36eef80f21fd7 ("arch/sh: make the DMA mapping
> > operations observe dev->dma_pfn_offset") the generic DMA allocation
> > fun
On 17.04.2018 16:31, Jeff Layton wrote:
> On Tue, 2018-04-17 at 14:53 +0300, Kirill Tkhai wrote:
>> Hi, Jeff,
>>
>> On 17.04.2018 14:42, Jeff Layton wrote:
>>> On Thu, 2018-04-05 at 14:58 +0300, Kirill Tkhai wrote:
I observed the following deadlock between them:
[task 1]
The __clear_user function is defined to return the number of bytes that
could not be cleared. From the underlying memset / bzero implementation
this means setting register a2 to that number on return. Currently if a
page fault is triggered within the memset_partial block, the value
loaded into a2 o
On Tue, Apr 17, 2018 at 08:32:33AM +, Thiebaud Weksteen wrote:
> On Tue, Apr 17, 2018 at 5:02 AM Jason Gunthorpe wrote:
>
> > On Thu, Apr 12, 2018 at 12:13:47PM +0200, Thiebaud Weksteen wrote:
> > > Signed-off-by: Thiebaud Weksteen
> > > drivers/char/tpm/tpm_eventlog_of.c | 4 ++--
> > > 1
On Thu, Apr 05, 2018 at 02:58:06PM +0300, Kirill Tkhai wrote:
> I observed the following deadlock between them:
>
> [task 1] [task 2] [task 3]
> kill_fasync() mm_update_next_owner()
> copy_process()
> spin_lock_irqsav
On Tue 17-04-18 12:39:32, Pavlos Parissis wrote:
> In one of our production servers where we run kernel version 4.14.32, I
> noticed
> the following:
OK, I was looking into this for some time and couldn't find a problem in
4.14.32 code. Can you try running a kernel with CONFIG_DEBUG_SLAB and
CONF
On Tue, Apr 17, 2018 at 01:07:17PM +0200, Michal Hocko wrote:
>On Tue 17-04-18 12:39:36, Greg KH wrote:
>> On Mon, Apr 16, 2018 at 11:28:44PM +0200, Jiri Kosina wrote:
>> > On Mon, 16 Apr 2018, Sasha Levin wrote:
>> >
>> > > I agree that as an enterprise distro taking everything from -stable
>> > >
Hi Jacopo,
Thanks for your patch!
On Tue, Apr 17, 2018 at 3:35 PM, Jacopo Mondi wrote:
> With commit ce88313069c36eef80f21fd7 ("arch/sh: make the DMA mapping
> operations observe dev->dma_pfn_offset") the generic DMA allocation
> function on which the SH 'dma_alloc_coherent()' function relies on
On Tue, Apr 17, 2018 at 08:47:16PM +0800, Tiwei Bie wrote:
> On Tue, Apr 17, 2018 at 03:17:41PM +0300, Michael S. Tsirkin wrote:
> > On Tue, Apr 17, 2018 at 10:51:33AM +0800, Tiwei Bie wrote:
> > > On Tue, Apr 17, 2018 at 10:11:58AM +0800, Jason Wang wrote:
> > > > On 2018年04月13日 15:15, Tiwei Bie w
Hi Guenter,
> [ ... ]
> > Ugh. Could you please keep that patch and apply this on top:
> >
> > diff --git a/mm/z3fold.c b/mm/z3fold.c
> > index c0bca6153b95..e8a80d044d9e 100644
> > --- a/mm/z3fold.c
> > +++ b/mm/z3fold.c
> > @@ -840,6 +840,7 @@ static int z3fold_reclaim_page(struct z3fold_pool
The label .Llast_fixup\@ is jumped to on page fault within the final
byte set loop of memset (on < MIPSR6 architectures). For some reason, in
this fault handler, the v1 register is randomly set to a2 & STORMASK.
This clobbers v1 for the calling function. This can be observed with the
following test
On Fri, Apr 13, 2018 at 05:29:08PM +0800, Baoquan He wrote:
> Hi Bjorn,
>
> There are changes I have made to solve 5-level conflict with
> kexec/kdump and also interface unification task, they will involve x86
> 64 only changes on these functions, I don't think we need remove them if
> without any
Assembly language within the MIPS kernel conventionally indents
instructions which are in a branch delay slot to make them easier to
see. Commit 8483b14aaa81 ("MIPS: lib: memset: Whitespace fixes") rather
inexplicably removed all of these indentations from memset.S. Reinstate
the convention for all
On Tue, Apr 17, 2018 at 12:57:12PM +0100, James Bottomley wrote:
> On Tue, 2018-04-17 at 04:47 -0700, Matthew Wilcox wrote:
> > On Tue, Apr 17, 2018 at 10:13:34AM +0100, James Bottomley wrote:
> > > On Sat, 2018-04-14 at 17:41 -0700, Matthew Wilcox wrote:
> > > > On Sat, Apr 14, 2018 at 06:44:19PM
Hi,
On Tue, Apr 17, 2018 at 07:27:42PM +0530, Souptick Joarder wrote:
> Use new return type vm_fault_t for fault handler. For
> now, this is just documenting that the function returns
> a VM_FAULT value rather than an errno. Once all instances
> are converted, vm_fault_t will become a distinct typ
The micromips implementation of bzero additionally clobbers registers t7
& t8. Specify this in the clobbers list when invoking bzero.
Reported-by: James Hogan
Fixes: 26c5e07d1478 ("MIPS: microMIPS: Optimise 'memset' core library
function.")
Cc: sta...@vger.kernel.org
Signed-off-by: Matt Redfearn
Partitions in HiKey960 are formatted as f2fs and squashfs.
f2fs is for userdata; squashfs is for system. Both partitions are required
by Android.
Signed-off-by: Li Wei
Signed-off-by: Zhangfei Gao
Signed-off-by: Guodong Xu
---
arch/arm64/configs/defconfig | 8
1 file changed, 8 inserti
add ufs node document for Hisilicon.
Signed-off-by: Li Wei
---
Documentation/devicetree/bindings/ufs/ufs-hisi.txt | 29 ++
.../devicetree/bindings/ufs/ufshcd-pltfrm.txt | 10 +---
2 files changed, 36 insertions(+), 3 deletions(-)
create mode 100644 Documentation/dev
This enable configs for Hisilicon Hi UFS driver.
Signed-off-by: Li Wei
Signed-off-by: Zhangfei Gao
Signed-off-by: Guodong Xu
---
arch/arm64/configs/defconfig | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index ecf613761e7
On Tuesday 17 April 2018 03:59 PM, Bartosz Golaszewski wrote:
> From: Bartosz Golaszewski
>
> We now have support for aemif & nand from board files. As an example
> add support for nand to da850-lcdk in legacy mode.
Hawkboard is a separate board of its own, although closely related to
LCDK. Lets
arm64: dts: add ufs node for Hisilicon.
Signed-off-by: Li Wei
---
arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 20
1 file changed, 20 insertions(+)
diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
index ec3eb8e33a3a..e9013d4
On Tue, 17 Apr 2018 09:47:58 -0400
Tony Krowiak wrote:
> On 04/17/2018 07:34 AM, Cornelia Huck wrote:
> > On Sun, 15 Apr 2018 17:22:12 -0400
> > Tony Krowiak wrote:
> >
> >> Introduces a new function to reset the crypto attributes for all
> >> vcpus whether they are running or not. Each vcpu i
This patchset adds driver support for UFS for Hi3660 SoC. It is verified on
HiKey960 board.
Li Wei (5):
scsi: ufs: add Hisilicon ufs driver code
dt-bindings: scsi: ufs: add document for hisi-ufs
arm64: dts: add ufs dts node
arm64: defconfig: enable configs for Hisilicon ufs
arm64: defco
On Fri, Apr 13, 2018 at 11:08:20AM +0200, Philipp Rudo wrote:
> Hi Bjorn,
>
> in recent patches AKASHI [1] and I [2] made some changes to the declarations
> you are touching and already removed some of the weak statements. The patches
> got accepted on linux-next and will (hopefully) be pulled for
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