On Sun, Apr 15, 2018 at 08:56:21PM +0200, Jesper Nilsson wrote:
> Some devices need an optional external gpio for controlling
> the PERST# signal to bring up for example a PCIe switch
> after a soft reset.
>
> Without this, some boards (the ARTPEC-6 master devboard)
> would not get the PCIe link b
On Mon, 2018-04-16 at 15:36 +0200, Benjamin Tissoires wrote:
> > > > +MODULE_LICENSE("GPL");
> > >
> > > The SPDX header says GPL-v2. And IIRC if there is the SPDX header
> > > you
> > > can drop the MODULE_LICENSE (not entirely sure though).
> >
> > Ack, will adjust and re-test.
>
> Actually, y
[+cc Keith, linux-nvme, LKML; another possible ASPM issue with Samsung
NVMe SSD 960 EVO]
On Mon, Apr 16, 2018 at 09:03:33PM +0530, Srinath Mannam wrote:
> On Sat, Apr 14, 2018 at 9:39 PM, Bjorn Helgaas wrote:
> > On Sat, Apr 14, 2018 at 09:04:05AM +0530, Srinath Mannam wrote:
> >> I am sorry, in
On Mon, Apr 16, 2018 at 10:32:19AM +0800, Ryder Lee wrote:
> Fulfill the pinmux macros for MT7623
>
> Signed-off-by: Ryder Lee
> ---
> include/dt-bindings/pinctrl/mt7623-pinfunc.h | 90
> +++-
> 1 file changed, 87 insertions(+), 3 deletions(-)
Reviewed-by: Rob Herring
On Mon, Apr 16, 2018 at 10:34:57AM +0100, Michel Pollet wrote:
> Add a special enable method for second CA8 of the Renesas RZ/N1D
> (R9A06G032).
>
> Signed-off-by: Michel Pollet
> ---
> Documentation/devicetree/bindings/arm/cpus.txt | 1 +
> 1 file changed, 1 insertion(+)
Reviewed-by: Rob Herri
This adds a new driver for the Redragon Asura keyboard. The Asura
keyboard contains an error in the HID descriptor which causes all
modifier keys to be mapped to left shift. Additionally, we suppress
the creation of a second, not working, keyboard device.
Signed-off-by: Robert Munteanu
---
drive
On Mon, Apr 16, 2018 at 03:37:49PM +0100, Gustavo Pimentel wrote:
> Replaces "ctrlreg" reg-name by "dbi" to be coherent with similar drivers,
> however it still be compatible with any previous DT that uses the old
> reg-name.
>
> Replaces the PCIe base address example by a real PCIe base address i
On Mon, Apr 16, 2018 at 03:37:52PM +0100, Gustavo Pimentel wrote:
> Add device tree binding documentation for the Endpoint in PCIe Designware
> driver.
>
> Signed-off-by: Gustavo Pimentel
> ---
> Change v1->v2:
> - Add a missing log description.
> - Add "snps,dw-pcie" compatible string followin
On Mon, Apr 16, 2018 at 05:34:06PM +0200, Fabian Mewes wrote:
> Update the example to use the compatible string including the
> vendor prefix instead of the ones deprecated in 3a872138e4b.
>
> Signed-off-by: Fabian Mewes
> ---
> Documentation/devicetree/bindings/iio/adc/mcp320x.txt |2 +-
>
On Mon, Apr 16, 2018 at 06:49:38PM +0200, Mark Jonas wrote:
> From: Zhu Yi
>
> Add Rohm BU21029 resistive touch panel controller support with I2C
> interface.
>
> Signed-off-by: Zhu Yi
> Signed-off-by: Mark Jonas
> Reviewed-by: Heiko Schocher
> ---
> Changes in v2:
> - make ABS_PRESSURE prop
Hi Michel,
On 04/16/2018 02:34 AM, Michel Pollet wrote:
> The Renesas RZ/N1D second CA7 is parked in a ROM pen at boot time, it
> requires a special enable method to get it started at boot time.
>
> Signed-off-by: Michel Pollet
Some few comments below. This patch should probably be re-ordered i
Device faults detected by IOMMU can be reported outside IOMMU
subsystem for further processing. This patch intends to provide
a generic device fault data such that device drivers can be
communicated with IOMMU faults without model specific knowledge.
The proposed format is the result of discussion
When Shared Virtual Address (SVA) is enabled for a guest OS via
vIOMMU, we need to provide invalidation support at IOMMU API and driver
level. This patch adds Intel VT-d specific function to implement
iommu passdown invalidate API for shared virtual address.
The use case is for supporting caching
For performance and debugging purposes, these trace events help
analyzing device faults and passdown invalidations that interact
with IOMMU subsystem.
E.g.
IOMMU::00:0a.0 type=2 reason=0 addr=0x007ff000 pasid=1
group=1 last=0 prot=1
Signed-off-by: Jacob Pan
---
drivers/iommu/iommu.c
PFSID should be used in the invalidation descriptor for flushing
device IOTLBs on SRIOV VFs.
Signed-off-by: Jacob Pan
---
drivers/iommu/dmar.c| 6 +++---
drivers/iommu/intel-iommu.c | 16 +++-
include/linux/intel-iommu.h | 5 ++---
3 files changed, 20 insertions(+), 7 delet
Hello Taniya,
On 04/16/2018 10:38 AM, Stephen Boyd wrote:
> Quoting Taniya Das (2018-04-13 19:36:41)
>> Add the RPMh clock driver to control the RPMh managed clock resources on
>> some of the Qualcomm Technologies, Inc. SoCs.
>>
>> Signed-off-by: David Collins
>> Signed-off-by: Amit Nischal
>
>
With the introduction of generic IOMMU device fault reporting API, we
can replace the private fault callback functions with standard function
and event data.
Signed-off-by: Jacob Pan
---
drivers/iommu/intel-svm.c | 7 +--
include/linux/intel-svm.h | 20 +++-
2 files changed,
vIOMMU passdown invalidation will be inclusive, PASID cache invalidation
includes TLBs. See Intel VT-d Specification Ch 6.5.2.2 for details.
Signed-off-by: Jacob Pan
---
drivers/iommu/intel-svm.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/iommu/intel-svm.c b/d
On Fri, Apr 13, 2018 at 03:05:03PM +0530, Gaurav Kohli wrote:
> During percpu_counter destroy, debug_object_free is calling
> twice which may create race. So removing once instance of call
> from debug_percpu_counter_deactivate.
I don't quite follow. Can you please elaborate how it can be called
On Mon, Apr 16, 2018 at 02:08:46PM -0600, Jonathan Corbet wrote:
> On Mon, 16 Apr 2018 17:45:01 +0200
> Thymo van Beers wrote:
>
> > Some lines used spaces instead of tabs at line start.
> > This can cause mangled lines in editors due to inconsistency.
> >
> > Replace spaces for tabs where appro
Signed-off-by: Jacob Pan
---
include/trace/events/iommu.h | 112 +++
1 file changed, 112 insertions(+)
diff --git a/include/trace/events/iommu.h b/include/trace/events/iommu.h
index 72b4582..e64eb29 100644
--- a/include/trace/events/iommu.h
+++ b/include/t
If the source device of a page request has its PASID table pointer
bound to a guest, the first level page tables are owned by the guest.
In this case, we shall let guest OS to manage page fault.
This patch uses the IOMMU fault reporting API to send fault events,
possibly via VFIO, to the guest OS.
This patch adds page response support for Intel VT-d.
Generic response data is taken from the IOMMU API
then parsed into VT-d specific response descriptor format.
Signed-off-by: Jacob Pan
---
drivers/iommu/intel-iommu.c | 47 +
include/linux/intel-iomm
When Shared Virtual Memory is exposed to a guest via vIOMMU, extended
IOTLB invalidation may be passed down from outside IOMMU subsystems.
This patch adds invalidation functions that can be used for additional
translation cache types.
Signed-off-by: Jacob Pan
---
drivers/iommu/dmar.c| 44
Some lines used spaces instead of tabs at line start.
This can cause mangled lines in editors due to inconsistency.
Replace spaces for tabs where appropriate.
Signed-off-by: Thymo van Beers
---
Changes in v2:
- Rebase against docs-next
- Fix indentation modifications
Documentation/admin-gu
When SRIOV VF device IOTLB is invalidated, we need to provide
the PF source ID such that IOMMU hardware can gauge the depth
of invalidation queue which is shared among VFs. This is needed
when device invalidation throttle (DIT) capability is supported.
This patch adds bit definitions for checking
Currently, dmar fault IRQ handler does nothing more than rate
limited printk, no critical hardware handling need to be done
in IRQ context.
For some use case such as vIOMMU, it might be useful to report
non-recoverable faults outside host IOMMU subsystem. DMAR fault
can come from both DMA and inter
When IO page faults are reported outside IOMMU subsystem, the page
request handler may fail for various reasons. E.g. a guest received
page requests but did not have a chance to run for a long time. The
irresponsive behavior could hold off limited resources on the pending
device.
There can be hardw
Intel VT-d interrupts come from both IRQ remapping and DMA remapping.
In order to report non-recoverable faults back to device driver, we
need to have access to IOMMU fault reporting APIs. This patch adds
build depenency to DMAR code where fault IRQ handlers can selectively
report faults.
Signed-o
IO page faults can be handled outside IOMMU subsystem. For an example,
when nested translation is turned on and guest owns the
first level page tables, device page request can be forwared
to the guest for handling faults. As the page response returns
by the guest, IOMMU driver on the host need to p
Add Intel VT-d ops to the generic iommu_bind_pasid_table API
functions.
The primary use case is for direct assignment of SVM capable
device. Originated from emulated IOMMU in the guest, the request goes
through many layers (e.g. VFIO). Upon calling host IOMMU driver, caller
passes guest PASID tabl
As we found in sun9i-a80, CPUCFG is a collection of registers that are
mapped to the SoC's signals from each individual processor core and
associated peripherals.
These registers are used for SMP bringup and CPU hotplugging.
Signed-off-by: Mylène Josserand
Reviewed-by: Chen-Yu Tsai
---
arch/ar
Add CCI-400 node and control-port on CPUs needed by SMP bringup.
Signed-off-by: Mylène Josserand
Reviewed-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 41 +++
1 file changed, 41 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi
b/arch
Hello everyone,
This is a V6 of my series that adds SMP support for Allwinner sun8i-a83t.
Based on sunxi's tree, sunxi/for-next branch.
Depends on a patch from Doug Berger that allows to include the "cpu-type"
header on assembly files:
6c7dd080ba4b ("ARM: Allow this header to be included by assemb
The R_CPUCFG is a collection of registers needed for SMP bringup
on clusters and cluster's reset.
For the moment, documentation about this register is found in
Allwinner's code only.
Signed-off-by: Mylène Josserand
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 5 +
1 file changed, 5 insertions(+)
To prepare the support for sun8i-a83t, rename the variable name
that handles the power-off of clusters because it is different from
sun9i-a80 to sun8i-a83t.
The power off register for clusters are different from a80 and a83t.
Signed-off-by: Mylène Josserand
Acked-by: Maxime Ripard
Reviewed-by:
The CNTVOFF register from arch timer is uninitialized.
It should be done by the bootloader but it is currently not the case,
even for boot CPU because this SoC is booting in secure mode.
It leads to an random offset value meaning that each CPU will have a
different time, which isn't working very we
To prepare the support of sun8i-a83t, add a field in the smp_data
structure to know if we are on sun9i-a80 or sun8i-a83t.
Add also a global variable to retrieve which architecture we are
having.
Signed-off-by: Mylène Josserand
---
arch/arm/mach-sunxi/mc_smp.c | 5 +
1 file changed, 5 insert
Add the support for A83T.
A83T SoC has an additional register than A80 to handle CPU configurations:
R_CPUS_CFG. Information about the register comes from Allwinner's BSP
driver.
An important difference is the Power Off Gating register for clusters
which is BIT(4) in case of SUN9I-A80 and BIT(0) i
Add the use of enable-method property for SMP support which allows
to handle the SMP support for this specific SoC.
This commit adds enable-method properties to all CPU nodes.
Signed-off-by: Mylène Josserand
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 8
1 file changed, 8 insertions(+)
di
Now that a common function is available for CNTVOFF's
initialization, let's convert shmobile-apmu code to use
this function.
Signed-off-by: Mylène Josserand
---
arch/arm/mach-shmobile/common.h | 1 -
arch/arm/mach-shmobile/headsmp-apmu.S| 22 +-
arch/arm/mach-sh
Add the initialization of CNTVOFF for sun8i-a83t.
For boot CPU, create a new machine that handles this
function's call in an "init_early" callback. We need to initialize
CNTVOFF before the arch timer's initialization otherwise, it will
not be taken into account and fails to boot correctly.
Because
Move the assembly code for cluster cache enabling and resuming
into an assembly file instead of having it directly in C code.
Remove the CFLAGS because we are using the ARM directive "arch"
instead.
Signed-off-by: Mylène Josserand
---
arch/arm/mach-sunxi/Makefile | 4 +--
arch/arm/mach-sunxi/
From: "Liu, Yi L"
When an SVM capable device is assigned to a guest, the first level page
tables are owned by the guest and the guest PASID table pointer is
linked to the device context entry of the physical IOMMU.
Host IOMMU driver has no knowledge of caching structure updates unless
the guest
Hi Joerg and All,
(Rebased to 4.17-rc1. resend)
Shared virtual address (SVA), a.k.a, Shared virtual memory (SVM) on Intel
platforms allow address space sharing between device DMA and applications.
SVA can reduce programming complexity and enhance security. To enable SVA
in the guest, i.e. shared
DMA faults can be detected by IOMMU at device level. Adding a pointer
to struct device allows IOMMU subsystem to report relevant faults
back to the device driver for further handling.
For direct assigned device (or user space drivers), guest OS holds
responsibility to handle and respond per device
Traditionally, device specific faults are detected and handled within
their own device drivers. When IOMMU is enabled, faults such as DMA
related transactions are detected by IOMMU. There is no generic
reporting mechanism to report faults back to the in-kernel device
driver or the guest OS in case
Virtual IOMMU was proposed to support Shared Virtual Memory (SVM)
use in the guest:
https://lists.gnu.org/archive/html/qemu-devel/2016-11/msg05311.html
As part of the proposed architecture, when an SVM capable PCI
device is assigned to a guest, nested mode is turned on. Guest owns the
first level
Adding a flag in device domain into to track whether a guest or
user PASID table is bound to a device.
Signed-off-by: Jacob Pan
---
include/linux/intel-iommu.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/linux/intel-iommu.h b/include/linux/intel-iommu.h
index 304afae..ddc7d79 100
Allow both intel-iommu.c and dmar.c to access device_domain_info.
Prepare for additional per device arch data used in TLB flush function
Signed-off-by: Jacob Pan
---
drivers/iommu/intel-iommu.c | 18 --
include/linux/intel-iommu.h | 19 +++
2 files changed, 19 ins
On Mon, Apr 16, 2018 at 02:21:07PM -0700, Randy Dunlap wrote:
> From: Randy Dunlap
>
> Fix build errors when INFINIBAND_USER_ACCESS=m and MLX5_INFINIBAND=y.
> The build error occurs when the mlx5 driver code attempts to use
> USER_ACCESS interfaces, which are built as a loadable module.
>
> Fixe
There seems to be a culture amongst BIOS teams to want to crash the
OS when an error can't be handled in firmware. Marking GHES errors as
"fatal" is a very common way to do this.
However, a number of errors reported by GHES may be fatal in the sense
a device or link is lost, but are not fatal to t
On 04/13/2018 11:38 AM, James Morse wrote:
> Hi Alex,
>
> On 09/04/18 19:11, Alex G. wrote:
>> On 04/06/2018 01:24 PM, James Morse wrote:
>> Do you have any ETA on when your SEA patches are going to make it
>> upstream? There's not much point in updating my patchset if it's going
>> to conflict wi
Use a mapping from CPER UUID to get the correct handler for a given
GHES error. This is in preparation of splitting some handlers into
irq safe and regular parts.
Signed-off-by: Alexandru Gagniuc
---
drivers/acpi/apei/ghes.c | 78 ++--
1 file changed,
Signed-off-by: Alexandru Gagniuc
---
drivers/acpi/apei/ghes.c | 2 +-
drivers/edac/ghes_edac.c | 3 +--
include/acpi/ghes.h | 5 ++---
3 files changed, 4 insertions(+), 6 deletions(-)
diff --git a/drivers/acpi/apei/ghes.c b/drivers/acpi/apei/ghes.c
index 1efefe919555..f9b53a6f55f3 100644
--
Firmware is evil:
- ACPI was created to "try and make the 'ACPI' extensions somehow
Windows specific" in order to "work well with NT and not the others
even if they are open"
- EFI was created to hide "secret" registers from the OS.
- UEFI was created to allow compromising an otherwise secure
Or "acpi: apei: Don't let puny firmware crash us with puny errors"
This is the improved implementation following feedback from James Morse
(thanks James!). This implementation, I think, is more modular, and easier to
follow, and just makes more sense.
I'm leaving this as RFC because the BIOS team
parisc architecture seems to be mapping readX() and readX_relaxed() APIs
to __raw_readX() API.
__raw_readX() API doesn't provide any kind of ordering guarantees.
commit 032d59e1cde9 ("io: define stronger ordering for the default readX()
implementation") changed asm-generic implementation to use a
parisc architecture seems to be mapping writeX() and writeX_relaxed() APIs
to __raw_writeX() API.
__raw_writeX() API doesn't provide any kind of ordering guarantees.
commit 755bd04aaf4b ("io: define stronger ordering for the default writeX()
implementation") changed asm-generic implementation to u
On 04/16/18 14:49, Thymo van Beers wrote:
> Some lines used spaces instead of tabs at line start.
> This can cause mangled lines in editors due to inconsistency.
>
> Replace spaces for tabs where appropriate.
>
> Signed-off-by: Thymo van Beers
> ---
> Changes in v2:
> - Rebase against docs-nex
Hi,
I am trying to understand what the exclude_idle event attribute is supposed
to accomplish.
As per the definition in the header file:
exclude_idle : 1, /* don't count when idle */
Naively, I thought it would simply stop the event when running in the
context of the idle task (swapper, p
On Mon, 16 Apr 2018 21:30:54 +
Bart Van Assche wrote:
> Hello Steve,
>
> The tool I'm most concerned about is blktrace. I'm not sure though how this
> tool receives event data from the block layer core.
Yeah, blktrace is "special", it looks like it registers its callbacks
from the tracepoin
Hello Rob,
On 04/16/2018 01:57 PM, Rob Herring wrote:
> On Fri, Apr 13, 2018 at 07:50:34PM -0700, David Collins wrote:
>> Introduce bindings for RPMh regulator devices found on some
>> Qualcomm Technlogies, Inc. SoCs. These devices allow a given
>> processor within the SoC to make PMIC regulator
Andreas,
On Sat, 10 Mar 2018 09:40:44 +0200
Andreas Christoforou wrote:
> The kernel would like to have all stack VLA usage removed[1].
> Instead of dynamic allocation, just use XFRM_MAX_DEPTH
> as already done for the "class" array, but as per feedback,
> I will not drop maxclass because that c
On Thu, Mar 29, 2018 at 10:28:24AM +0100, Matt Redfearn wrote:
> The __clear_user function is defined to return the number of bytes that
> could not be cleared. From the underlying memset / bzero implementation
> this means setting register a2 to that number on return. Currently if a
> page fault i
On 4/16/18 5:58 PM, Guenter Roeck wrote:
On Mon, Apr 16, 2018 at 02:43:01PM +0200, Vitaly Wool wrote:
Hey Guenter,
On 04/13/2018 07:56 PM, Guenter Roeck wrote:
On Fri, Apr 13, 2018 at 05:40:18PM +, Vitaly Wool wrote:
On Fri, Apr 13, 2018, 7:35 PM Guenter Roeck wrote:
On Fri, Apr 13,
On Wed, Dec 20, 2017 at 08:07:17PM +0100, Jiri Slaby wrote:
> On 12/20/2017, 06:45 PM, Josh Poimboeuf wrote:
> > It might not be until 2018 though. But in the meantime you can go ahead
> > and update your patches accordingly and then we can combine them for
> > testing next year.
>
> I already di
On Fri, 23 Feb 2018 13:09:21 -0800, Florian Fainelli
wrote:
> From: Doug Berger
>
> This commit allows a Broadcom Brahma-B53 core to be detected when executing
> an arm architecture kernel in aarch32 state.
>
> Signed-off-by: Doug Berger
> Signed-off-by: Florian Fainelli
> ---
Applied to so
On Fri, 23 Feb 2018 13:09:22 -0800, Florian Fainelli
wrote:
> Define Broadcom's Brahma-B15 main ID register value, masked with
> ARM_CPU_PART_MASK.
>
> Signed-off-by: Florian Fainelli
> ---
Applied to soc/next, thanks!
--
Florian
memory-barriers.txt has been updated with the following requirement.
"When using writel(), a prior wmb() is not needed to guarantee that the
cache coherent memory writes have completed before writing to the MMIO
region."
Current writeX() and iowriteX() implementations on alpha are not
satisfying
On Fri, 23 Feb 2018 13:09:23 -0800, Florian Fainelli
wrote:
> From: Doug Berger
>
> The 7278 device is the first device that includes support for the V7
> memory map developed for use in 64-bit architecture brcmstb devices.
> This map relocates the register physical offset from 0xF000 to
>
On Fri, 23 Feb 2018 12:41:10 -0800, Florian Fainelli
wrote:
> The B53 CPU design supports up to 8 processors, which moved the RAC_FLUSH_REG
> offset 0x4 bytes below to make room for a RAC_CONFIG2_REG to control RAC
> settings for CPU4-7.
>
> Lookup the processor type (B15 or B53) and adjust the
On Fri, 23 Feb 2018 13:09:20 -0800, Florian Fainelli
wrote:
> From: Doug Berger
>
> The constants defined in this file are equally useful in assembly and C
> source files. The arm64 architecture version of this file allows
> inclusion in both assembly and C source files, so this this commit add
Hey Everyone,
Thanks everyone for the feedback on the RFC:
https://lkml.org/lkml/2018/3/9/903
Seems like there is a general interest in this feature, so here
is a V2 of the proposal with the comments I received.
Please provide comments on the _nowait2() API. It is not my favorite,
but it seems l
This should let us associate enum kdoc to these values.
Signed-off-by: Andres Rodriguez
---
drivers/base/firmware_loader/fallback.c | 12 ++--
drivers/base/firmware_loader/fallback.h | 6 --
drivers/base/firmware_loader/firmware.h | 17 +
drivers/base/firmware_loader
This reduces the unnecessary spew when trying to load optional firmware:
"Direct firmware load for ... failed with error -2"
Signed-off-by: Andres Rodriguez
---
drivers/net/wireless/ath/ath10k/core.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/wireless/ath/ath
This reduces the unnecessary spew when trying to load optional firmware:
"Direct firmware load for ... failed with error -2"
Signed-off-by: Andres Rodriguez
---
drivers/net/wireless/broadcom/brcm80211/brcmfmac/firmware.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/
Some basic definitions for the FW_OPT_* values
Signed-off-by: Andres Rodriguez
---
drivers/base/firmware_loader/firmware.h | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/base/firmware_loader/firmware.h
b/drivers/base/firmware_loader/firmware.h
index 957396293b92..8ef23
Previously, one could assume the firmware name from the preceding
message: "Direct firmware load for {name} failed with error %d".
However, with the new firmware_request_nowarn() entrypoint, the message
outlined above will not always be printed.
Therefore, we add the firmware name to the fallback
Currently the firmware loader only exposes one silent path for querying
optional firmware, and that is firmware_request_direct(). This function
also disables the fallback path, which might not always be the
desired behaviour. [0]
This patch introduces variations of firmware_request() and
firmware_
Currently, during the normal boot process the amdgpu driver will produce
spew like the following in dmesg:
Direct firmware load for amdgpu/polaris10_mec_2.bin failed with error -2
This happens when amdgpu tries to load optional firmware files. So the
error does not affect the startup sequence.
Th
Including:
- Fixup outdated kernel-doc paths
- Slightly too short title underline
- Some typos
Signed-off-by: Andres Rodriguez
---
Documentation/driver-api/firmware/request_firmware.rst | 16
drivers/base/firmware_loader/fallback.c| 4 ++--
drivers/base/firmw
On Tue, Apr 17, 2018 at 12:14:37AM +0200, Vitaly Wool wrote:
[ ... ]
> Ugh. Could you please keep that patch and apply this on top:
>
> diff --git a/mm/z3fold.c b/mm/z3fold.c
> index c0bca6153b95..e8a80d044d9e 100644
> --- a/mm/z3fold.c
> +++ b/mm/z3fold.c
> @@ -840,6 +840,7 @@ static int z3fold_r
> James,
>
> If I understand correctly, you're saying you want to be able to build without
> debug support...? I'm not convinced that building a client without debug
> support is interesting or useful. In fact, I think it would be harmful, and
> we shouldn't open up the possibility - this is
>-Original Message-
>From: Jani Nikula [mailto:jani.nik...@linux.intel.com]
>Sent: Wednesday, April 11, 2018 5:27 AM
>To: Ian W MORRISON
>Cc: Vivi, Rodrigo ; Srivatsa, Anusha
>; Wajdeczko, Michal
>; Greg KH ;
>airl...@linux.ie; joonas.lahti...@linux.intel.com;
>linux-kernel@vger.kernel.
On Mon, 16 Apr 2018 12:24:07 -0500
Kim Phillips wrote:
> On Mon, 16 Apr 2018 13:58:00 -0300
> Arnaldo Carvalho de Melo wrote:
>
> > Em Mon, Apr 16, 2018 at 11:07:30AM -0500, Kim Phillips escreveu:
> > > On Mon, 16 Apr 2018 10:51:25 -0300
> > > Arnaldo Carvalho de Melo wrote:
> > >
> > > > Em
On 04/16/18 15:24, Andres Rodriguez wrote:
> Currently the firmware loader only exposes one silent path for querying
> optional firmware, and that is firmware_request_direct(). This function
> also disables the fallback path, which might not always be the
> desired behaviour. [0]
>
> This patch in
The GPU subsystem node was a workaround to have a central device to
bind V3D and display to. Following the lead of 246774d17fc0
("drm/etnaviv: remove the need for a gpu-subsystem DT node"), remove
the subsystem node usage and just create a platform device for the DRM
device to attach to if any of
From: Randy Dunlap
Date: Mon, 16 Apr 2018 12:32:55 -0700
> From: Randy Dunlap
>
> Make lib/textsearch.c usable as kernel-doc.
> Add textsearch() function family to kernel-api documentation.
> Fix kernel-doc warnings in :
> ../include/linux/textsearch.h:65: warning: Incorrect use of kernel-doc
> On Apr 16, 2018, at 3:42 PM, James Simmons wrote:
>
>
>> James,
>>
>> If I understand correctly, you're saying you want to be able to build
>> without debug support...? I'm not convinced that building a client without
>> debug support is interesting or useful. In fact, I think it would b
Hi Rob,
Thanks for sharing your time. Please see my answers inline.
On 4/16/2018 10:59 AM, Rob Herring wrote:
On Tue, Apr 10, 2018 at 11:32:03AM -0700, Jae Hyun Yoo wrote:
This commit adds documents of generic PECI bus, adapter and client drivers.
"dt-bindings: ..." for the subject prefix pl
Hello,
Rebased on top of e27be240df53 ("mm: memcg: make sure memory.events is
uptodate when waking pollers").
This patchset implements memory.swap.events which contains max and
fail events so that userland can monitor and respond to swap running
out. It contains the following two patches.
0001
get_swap_page() is always followed by mem_cgroup_try_charge_swap().
This patch moves mem_cgroup_try_charge_swap() into get_swap_page() and
makes get_swap_page() call the function even after swap allocation
failure.
This simplifies the callers and consolidates memcg related logic and
will ease addi
For certain applications it is desirable to rapidly boot a KVM virtual
machine. In cases where legacy hardware and software support within the
guest is not needed, Qemu should be able to boot directly into the
uncompressed Linux kernel binary without the need to run firmware.
There already exists
I HAVE AN IMPORTANT MESSAGE TO DISCUSS WITH YOU, PLEASE WRITE BACK TO ME FOR
DETAILS.
REGARDS,
ELIZABETH WHITE
-Sent from IPad
Add swap max and fail events so that userland can monitor and respond
to running out of swap.
v2: Rebased on top of e27be240df53 ("mm: memcg: make sure
memory.events is uptodate when waking pollers")
Signed-off-by: Tejun Heo
Cc: Johannes Weiner
Cc: Michal Hocko
Cc: Vladimir Davydov
Cc: Ro
In order to pave the way for hypervisors other than Xen to use the PVH
entry point for VMs, we need to factor the PVH entry code into Xen specific
and hypervisor agnostic components. The first step in doing that, is to
create a new config option for PVH entry that can be enabled
independently from
On 4/16/2018 11:10 AM, Rob Herring wrote:
On Tue, Apr 10, 2018 at 11:32:06AM -0700, Jae Hyun Yoo wrote:
This commit adds a dt-bindings document of PECI adapter driver for Aspeed
AST24xx/25xx SoCs.
Signed-off-by: Jae Hyun Yoo
Reviewed-by: Haiyue Wang
Reviewed-by: James Feist
Reviewed-by: Vern
Once hypervisors other than Xen start using the PVH entry point for
starting VMs, we would like the option of being able to compile PVH entry
capable kernels without enabling CONFIG_XEN and all the code that comes
along with that. To allow that, we are moving the PVH code out of Xen and
into files
We need to refactor PVH entry code so that support for other hypervisors
like Qemu/KVM can be added more easily.
This patch moves the small block of code used for initializing Xen PVH
virtual machines into the Xen specific file. This initialization is not
going to be needed for Qemu/KVM guests. Mo
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