On Thu, 29 Mar 2018 15:10:54 +0200
Peter Rosin wrote:
> On a sama5d31 with a Full-HD dual LVDS panel (132MHz pixel clock) NAND
> flash accesses have a tendency to cause display disturbances. Add a
> module param to disable DMA from the NAND controller, since that fixes
> the display problem for m
On Mon, 26 Mar 2018 20:56:45 -0600
Aaron Durbin wrote:
> On Mon, Mar 26, 2018 at 12:24 PM, Alan Cox wrote:
> >> Sadly, this situation
> >> is not unique to this hardware. There is hardware all over that does
> >> not meet the current assumptions being made in the early uart drivers
> >> within t
Hi,
On Wed, Mar 28, 2018 at 06:45:07PM -0700, Tony Lindgren wrote:
> Hi,
>
> * Sebastian Reichel [180328 14:03]:
> > Hi,
> >
> > On Wed, Mar 28, 2018 at 10:29:10AM +0800, Mark Brown wrote:
> > > On Wed, Mar 28, 2018 at 12:22:37AM +0200, Sebastian Reichel wrote:
> > > > On Tue, Mar 27, 2018 at 0
On Thu 29-03-18 16:13:08, Kirill A. Shutemov wrote:
> On Thu, Mar 29, 2018 at 02:52:27PM +0200, Michal Hocko wrote:
> > On Thu 29-03-18 15:37:12, Kirill A. Shutemov wrote:
> > > On Thu, Mar 29, 2018 at 01:20:34PM +0200, Michal Hocko wrote:
> > > > On Wed 28-03-18 19:55:32, Kirill A. Shutemov wrote:
On 2018-03-29 15:33, Boris Brezillon wrote:
> On Thu, 29 Mar 2018 15:10:54 +0200
> Peter Rosin wrote:
>
>> On a sama5d31 with a Full-HD dual LVDS panel (132MHz pixel clock) NAND
>> flash accesses have a tendency to cause display disturbances. Add a
>> module param to disable DMA from the NAND con
Commit-ID: 00c720743fc951d46a7ee15f26a531b27f6082cb
Gitweb: https://git.kernel.org/tip/00c720743fc951d46a7ee15f26a531b27f6082cb
Author: Thomas Gleixner
AuthorDate: Mon, 26 Mar 2018 15:29:57 +0200
Committer: Thomas Gleixner
CommitDate: Thu, 29 Mar 2018 15:35:59 +0200
alarmtimer: Init na
On 03/29/2018 02:59 PM, Lee Jones wrote:
> On Wed, 28 Mar 2018, Fabrice Gasnier wrote:
>
>> On 03/28/2018 05:22 PM, Lee Jones wrote:
>>> On Wed, 14 Feb 2018, Fabrice Gasnier wrote:
>>>
STM32 Timers can support up to 7 DMA requests:
- 4 channels, update, compare and trigger.
Optional
On 03/28/2018 11:36 PM, David Wang wrote:
Newer centaur CPUs(Family == 7) also support this cpu temperature sensor.
Signed-off-by: David Wang
---
FWIW, this would be v2, not v1, and a changelog would be appreciated.
drivers/hwmon/via-cputemp.c | 7 +++
1 file changed, 7 insertions(+)
Hi,
On 29-03-18 13:58, Greg Kroah-Hartman wrote:
On Thu, Mar 29, 2018 at 01:21:15PM +0200, Hans de Goede wrote:
It is not possible to get DMA32 zone memory through kmalloc,
Why can't we just fix that issue here instead?
AFAIK that would go against the design of the whole slab
allocator, it
On Thu, 29 Mar 2018 15:37:43 +0200
Peter Rosin wrote:
> On 2018-03-29 15:33, Boris Brezillon wrote:
> > On Thu, 29 Mar 2018 15:10:54 +0200
> > Peter Rosin wrote:
> >
> >> On a sama5d31 with a Full-HD dual LVDS panel (132MHz pixel clock) NAND
> >> flash accesses have a tendency to cause displa
On 03/29/2018 06:16 AM, Thomas Gleixner wrote:
>> This is OK at least on the hardware we are immediately concerned about
>> because the LLC sharing happens at both the slice and at the package
>> level, which are also NUMA boundaries.
> So that addresses the scheduler interaction, but it still leav
Hi Ariel,
On 3/29/2018 5:17 AM, Elior, Ariel wrote:
>> Subject: [PATCH v7 3/7] bnx2x: Replace doorbell barrier() with wmb()
>>
>> barrier() doesn't guarantee memory writes to be observed by the hardware on
>> all architectures. barrier() only tells compiler not to move this code
>> with respect to
Hi Oleksandr,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm/drm-next]
[also build test ERROR on next-20180329]
[cannot apply to v4.16-rc7]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https
> -Original Message-
> From: Borislav Petkov
> Sent: Thursday, March 29, 2018 5:46 AM
> To: Ghannam, Yazen
> Cc: linux-...@vger.kernel.org; linux-kernel@vger.kernel.org;
> ard.biesheu...@linaro.org; x...@kernel.org; tony.l...@intel.com
> Subject: Re: [PATCH v3 2/8] efi: Decode IA32/X64 Pr
On Thu, Mar 29, 2018 at 03:16:12PM +0200, Thomas Gleixner wrote:
> On Wed, 28 Mar 2018, Alison Schofield wrote:
> > From: Alison Schofield
> >
> > Intel's Skylake Server CPUs have a different LLC topology than previous
> > generations. When in Sub-NUMA-Clustering (SNC) mode, the package is
> > di
On Thu, Mar 29, 2018 at 09:16:19AM +0200, Peter Zijlstra wrote:
> On Thu, Mar 29, 2018 at 04:27:05AM +0200, Frederic Weisbecker wrote:
> > The last user of __ARCH_SET_SOFTIRQ_PENDING has been converted to generic
> > per-cpu softirq mask. We can now remove this conditional.
>
> This seems like hal
On Thu, Mar 29, 2018 at 01:11:07PM +0100, Colin King wrote:
> From: Colin Ian King
>
> Trivial fix to spelling mistake in DP_ERR message text
>
> Signed-off-by: Colin Ian King
> ---
> drivers/infiniband/hw/qedr/main.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git
2018-03-29 9:50 GMT+01:00 Joerg Roedel :
> On Tue, Mar 20, 2018 at 08:50:13PM +, Dmitry Safonov wrote:
>> Hmm, but this fixes my softlockup issue, because it's about time spent
>> in printk() inside irq-disabled section, rather about exiting the dmar-
>> clearing loop.
>> And on my hw doesn't m
> -Original Message-
> From: Borislav Petkov
> Sent: Thursday, March 29, 2018 6:55 AM
> To: Ghannam, Yazen
> Cc: linux-...@vger.kernel.org; linux-kernel@vger.kernel.org;
> ard.biesheu...@linaro.org; x...@kernel.org; tony.l...@intel.com
> Subject: Re: [PATCH v3 3/8] efi: Decode IA32/X64 Pr
Hi Niklas,
On 28/03/2018 12:50, Niklas Cassel wrote:
> PCI endpoint fixes to improve the way 64-bit BARs are handled.
>
>
> There are still future improvements that could be made:
>
> pci-epf-test.c always allocates space for
> 6 BARs, even when using 64-bit BARs (which
> really only requires u
- On Mar 28, 2018, at 5:25 PM, Thomas Gleixner t...@linutronix.de wrote:
> On Wed, 28 Mar 2018, Mathieu Desnoyers wrote:
>> - On Mar 28, 2018, at 1:49 PM, Peter Zijlstra pet...@infradead.org wrote:
>> > I don't think disallowing system calls is arbitrary. And I think that is
>> > something
On Tue, Mar 27, 2018 at 3:01 AM, Peter Rosin wrote:
> On 2018-03-27 00:23, Rob Herring wrote:
>> On Mon, Mar 19, 2018 at 06:02:45PM +0100, Peter Rosin wrote:
>>> Allow linear scaling and modification of the type of an io-channel.
>>>
>>> When an ADC channel measures the midpoint of a voltage divid
On Wed, Mar 28, 2018 at 10:00 AM, Gustavo Pimentel
wrote:
> Yes, it's not a replace character from lower to upper case. It's just a code
> formatting style to be coherent with the rest of the driver code. I guess I
> can
> added on the patch description a note about it.
> It works for you?
Yes,
On Thu, Mar 29, 2018 at 06:45:12AM -0700, Dave Hansen wrote:
> On 03/29/2018 06:16 AM, Thomas Gleixner wrote:
> >> This is OK at least on the hardware we are immediately concerned about
> >> because the LLC sharing happens at both the slice and at the package
> >> level, which are also NUMA boundar
On 29.03.2018 16:31, Alexander Shishkin wrote:
> On Mon, Mar 26, 2018 at 12:20:32PM +0300, Alexey Budankov wrote:
>>
>> Store thread context-switch-out event type into Perf trace as a part of
>> PERF_RECORD_SWITCH[_CPU_WIDE] records.
>>
>> Introduced types of switch-out events assumed to be
>> a)
Commit-ID: b4c786e5aa69c5a75ac3932f81fdf8e8c120c03b
Gitweb: https://git.kernel.org/tip/b4c786e5aa69c5a75ac3932f81fdf8e8c120c03b
Author: Jiri Olsa
AuthorDate: Wed, 21 Mar 2018 15:05:15 +0100
Committer: Arnaldo Carvalho de Melo
CommitDate: Tue, 27 Mar 2018 13:13:38 -0300
perf build: Fix
Commit-ID: f58385f629c87a9e210108b39c1f4950d0363ad2
Gitweb: https://git.kernel.org/tip/f58385f629c87a9e210108b39c1f4950d0363ad2
Author: Kan Liang
AuthorDate: Mon, 26 Mar 2018 09:42:09 -0400
Committer: Arnaldo Carvalho de Melo
CommitDate: Tue, 27 Mar 2018 13:13:38 -0300
perf mmap: Fix a
* Sebastian Reichel [180329 13:37]:
> Hi,
>
> On Wed, Mar 28, 2018 at 06:45:07PM -0700, Tony Lindgren wrote:
> > Hi,
> >
> > * Sebastian Reichel [180328 14:03]:
> > > Hi,
> > >
> > > On Wed, Mar 28, 2018 at 10:29:10AM +0800, Mark Brown wrote:
> > > > On Wed, Mar 28, 2018 at 12:22:37AM +0200, S
Commit-ID: 895e3b06fc2ce438adc62cb13d31ea001dcfda16
Gitweb: https://git.kernel.org/tip/895e3b06fc2ce438adc62cb13d31ea001dcfda16
Author: Arnaldo Carvalho de Melo
AuthorDate: Mon, 26 Mar 2018 11:42:15 -0300
Committer: Arnaldo Carvalho de Melo
CommitDate: Tue, 27 Mar 2018 13:13:38 -0300
p
Commit-ID: cfbb9be8119dec38a2adefeb8fac526dd66a1d16
Gitweb: https://git.kernel.org/tip/cfbb9be8119dec38a2adefeb8fac526dd66a1d16
Author: Thomas Richter
AuthorDate: Mon, 26 Mar 2018 10:25:34 +0200
Committer: Arnaldo Carvalho de Melo
CommitDate: Tue, 27 Mar 2018 13:13:38 -0300
perf vendor
Commit-ID: 0a73d21e9bdf43124241c3253dadc5044e239647
Gitweb: https://git.kernel.org/tip/0a73d21e9bdf43124241c3253dadc5044e239647
Author: Thomas Richter
AuthorDate: Mon, 26 Mar 2018 10:25:35 +0200
Committer: Arnaldo Carvalho de Melo
CommitDate: Tue, 27 Mar 2018 13:13:38 -0300
perf vendor
Hello,
syzbot hit the following crash on upstream commit
bcfc1f4554662d8f2429ac8bd96064a59c149754 (Sat Mar 24 16:50:12 2018 +)
Merge tag 'pinctrl-v4.16-3' of
git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
syzbot dashboard link:
https://syzkaller.appspot.com/bug?extid=2
Commit-ID: 3fb1a23155e91bd00281425041ec2381e435dcc2
Gitweb: https://git.kernel.org/tip/3fb1a23155e91bd00281425041ec2381e435dcc2
Author: Thomas Richter
AuthorDate: Mon, 26 Mar 2018 10:25:36 +0200
Committer: Arnaldo Carvalho de Melo
CommitDate: Tue, 27 Mar 2018 13:13:38 -0300
perf vendor
On Thu, Mar 29, 2018 at 03:47:46PM +0200, Frederic Weisbecker wrote:
> On Thu, Mar 29, 2018 at 09:16:19AM +0200, Peter Zijlstra wrote:
> > On Thu, Mar 29, 2018 at 04:27:05AM +0200, Frederic Weisbecker wrote:
> > > The last user of __ARCH_SET_SOFTIRQ_PENDING has been converted to generic
> > > per-c
Commit-ID: bc17f949d6feb633e579ee7e7dd58d9200073215
Gitweb: https://git.kernel.org/tip/bc17f949d6feb633e579ee7e7dd58d9200073215
Author: Thomas Richter
AuthorDate: Mon, 26 Mar 2018 10:25:37 +0200
Committer: Arnaldo Carvalho de Melo
CommitDate: Tue, 27 Mar 2018 13:13:39 -0300
perf vendor
Commit-ID: 109d59b900e78834c66657dd4748fcedb9a1fe8d
Gitweb: https://git.kernel.org/tip/109d59b900e78834c66657dd4748fcedb9a1fe8d
Author: Thomas Richter
AuthorDate: Mon, 26 Mar 2018 10:25:38 +0200
Committer: Arnaldo Carvalho de Melo
CommitDate: Tue, 27 Mar 2018 13:13:39 -0300
perf vendor
On 23/03/2018 at 21:49:39 +0100, Andrew Lunn wrote:
> On Fri, Mar 23, 2018 at 09:11:12PM +0100, Alexandre Belloni wrote:
> > Add a driver for the Microsemi MII Management controller (MIIM) found on
> > Microsemi SoCs.
> > On Ocelot, there are two controllers, one is connected to the internal
> > PH
* Peter Zijlstra wrote:
> On Thu, Mar 29, 2018 at 03:06:48PM +0300, Alexander Shishkin wrote:
> > This is a cosmetic patch that deals with the address filter structure's
> > ambiguous fields 'filter' and 'range'. The former stands to mean that the
> > filter's *action* should be to filter the tr
On Thu, Mar 29, 2018 at 04:01:11PM +0200, Peter Zijlstra wrote:
> On Thu, Mar 29, 2018 at 03:47:46PM +0200, Frederic Weisbecker wrote:
> > On Thu, Mar 29, 2018 at 09:16:19AM +0200, Peter Zijlstra wrote:
> > > On Thu, Mar 29, 2018 at 04:27:05AM +0200, Frederic Weisbecker wrote:
> > > > The last user
Hi!
> Meanwhile, I can try to make voice calls more reproducable with
> qmi or MM for example instead of just n_gsm.. And then I'll try
> to fix my n_gsm pile of hacks for posting..
If you get something to work, that will be great.
If you get ofonod to work, that would be even better :-). [That'
Commit-ID: bd03143007eb9b03a7f2316c677780561b68ba2a
Gitweb: https://git.kernel.org/tip/bd03143007eb9b03a7f2316c677780561b68ba2a
Author: Thomas Gleixner
AuthorDate: Mon, 26 Mar 2018 15:29:57 +0200
Committer: Thomas Gleixner
CommitDate: Thu, 29 Mar 2018 16:10:07 +0200
alarmtimer: Init na
On 23/03/2018 at 14:51:19 -0700, Florian Fainelli wrote:
> > + writel(MSCC_MIIM_CMD_VLD | (mii_id << MSCC_MIIM_CMD_PHYAD_SHIFT) |
> > + (regnum << MSCC_MIIM_CMD_REGAD_SHIFT) | MSCC_MIIM_CMD_OPR_READ,
> > + miim->regs + MSCC_MIIM_REG_CMD);
> > +
> > + ret = mscc_miim_wait_ready
From: Borislav Petkov
A separate define just to print a space character is silly and
completely unneeded. Remove it.
Signed-off-by: Borislav Petkov
Cc: Ard Biesheuvel
Cc: linux-...@vger.kernel.org
---
drivers/firmware/efi/cper-arm.c | 6 ++
drivers/firmware/efi/cper.c | 6 ++
2 fi
On 29/03/2018 at 15:10, Peter Rosin wrote:
On a sama5d31 with a Full-HD dual LVDS panel (132MHz pixel clock) NAND
flash accesses have a tendency to cause display disturbances. Add a
module param to disable DMA from the NAND controller, since that fixes
the display problem for me.
Signed-off-by:
On Thu, Mar 29, 2018 at 01:22:37PM +0200, Dominik Brodowski wrote:
> At least on 64-bit x86, it will likely be a hard requirement from v4.17
> onwards to not call system call functions in the kernel: It is better to
> use use a different calling convention for system calls there, where
> struct pt
* Pavel Machek [180329 14:11]:
> Hi!
>
> > Meanwhile, I can try to make voice calls more reproducable with
> > qmi or MM for example instead of just n_gsm.. And then I'll try
> > to fix my n_gsm pile of hacks for posting..
>
> If you get something to work, that will be great.
Yeah I need to at
The intention is to get notified of process failures as soon
as possible, before a possible core dumping (which could be very long)
(e.g. in some process-manager). Coredump and exit process events
are perfect for such use cases (see 2b5faa4c553f "connector: Added
coredumping event to the process co
On 2018-03-29 16:20, Nicolas Ferre wrote:
> On 29/03/2018 at 15:10, Peter Rosin wrote:
>> On a sama5d31 with a Full-HD dual LVDS panel (132MHz pixel clock) NAND
>> flash accesses have a tendency to cause display disturbances. Add a
>> module param to disable DMA from the NAND controller, since that
Linus,
please pull sound fixes for v4.16-final from:
git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound.git tags/sound-4.16
The topmost commit is 5607dddbfca774fb38bffadcb077fe03aa4ac5c6
sound fixes for 4.16-final
Very
On Thu, Mar 29, 2018 at 09:54:01AM -0400, Mathieu Desnoyers wrote:
> Let's say we disallow system calls from rseq critical sections. A few points
> arise:
>
> - We still need to allow traps (page faults, breakpoints, ...) within rseq
> c.s.,
>
> - We still need to allow interrupts within rseq c.
On Thu, Mar 29, 2018 at 10:53:05AM +0200, Christoph Hellwig wrote:
> On Wed, Mar 28, 2018 at 05:35:26PM +0100, Al Viro wrote:
> > > ret = vfs_fsync(req->file, req->datasync);
> > > - fput(req->file);
> > > - aio_complete(container_of(req, struct aio_kiocb, fsync), ret, 0);
> > > + if (aio_complet
On Wed, Mar 28, 2018 at 11:18:09AM -0700, Laura Abbott wrote:
> The new challenge is to remove VLAs from the kernel
> (see https://lkml.org/lkml/2018/3/7/621) to eventually
> turn on -Wvla.
>
> Using a kmalloc array is the easy way to fix this but kmalloc is still
> more expensive than stack alloc
On Thu, 29 Mar 2018 10:16:22 +0800
Wang Yu wrote:
> > What you can do is make that map_pid_to_cmdline array bigger.
> >
> > -- Steve
>
> I am sorry about it, and as the number of cpu cores increases, the current
>
> PID_MAX_DEFAULT is too small, our online machines set the pid_max 65536 as
>
On 2018-03-29 15:44, Boris Brezillon wrote:
> On Thu, 29 Mar 2018 15:37:43 +0200
> Peter Rosin wrote:
>
>> On 2018-03-29 15:33, Boris Brezillon wrote:
>>> On Thu, 29 Mar 2018 15:10:54 +0200
>>> Peter Rosin wrote:
>>>
On a sama5d31 with a Full-HD dual LVDS panel (132MHz pixel clock) NAND
On Thu, 29 Mar 2018 16:20:38 +0200
Nicolas Ferre wrote:
> On 29/03/2018 at 15:10, Peter Rosin wrote:
> > On a sama5d31 with a Full-HD dual LVDS panel (132MHz pixel clock) NAND
> > flash accesses have a tendency to cause display disturbances. Add a
> > module param to disable DMA from the NAND con
Em Thu, 29 Mar 2018 08:22:08 +0900
Inki Dae escreveu:
> Hi Mauro,
>
> 2018년 03월 29일 03:12에 Mauro Carvalho Chehab 이(가) 쓴 글:
> > Hi Greg,
> >
> > Those are the backports meant to solve CVE-2017-13166 on Kernel 3.18.
> >
> > It contains two v4l2-ctrls fixes that are required to avoid crashes
> >
On Thu, 29 Mar 2018, Fabrice Gasnier wrote:
> On 03/29/2018 02:59 PM, Lee Jones wrote:
> > On Wed, 28 Mar 2018, Fabrice Gasnier wrote:
> >
> >> On 03/28/2018 05:22 PM, Lee Jones wrote:
> >>> On Wed, 14 Feb 2018, Fabrice Gasnier wrote:
> >>>
> STM32 Timers can support up to 7 DMA requests:
>
On Thu, Mar 29, 2018 at 03:37:00PM +0200, Michal Hocko wrote:
> On Thu 29-03-18 16:13:08, Kirill A. Shutemov wrote:
> > On Thu, Mar 29, 2018 at 02:52:27PM +0200, Michal Hocko wrote:
> > > On Thu 29-03-18 15:37:12, Kirill A. Shutemov wrote:
> > > > On Thu, Mar 29, 2018 at 01:20:34PM +0200, Michal Ho
On Wed, Mar 28, 2018 at 03:03:42PM -0500, Alan Tull wrote:
> On Wed, Mar 28, 2018 at 11:26 AM, Alan Tull wrote:
> > On Fri, Mar 23, 2018 at 7:27 AM, Paolo Pisati wrote:
> >
> > Hi Paolo,
>
> One more thing. The api for registering a FPGA manager is changing.
> It won't be hard to adapt. I've p
On Tue, Mar 27, 2018 at 02:59:21AM +0430, Nasser wrote:
Hi Mauro,
Thank you for taking time to review my patch.
May be I should rephrase the commit message to something like:
Use the default register values as suggested in TVP5150AM1 datasheet
As this is not a hardware-dependent issue. A
On 03/29/2018 06:47 AM, Peter Zijlstra wrote:
> The issue is that HPC workloads care about cache-size-per-cpu measure,
> and the way they go about obtaining that is reading the cache-size and
> dividing it by the h-weight of the cache-mask.
That works, but only if the memory being accessed is slic
Sorry, didn't mean to drop the lists here. re-adding.
On Wed, Mar 28, 2018 at 4:05 PM, Alex Deucher wrote:
> On Wed, Mar 28, 2018 at 3:53 PM, Logan Gunthorpe wrote:
>>
>>
>> On 28/03/18 01:44 PM, Christian König wrote:
>>> Well, isn't that exactly what dma_map_resource() is good for? As far as
>
On 03/29/2018 06:47 AM, Peter Zijlstra wrote:
> Further I think Dave argued that we should not change the llc-size,
> because while SNC presents a subset of the cache to local CPUs, for
> remote data the whole cache is still available, again something some
> applications might rely on.
BTW, I may
On Tue, Mar 20, 2018 at 07:31:31AM -0700, Richard Cochran wrote:
> On Tue, Mar 20, 2018 at 09:28:47AM +0530, Sricharan R wrote:
> > Reviewed-by: Abhishek Sahu
> > Adds missing memory, reserved-memory nodes.
> >
> > Signed-off-by: Sricharan R
> > ---
> > arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.
On Wed, 28 Mar 2018, Paul E. McKenney wrote:
> > > In the meantime, does the cat file look to you like it correctly
> > > models the combination of TSO and multicopy atomicity? Do the
> > > fences really work, or did I just get lucky with my choice of
> > > litmus tests?
> >
> > You got lucky.
On Thu, Mar 29, 2018 at 04:05:44PM +0200, Alexandre Belloni wrote:
> On 23/03/2018 at 21:49:39 +0100, Andrew Lunn wrote:
> > On Fri, Mar 23, 2018 at 09:11:12PM +0100, Alexandre Belloni wrote:
> > > Add a driver for the Microsemi MII Management controller (MIIM) found on
> > > Microsemi SoCs.
> > >
On Thu, Mar 29, 2018 at 07:20:27AM -0700, Matthew Wilcox wrote:
> On Thu, Mar 29, 2018 at 01:22:37PM +0200, Dominik Brodowski wrote:
> > At least on 64-bit x86, it will likely be a hard requirement from v4.17
> > onwards to not call system call functions in the kernel: It is better to
> > use use a
This patch prevents the mutex global_tunables_lock from being
unlocked before being locked. This mutex is not locked if the
function sugov_kthread_create fails.
Signed-off-by: Jules Maselbas
---
kernel/sched/cpufreq_schedutil.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git
On Thu, Mar 29, 2018 at 04:00:04PM +0800, Jason Wang wrote:
> Vq log_base is the userspace address of bitmap which has nothing to do
> with IOTLB. So it needs to be validated unconditionally otherwise we
> may try use 0 as log_base which may lead to pin pages that will lead
> unexpected result (e.g
Add documentation about a new rk808 devicetree property. This can enable
the rk805/rk808/rk818 PMIC reset, instead of using soft resets from the
Control and Reset Module.
Signed-off-by: Daniel Schultz
---
Changes:
v2: Changed commit message
Documentation/devicetree/bindings/mfd/rk808.tx
Hi Rob,
On 03/18/2018 01:52 PM, Rob Herring wrote:
On Thu, Mar 15, 2018 at 11:58:50AM +0100, Daniel Schultz wrote:
Add documentation about a new rk808 devicetree property, which can
enable resets by the PMIC.
The subject needs to be more specific that this is for Rockchip PMIC.
Signed-off-
From: Dominik Brodowski
> Sent: 29 March 2018 15:42
> On Thu, Mar 29, 2018 at 07:20:27AM -0700, Matthew Wilcox wrote:
> > On Thu, Mar 29, 2018 at 01:22:37PM +0200, Dominik Brodowski wrote:
> > > At least on 64-bit x86, it will likely be a hard requirement from v4.17
> > > onwards to not call system
Hi Grygorii,
Thanks for reviewing this!
On 03/28/2018 03:01 PM, Grygorii Strashko wrote:
> Hi Murali,
>
> On 03/27/2018 11:31 AM, Murali Karicheri wrote:
>> Navigator Subsystem (NSS) available on K2G SoC has a cut down
>> version of QMSS with less number of queues, internal linking ram
>> with l
Since all three shutdown functions have almost the same code, all logic
from the shutdown functions can be refactored to a new function
"rk808_update_bits", which can update a register by a given address and
bitmask.
Signed-off-by: Daniel Schultz
---
Changes:
v2: Re-submit with recipients
When using Rockchip SoCs with rk805/808/818 PMICs, restarts are realized by
setting the reset registers in the "Clock and Reset Unit".
Now, the driver can trigger a restart in the PMIC. Like the
shutdown function, the restart is bound to an independent
"rockchip,system-reset-controller" devicetree
Hi All,
Since I made the same mistake myself I've done a quick grep for
GFP_DMA32 in the kernel and drivers/scsi/aacraid/commctrl.c
came up as a result of this grep, it does:
p = kmalloc(sg_count[i], GFP_KERNEL|GFP_DMA32);
But kmalloc always returns memory from t
Le mer. 28 mars 2018 à 18:25, Daniel Lezcano
a écrit :
On 28/03/2018 17:15, Paul Cercueil wrote:
Le 2018-03-24 07:26, Daniel Lezcano a écrit :
On 18/03/2018 00:29, Paul Cercueil wrote:
This driver will use the TCU (Timer Counter Unit) present on the
Ingenic
JZ47xx SoCs to provide the
On Fri 2018-03-16 20:19:35, Andy Shevchenko wrote:
> On Thu, 2018-03-15 at 16:26 +0100, Petr Mladek wrote:
> > On Thu 2018-03-15 15:09:03, Andy Shevchenko wrote:
> > > On Wed, 2018-03-14 at 15:09 +0100, Petr Mladek wrote:
> > > > We already prevent crash when dereferencing some obviously broken
> >
On Thu, 29 Mar 2018 16:07:49 +0200
Frederic Weisbecker wrote:
> On Thu, Mar 29, 2018 at 04:01:11PM +0200, Peter Zijlstra wrote:
> > On Thu, Mar 29, 2018 at 03:47:46PM +0200, Frederic Weisbecker wrote:
> > > On Thu, Mar 29, 2018 at 09:16:19AM +0200, Peter Zijlstra wrote:
> > > > On Thu, Mar 29
On 29/03/2018 at 16:40:41 +0200, Andrew Lunn wrote:
> > > > + for (i = 0; i < PHY_MAX_ADDR; i++) {
> > > > + if (mscc_miim_read(bus, i, MII_PHYSID1) < 0)
> > > > + bus->phy_mask |= BIT(i);
> > > > + }
> > >
> > > Why do this? Especially so for the ex
Implement preempting context switch out event as a part of
PERF_RECORD_SWITCH[_CPU_WIDE] record. The event is treated as preemption
one when task->state value of the thread being switched out is TASK_RUNNING;
Percentage of preempting and non-preempting context switches help
understanding the n
Some of the camera subsystems like camss in Qualcommm MSM chipsets
require pixel clock support in camera sensor drivers. So, this commit
adds a default pixel clock rate of 96MHz to OV5640 camera sensor driver.
According to the datasheet, 96MHz can be used as a pixel clock rate for
most of the mode
Some of the camera subsystems like camss in Qualcommm MSM chipsets
require pixel clock support in camera sensor drivers for proper functioning.
So, add a default pixel clock rate of 96MHz to OV5640 camera sensor driver.
According to the datasheet, 96MHz can be used as a pixel clock rate for
most o
On Thu, Mar 29, 2018 at 02:46:44PM +, David Laight wrote:
> From: Dominik Brodowski
> > Sent: 29 March 2018 15:42
> > On Thu, Mar 29, 2018 at 07:20:27AM -0700, Matthew Wilcox wrote:
> > > On Thu, Mar 29, 2018 at 01:22:37PM +0200, Dominik Brodowski wrote:
> > > > At least on 64-bit x86, it will
On 03/28/2018 09:32 PM, Davidlohr Bueso wrote:
> On Wed, 28 Mar 2018, Waiman Long wrote:
>
>> +config DEBUG_RWSEMS
>> +bool "RW Semaphore debugging: basic checks"
>> +depends on DEBUG_KERNEL && RWSEM_SPIN_ON_OWNER
>
> Why depend on RWSEM_SPIN_ON_OWNER? Doesn't everyone benefit from this?
>
On Thu, Mar 29, 2018 at 07:37:29AM -0700, Dave Hansen wrote:
> On 03/29/2018 06:47 AM, Peter Zijlstra wrote:
> > Further I think Dave argued that we should not change the llc-size,
> > because while SNC presents a subset of the cache to local CPUs, for
> > remote data the whole cache is still avail
On 03/28/2018 03:01 PM, Grygorii Strashko wrote:
> Hi Murali,
>
>>
>> +enum qmss_version {
>> +QMSS,
>> +QMSS_LITE,
>
> QMSS_66AK2G
>
OK.
>> +};
>> +
>> struct knav_device {
>> struct device *dev;
>> unsignedbase
> > It sounds like the correct fix is for get_phy_id() to look at the
> > error code for mdiobus_read(bus, addr, MII_PHYSID1). If it is EIO and
> > maybe ENODEV, set *phy_id to 0x and return. The scan code
> > should then do the correct thing.
> >
>
> That could work indeed. Do you want m
On 三, 2018-03-28 at 16:11 +0200, Arnd Bergmann wrote:
> nsec_to_clock_t was traditionally used only in the core kernel, now
> we
> have a sysfs file that needs it from a loadable module, causing a
> link-time error:
>
> ERROR: "nsec_to_clock_t" [drivers/thermal/thermal_sys.ko] undefined!
>
> This
Commit-ID: 6ed70cf342de03c7b11cd4eb032705faeb29d284
Gitweb: https://git.kernel.org/tip/6ed70cf342de03c7b11cd4eb032705faeb29d284
Author: Alexander Shishkin
AuthorDate: Thu, 29 Mar 2018 15:06:48 +0300
Committer: Ingo Molnar
CommitDate: Thu, 29 Mar 2018 16:07:22 +0200
perf/x86/pt, coresig
The __clear_user function is defined to return the number of bytes that
could not be cleared. From the underlying memset / bzero implementation
this means setting register a2 to that number on return. Currently if a
page fault is triggered within the memset_partial block, the value
loaded into a2 o
Store preempting context switch out event into Perf trace as a part of
PERF_RECORD_SWITCH[_CPU_WIDE] record.
Percentage of preempting and non-preempting context switches help
understanding the nature of workloads (CPU or IO bound) that are running
on a machine;
The event is treated as preempt
Em Thu, 29 Mar 2018 19:04:35 +0430
Nasser escreveu:
> On Tue, Mar 27, 2018 at 02:59:21AM +0430, Nasser wrote:
> Hi Mauro,
>
> Thank you for taking time to review my patch.
>
> May be I should rephrase the commit message to something like:
> Use the default register values as suggested in
Print additional 'preempt' tag for PERF_RECORD_SWITCH[_CPU_WIDE] OUT records
when
event header misc field contains PERF_RECORD_MISC_SWITCH_OUT_PREEMPT bit set
designating preemption context switch out event:
tools/perf/perf report -D -i perf.data | grep _SWITCH
0 768361415226 0x27f076 [0x28]:
Append 'p' sign to 'S' tag designating the type of context switch out event so
'Sp' means preemption context switch. Documentation is extended to cover
new presentation changes.
perf script --show-switch-events -F +misc -I -i perf.data:
hdparm 4073 [004] U 762.198265: 3801
From: Rajneesh Bhardwaj
>From Skylake onwards, the platform controller hub (Sunrisepoint PCH) does
not support legacy DMA operations to IO ports 81h-83h, 87h, 89h-8Bh, 8Fh.
Currently this driver registers as syscore ops and its resume function is
called on every resume from S3. On Skylake and Kab
Hei hei,
Am Donnerstag, 29. März 2018, 10:01:26 CEST schrieb Alexander Dahl:
> This is the result:
>
> INTNAME RATE MAX
> 17 [vel timer@fffa] 1837 Ints/s (max: 1912)
> 26 [ vel eth0] 3 Ints/s (max:11)
Above was with v4.16-rc7+
On Fri 2018-03-02 16:17:34, Andy Shevchenko wrote:
> On Fri, 2018-03-02 at 13:53 +0100, Petr Mladek wrote:
> > %p has many modifiers where the pointer is dereferenced. An invalid
> > pointer might cause kernel to crash silently.
> >
> > Note that printk() formats the string under logbuf_lock. Any
On Thu, 29 Mar 2018, Waiman Long wrote:
Because it checks the owner field which is present only if
RWSEM_SPIN_ON_OWNER is defined. Mutex is different in the sense that the
owner field is always there no matter if MUTEX_SPIN_ON_OWNER is set or not.
Ah right; that's after Peter's mutex rewrite i
On 03/29/2018 11:01 AM, Davidlohr Bueso wrote:
> On Thu, 29 Mar 2018, Waiman Long wrote:
>
>> Because it checks the owner field which is present only if
>> RWSEM_SPIN_ON_OWNER is defined. Mutex is different in the sense that the
>> owner field is always there no matter if MUTEX_SPIN_ON_OWNER is set
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