On Wed, Mar 28, 2018 at 01:04:36PM +0200, Peter Zijlstra wrote:
> On Wed, Mar 28, 2018 at 04:25:37PM +1100, Michael Ellerman wrote:
> > Documenting it would definitely be good, but even then I'd be inclined
> > to leave the barrier in our implementation. Matching the documented
> > behaviour is one
On Fri, 23 Mar 2018, Enric Balletbo i Serra wrote:
> From: Shawn Nematbakhsh
>
> Add info useful for debugging USB-PD port state.
>
> Signed-off-by: Shawn Nematbakhsh
> Signed-off-by: Enric Balletbo i Serra
> Reviewed-by: Andy Shevchenko
> ---
>
> Changes in v4: None
> Changes in v3:
> - [5
On 03/27/2018 07:01 PM, Eric W. Biederman wrote:
Stefan Berger writes:
From: Yuqiong Sun
Add new CONFIG_IMA_NS config option. Let clone() create a new IMA
namespace upon CLONE_NEWUSER flag. Attach the ima_ns data structure
to user_namespace. ima_ns is allocated and freed upon IMA namespace
On Fri, 23 Mar 2018, Enric Balletbo i Serra wrote:
> From: Gwendal Grignou
>
> This adds a sysfs attribute (/sys/class/chromeos/cros_ec/kb_wake_angle)
> used to set and get the keyboard wake lid angle. This attribute is
> present only if 2 accelerometers are controlled by the EC.
>
> This patch
On Mon, 26 Mar 2018, Enric Balletbo i Serra wrote:
> Before this patch the enable signal was set before the PWM signal and
> vice-versa on power off. This sequence is wrong, at least, it is on
> the different panels datasheets that I checked, so I inverted the sequence
> to follow the specs.
>
>
On Fri, 23 Mar 2018, sean.w...@mediatek.com wrote:
> From: Sean Wang
>
> Add a description for MT6323 RTC and link it to the detailed binding
> documentation.
>
> Signed-off-by: Sean Wang
> ---
> Documentation/devicetree/bindings/mfd/mt6397.txt | 4 +++-
> 1 file changed, 3 insertions(+), 1 d
On Fri, 23 Mar 2018, sean.w...@mediatek.com wrote:
> From: Sean Wang
>
> Add compatible string as "mt6323-rtc" that will make the OF core spawn
> child devices for the RTC subnode of that MT6323 MFD node.
>
> Signed-off-by: Sean Wang
> ---
> drivers/mfd/mt6397-core.c | 23
On 28/03/2018 12:16, David Rientjes wrote:
> On Wed, 28 Mar 2018, Laurent Dufour wrote:
>
This configuration variable will be used to build the code needed to
handle speculative page fault.
By default it is turned off, and activated depending on architecture
support.
>>>
On Wed, 14 Feb 2018, Fabrice Gasnier wrote:
> Add support for DMAs to STM32 timers. STM32 Timers can support up to 7
> dma requests: up to 4 channels, update, compare and trigger.
> DMAs may be used to transfer data from pwm capture for instance.
> DMA support is made optional, PWM capture support
On Mon, Mar 26, 2018 at 10:29 PM, Masahiro Yamada
wrote:
> Move the test for -fstack-protector(-strong) option to Kconfig.
>
> If the compiler does not support the option, the corresponding menu
> is automatically hidden. If _STRONG is not supported, it will fall
> back to _REGULAR. If _REGULAR
On Mon, Mar 26, 2018 at 10:29 PM, Masahiro Yamada
wrote:
> This will be useful to specify the required compiler version,
> like this:
>
> config FOO
> bool "Use Foo"
> depends on GCC_VERSION >= 408000
> help
> This feature requires GCC 4.8 or newer.
>
> Signed-off
On Tue, Mar 27, 2018 at 12:05:23PM -0400, Mathieu Desnoyers wrote:
> +#ifdef CONFIG_RSEQ
> + struct rseq __user *rseq;
> + u32 rseq_len;
> + u32 rseq_sig;
> + /*
> + * RmW on rseq_event_mask must be performed atomically
> + * with respect to preemption.
> + */
> +
On Tue, Mar 27, 2018 at 12:05:23PM -0400, Mathieu Desnoyers wrote:
> +/*
> + * struct rseq_cs is aligned on 4 * 8 bytes to ensure it is always
> + * contained within a single cache-line. It is usually declared as
> + * link-time constant data.
> + */
> +struct rseq_cs {
> + /* Version of this s
On Mon, Mar 26, 2018 at 10:29 PM, Masahiro Yamada
wrote:
> This will be useful to describe the clang version dependency.
>
> Signed-off-by: Masahiro Yamada
One aspect of clang version checking that may be "weird" (and likely
won't be meaningful for very long as we're about to raise the minimum
g
On Mon, Mar 26, 2018 at 10:29 PM, Masahiro Yamada
wrote:
> CONFIG_GCOV_FORMAT_AUTODETECT compiles either gcc_3_4.c or gcc_4_7.c
> according to your GCC version.
>
> We can achieve the equivalent behavior by setting reasonable dependency
> with the knowledge of the compiler version.
>
> If GCC olde
On Mon, Mar 26, 2018 at 10:29 PM, Masahiro Yamada
wrote:
> As Documentation/kbuild/kconfig-language.txt notes, 'select' should be
> used with care - it forces a lower limit of another symbol, ignoring
> the dependency. In this case, KCOV can select GCC_PLUGINS even if
> 'depends on HAVE_GCC_PLUGI
On Wed, Mar 28, 2018 at 11:14:50AM +0200, Martijn Coenen wrote:
> This can't happen with normal nodes (because you can't get a ref
> to a node you own), but it could happen with the context manager;
> to make the behavior consistent with regular nodes, reject
> transactions into the context manager
On Mon, Mar 26, 2018 at 10:29 PM, Masahiro Yamada
wrote:
> If the target compiler is GCC 4.8 or newer, plugins are compiled with
> HOSTCXX. Otherwise, gcc-plugin.sh will select HOSTCC or HOSTCXX.
>
> To simplify things, drop the HOSTCC support for plugins. If you use
> GCC plugins, the requireme
On Wed, Mar 28, 2018 at 11:06:54AM +0200, Martijn Coenen wrote:
> On Wed, Mar 28, 2018 at 10:19 AM, Greg KH wrote:
> > Does this need to go to older kernels as well?
>
> Yes, this should apply cleanly to 4.14 as well. It won't apply to
> pre-4.14 kernels because of the fine-grained locking change
On Mon, Mar 26, 2018 at 10:29 PM, Masahiro Yamada
wrote:
> For PowerPC, GCC 5.2 is the requirement for GCC plugins. Move the
> version check to Kconfig so that the GCC plugin menus will be hidden
> if an older compiler is in use.
>
> Signed-off-by: Masahiro Yamada
> Acked-by: Andrew Donnellan
>
On Wed, Mar 28, 2018 at 1:28 PM, Greg KH wrote:
> What is different from "v2" you sent before this? No change information
> from v1?
Sorry I messed this up - the first resend did not have "v2" in the
subject but did contain v2 change information, the second resend had
the v2 subject and did not
On Wed, Mar 28, 2018 at 1:29 PM, Greg KH wrote:
> I can mark it for stable, and then when you get the "this did not apply
> to this tree" email, you can send a backported patch to me so I know to
> take that one then.
Ack, thanks.
>
> thanks,
>
> greg k-h
Adds the designware EP device ID entry to pci_endpoint_test driver table
to allow this device to be recognize and handle by the pci_endpoint_test
driver.
Signed-off-by: Gustavo Pimentel
---
drivers/misc/pci_endpoint_test.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/misc/pci_endp
Signed-off-by: Gustavo Pimentel
---
Documentation/devicetree/bindings/pci/designware-pcie.txt | 13 +
1 file changed, 13 insertions(+)
diff --git a/Documentation/devicetree/bindings/pci/designware-pcie.txt
b/Documentation/devicetree/bindings/pci/designware-pcie.txt
index 6300762..4b
Replace magic numbers by a well known define in order to make the code
human readable and also facilitate the code reusability.
Signed-off-by: Gustavo Pimentel
---
drivers/pci/dwc/pcie-designware-host.c | 34 --
drivers/pci/dwc/pcie-designware.h | 1 +
2 fil
The patch set was made against the Bjorn's next branch.
Adds support Designware EP support.
Increases the maximum number of interrupts allowed for Designware IP
controller.
Does a code cleanup on Designware driver:
- Replaces magic numbers without a easy meaning by a well known define
that h
Changes the IP registers size to accommodate the ATU unroll space.
Replaces "ctrlreg" reg-name by "dbi" to be coherent with similar drivers.
Replaces the pcie base address example by a real pcie base address in use.
Signed-off-by: Gustavo Pimentel
---
Documentation/devicetree/bindings/pci/desi
Adds a callback that defines the maximum number of vectors that can be use
by the Root Complex.
Since this is a parameter associated to each SoC IP setting, makes sense to
be configurable and easily visible to future modifications.
The designware IP supports a maximum of 256 vectors.
Signed-off-
On Mon, Mar 26, 2018 at 06:16:29PM +0100, Colin King wrote:
> From: Colin Ian King
>
> Replace several allocation and memcpys with kmemdup and add in some
> missing memory allocation failure checks. Also fix an incorrect
> -EFAULT return with -ENOMEM.
>
> Signed-off-by: Colin Ian King
> ---
>
Replaces lower into upper case characters in comments and debug printks.
This is an attempt to keep the messages coherent within the designware
driver.
Signed-off-by: Gustavo Pimentel
---
drivers/pci/dwc/pcie-designware-ep.c | 16
drivers/pci/dwc/pcie-designware-host.c | 35 +
Replaces a simple division by 2 to a right shiftrotation of 1 bit.
Signed-off-by: Gustavo Pimentel
---
drivers/pci/dwc/pcie-designware-host.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/pci/dwc/pcie-designware-host.c
b/drivers/pci/dwc/pcie-designware-host
The PCIe controller dual mode is capable of operating in host mode as well
as endpoint mode by configuration, therefore this patch aims to add
endpoint mode support to the designware driver.
Signed-off-by: Gustavo Pimentel
---
drivers/pci/dwc/Kconfig | 45 ++--
drivers
On Mon, Mar 26, 2018 at 10:29 PM, Masahiro Yamada
wrote:
> Run scripts/gcc-plugin.sh from Kconfig. Users can enable GCC_PLUGINS
> only when it is supported.
>
> Signed-off-by: Masahiro Yamada
> ---
>
> Changes in v2: None
>
> arch/Kconfig | 4 +++
> scripts/Makefile.gcc-plugins
On Mon, Mar 26, 2018 at 10:29 PM, Masahiro Yamada
wrote:
> The plugin availability is checked in Kconfig, so all{yes,mod}config
> will not be bothered. Remove 'depends on !COMPILE_TEST'.
>
> Signed-off-by: Masahiro Yamada
> ---
>
> Changes in v2:
> - Remove more 'depends on'
>
> arch/Kconfig
PCI endpoint fixes to improve the way 64-bit BARs are handled.
There are still future improvements that could be made:
pci-epf-test.c always allocates space for
6 BARs, even when using 64-bit BARs (which
really only requires us to allocate 3 BARs).
pcitest.sh will print "NOT OKAY" for BAR1,
BAR
Setting a BAR size > 4 GB is invalid if PCI_BASE_ADDRESS_MEM_TYPE_64
flag is not set.
This sanity check is done in pci_epc_set_bar(), so that we don't need
to do this sanity check in all epc->ops->set_bar() implementations.
Signed-off-by: Niklas Cassel
---
drivers/pci/endpoint/pci-epc-core.c |
If a BAR supports 64-bit width or not depends on the hardware,
and should thus not depend on sizeof(dma_addr_t).
If a certain hardware doesn't support 64-bit BARs, its
epc->ops->set_bar() implementation should return -EINVAL
when PCI_BASE_ADDRESS_MEM_TYPE_64 is set.
We can't change pci_epc_set_ba
Hi Chintan,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on v4.16-rc7]
[also build test ERROR on next-20180328]
[cannot apply to arm64/for-next/core tip/x86/core asm-generic/master]
[if your patch is applied to the wrong git tree, please drop us a note to help
Since a 64-bit BAR consists of a BAR pair, and since there is no
BAR after BAR_5, BAR_5 cannot be 64-bits wide.
This sanity check is done in pci_epc_set_bar(), so that we don't need
to do this sanity check in all epc->ops->set_bar() implementations.
Signed-off-by: Niklas Cassel
---
drivers/pci/
A 64-bit BAR consists of a BAR pair, where the second BAR has the
upper bits, so we cannot simply call pci_ioremap_bar() on every single
BAR index.
The second BAR in a BAR pair will not have the IORESOURCE_MEM resource
flag set. Only call ioremap on BARs that have the IORESOURCE_MEM
resource flag
cdns_pcie_ep_set_bar() does some round-up of the BAR size, which means
that a 64-bit BAR can be set-up, even when the flag
PCI_BASE_ADDRESS_MEM_TYPE_64 isn't set.
If a 64-bit BAR was set-up, set the flag PCI_BASE_ADDRESS_MEM_TYPE_64,
so that the calling function can know what BAR width that was ac
If a 64-bit BAR was set-up, we need to skip a BAR,
since a 64-bit BAR consists of a BAR pair.
We need to check what BAR width the epc->ops->set_bar() specific
implementation actually did set-up, since some drivers, like the
Cadence EP controller, sometimes sets up a 64-bit BAR, even though
a 32-bi
Make epc->ops->clear_bar()/pci_epc_clear_bar() take struct *epf_bar.
This is needed so that epc->ops->clear_bar() can clear the BAR pair,
if the BAR is 64-bits wide.
This also makes it possible for pci_epc_clear_bar() to sanity check
the flags.
Signed-off-by: Niklas Cassel
---
drivers/pci/cade
Since a 64-bit BAR consists of a BAR pair, we need to write to both
BARs in the BAR pair to setup the BAR properly.
Signed-off-by: Niklas Cassel
---
drivers/pci/dwc/pcie-designware-ep.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/dwc/pcie-designwar
Since a 64-bit BAR consists of a BAR pair, we need to write to both
BARs in the BAR pair to clear the BAR properly.
Signed-off-by: Niklas Cassel
---
drivers/pci/dwc/pcie-designware-ep.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/pci/dwc/pcie-designware-ep.c
b/drivers/pci/dw
On Fri, Mar 23, 2018 at 11:40:42PM -0700, Quytelda Kahja wrote:
> The "_t" suffix is not needed for structure names in this driver,
> and is a reflection of an older typedef system that is no longer
> in place. Remove the "_t" suffix from every structure defined in this
> driver.
>
> Signed-off-b
2018-03-28 20:22 GMT+09:00 Kees Cook :
> On Mon, Mar 26, 2018 at 10:29 PM, Masahiro Yamada
> wrote:
>> This will be useful to describe the clang version dependency.
>>
>> Signed-off-by: Masahiro Yamada
>
> One aspect of clang version checking that may be "weird" (and likely
> won't be meaningful
Since a 64-bit BAR consists of a BAR pair, and since there is no
BAR after BAR_5, BAR_5 cannot be 64-bits wide.
This sanity check is done in pci_epc_clear_bar(), so that we don't need
to do this sanity check in all epc->ops->clear_bar() implementations.
Signed-off-by: Niklas Cassel
---
Kishon ma
If flag PCI_BASE_ADDRESS_SPACE_IO is set, also having any
PCI_BASE_ADDRESS_MEM_* bit set is invalid.
This sanity check is done in pci_epc_set_bar(), so that we don't need
to do this sanity check in all epc->ops->set_bar() implementations.
Signed-off-by: Niklas Cassel
---
drivers/pci/endpoint/pc
On Wed, Mar 28, 2018 at 9:26 AM, Mathieu Malaterre wrote:
> On Tue, Mar 27, 2018 at 7:33 PM, LEROY Christophe
> wrote:
>> LEROY Christophe a écrit :
>>
>>
>>> Mathieu Malaterre a écrit :
>>>
Christophe,
On Sat, Mar 24, 2018 at 9:10 PM, LEROY Christophe
wrote:
>
> Ma
On Mon, Mar 26, 2018 at 10:29 PM, Masahiro Yamada
wrote:
> As Documentation/kbuild/kconfig-language.txt notes, 'select' should be
> used with care - it forces a lower limit of another symbol, ignoring
> the dependency. In this case, KCOV can select GCC_PLUGINS even if
> 'depends on HAVE_GCC_PLUGI
Hi Stephen,
On Wed, Mar 28, 2018 at 04:00:34PM +1100, Stephen Rothwell wrote:
> Hi all,
>
> Today's linux-next merge of the kvm-arm tree got a conflict in:
>
> arch/arm64/kernel/cpu_errata.c
>
> between commit:
>
> c0cda3b8ee6b ("arm64: capabilities: Update prototype for enable call back")
Add barno and flags to struct epf_bar.
That way we can simplify epc->ops->set_bar()/pci_epc_set_bar()
by passing a struct *epf_bar instead of a whole lot of arguments.
This is needed so that epc->ops->set_bar() implementations can
modify BAR flags. Will be utilized in a succeeding patch.
Signed-o
Smatch complains that idx can be used uninitialized when we check if
(idx < 0). It has to be the first iteration through the loop and the
HIST_FIELD_FL_STACKTRACE bit has to be clear and the HIST_FIELD_FL_VAR
bit has to be set to reach the bug.
Fixes: 30350d65ac56 ("tracing: Add variable support
On Mon, Mar 26, 2018 at 10:29 PM, Masahiro Yamada
wrote:
> This becomes much neater in Kconfig.
>
> Signed-off-by: Masahiro Yamada
Is there a reason this doesn't have a cc-option test, or was this a
silent addition to the compiler? (And as such, should there be a
comment for this in the Kconfig?
On Tue, Mar 27, 2018 at 07:04:51PM +0200, Sebastian Ott wrote:
> What was wrong with the old behavior (let the caller decide - the same
> as with memory allocations)?
The old behavior on most (all?) mainstream architectures is that we
always zero the return value. On x86/i386 this goes back to at
Hi Wei,
i'll add this fix, got this also from the kbuild test robot.
Thank you,
Yael
> -Original Message-
> From: Wei Yongjun
> Sent: Wednesday, 28 March 2018 14:12
> To: Alasdair Kergon ; Mike Snitzer ;
> yaeceh01
> Cc: Wei Yongjun ; dm-de...@redhat.com; linux-
> ker...@vger.kernel.org;
On Tue, Mar 27, 2018 at 08:03:07PM -0500, Shanker Donthineni wrote:
> On 03/27/2018 12:36 PM, Will Deacon wrote:
> > On Tue, Mar 27, 2018 at 09:53:16AM -0500, Shanker Donthineni wrote:
> @@ -154,8 +163,8 @@ static inline void __flush_tlb_range(struct
> vm_area_struct *vma,
>
> +#ifdef CONFIG_INITRAMFS_GENERIC_UNLOAD
> +void free_initrd_mem(unsigned long start, unsigned long end)
> +{
> + free_reserved_area((void *)start, (void *)end, -1, "initrd");
> +}
> +#endif
Given how trivial this is and how many architectures can use it I'd
reverse the polarity and add a C
Hi Gustavo,
On Wed, Mar 28, 2018 at 8:38 AM, Gustavo Pimentel
wrote:
> diff --git a/drivers/pci/dwc/pcie-designware-host.c
> b/drivers/pci/dwc/pcie-designware-host.c
> index 550fdbb..03e9b82 100644
> --- a/drivers/pci/dwc/pcie-designware-host.c
> +++ b/drivers/pci/dwc/pcie-designware-host.c
> @
I goofed up in making a patch file so enumeration is wrong.
I'll upload v7
On 3/28/2018 4:28 PM, Chintan Pandya wrote:
This series of patches are follow up work (and depends on)
Toshi Kani 's patches "fix memory leak/
panic in ioremap huge pages".
This series of patches are tested on 4.9 kernel
Hi Abel,
On Tue, Mar 27, 2018 at 11:23 AM, Abel Vesa wrote:
> From: Dong Aisheng
>
> For init on clocks we should move it at the first place in imx7d_clocks_init()
> before any clock operations, else the clock operation may fail in case the
> clock
> is still not on.
The patch and the commit l
Hi Aniruddha,
On 28/03/18 09:54, Aniruddha Banerjee wrote:
> The kernel documentation states that the locking of the irq-chip
> registers should be handled by the irq-chip driver. In the irq-gic,
> the accesses to the irqchip are seemingly not protected and multiple
> writes to SPIs from different
Hi all,
The directory (not yet three years old although, I freely admit, I've
only recently become aware of it) provides arch. support matrices for
more than 40 generic kernel features that need per-arch. support:
This is a superb project! ;-) and not a simple one given that, to be
effective, th
On 3/28/2018 5:20 PM, kbuild test robot wrote:
@725 if (!pmd_free_pte_page(&pmd[i]))
My bad ! Will fix this in v7
Chintan
--
Qualcomm India Private Limited, on behalf of Qualcomm Innovation Center,
Inc. is a member of the Code Aurora Forum, a Linux Foundation
Collaborative
On Wed, Mar 28, 2018 at 09:34:54AM +0200, Boris Brezillon wrote:
> Hi Peter,
>
> On Mon, 26 Mar 2018 09:35:02 +0200
> Peter Rosin wrote:
>
> > I have an sama5d31-based system with 64MB of memory and a 1920x1080
> > LVDS display wired for 16-bpp. When I enable legacy fbdev support,
> > the contig
On Wed, Mar 28, 2018 at 2:04 PM, Christoph Hellwig wrote:
>> +#ifdef CONFIG_INITRAMFS_GENERIC_UNLOAD
>> +void free_initrd_mem(unsigned long start, unsigned long end)
>> +{
>> + free_reserved_area((void *)start, (void *)end, -1, "initrd");
>> +}
>> +#endif
>
> Given how trivial this is and ho
On Wed, 28 Mar 2018 14:22:36 +0200
Daniel Vetter wrote:
> On Wed, Mar 28, 2018 at 09:34:54AM +0200, Boris Brezillon wrote:
> > Hi Peter,
> >
> > On Mon, 26 Mar 2018 09:35:02 +0200
> > Peter Rosin wrote:
> >
> > > I have an sama5d31-based system with 64MB of memory and a 1920x1080
> > > LVDS
Hi Vadim,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on net-next/master]
[also build test WARNING on v4.16-rc7 next-20180328]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day
On Tue, Mar 27, 2018 at 12:05:23PM -0400, Mathieu Desnoyers wrote:
> +static int rseq_update_cpu_id(struct task_struct *t)
> +{
> + uint32_t cpu_id = raw_smp_processor_id();
u32
> +
> + if (__put_user(cpu_id, &t->rseq->cpu_id_start))
> + return -EFAULT;
> + if (__put_user(
This patch ("mm/vmalloc: Add interfaces to free unmapped
page table") adds following 2 interfaces to free the page
table in case we implement huge mapping.
pud_free_pmd_page() and pmd_free_pte_page()
Some architectures (like arm64) needs to do proper TLB
maintanance after updating pagetable entry
This series of patches are follow up work (and depends on)
Toshi Kani 's patches "fix memory leak/
panic in ioremap huge pages".
This series of patches are tested on 4.9 kernel with Cortex-A75
based SoC.
These patches can also go into '-stable' branch (if accepted)
for 4.6 onwards.
>From V6->V7:
Add an interface to invalidate intermediate page tables
from TLB for kernel.
Signed-off-by: Chintan Pandya
---
arch/arm64/include/asm/tlbflush.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/include/asm/tlbflush.h
b/arch/arm64/include/asm/tlbflush.h
index 9e82dd7..6a4816d
Implement pud_free_pmd_page() and pmd_free_pte_page().
Implementation requires,
1) Clearing off the current pud/pmd entry
2) Invalidate TLB which could have previously
valid but not stale entry
3) Freeing of the un-used next level page tables
Signed-off-by: Chintan Pandya
---
arch/arm64/
This commit 15122ee2c515a ("arm64: Enforce BBM for huge
IO/VMAP mappings") is a temporary work-around until the
issues with CONFIG_HAVE_ARCH_HUGE_VMAP gets fixed.
Revert this change as we have fixes for the issue.
Signed-off-by: Chintan Pandya
---
arch/arm64/mm/mmu.c | 8
1 file change
when pid is bigger than PID_MAX_DEFAULT, the comm of task
is <...>, it is better use pid_max to compare
Signed-off-by: Wang Yu
---
kernel/trace/trace.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
mode change 100644 => 100755 kernel/trace/trace.c
diff --git a/kernel/trace/trace.c b/ke
On Tue, Mar 27, 2018 at 09:13:32PM +0200, Thorsten Leemhuis wrote:
> On 26.03.2018 01:37, Linus Torvalds wrote:
> > […] Anyway. Go out and test. And let's hope next week is nice and calm and
> > I can release the final 4.16 next Sunday without any extra rc's.
> >
> >Linus
>
> Hi!
On 28/03/2018 10.28, Christoph Hellwig wrote:
I really don't want more lightnvm cruft in the core. We'll need
a proper abstraction.c
I agree, we should get that moving, and make a proper abstraction for
it. Also with respect to how an SMR interface in general is integrated
into NVMe.
The
On Sun, Mar 25, 2018 at 12:59:53PM +0200, Christian König wrote:
> Use this function to set an sg entry to point to device resources mapped
> using dma_map_resource(). The page pointer is set to NULL and only the DMA
> address, length and offset values are valid.
NAK. Please provide a higher leve
On Sun, Mar 25, 2018 at 12:59:54PM +0200, Christian König wrote:
> From: "wda...@nvidia.com"
>
> Add an interface to find the first device which is upstream of both
> devices.
Please work with Logan and base this on top of the outstanding peer
to peer patchset.
On 03/28/2018 08:14 AM, Dr. Greg Wettstein wrote:
On Wed, Mar 28, 2018 at 07:10:12AM -0400, Stefan Berger wrote:
Good morning, I hope the day is starting out well for everyone.
On 03/27/2018 07:01 PM, Eric W. Biederman wrote:
Stefan Berger writes:
From: Yuqiong Sun
Add new CONFIG_IMA_NS
On Wed, Mar 28, 2018 at 07:10:12AM -0400, Stefan Berger wrote:
Good morning, I hope the day is starting out well for everyone.
> On 03/27/2018 07:01 PM, Eric W. Biederman wrote:
> >Stefan Berger writes:
> >
> >>From: Yuqiong Sun
> >>
> >>Add new CONFIG_IMA_NS config option. Let clone() create
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Hi Linus,
Please pull some more powerpc fixes for 4.16. Apologies if this is a bit
big at rc7, but they're all reasonably important fixes. None are
actually for new code, so they aren't indicative of 4.16 being in bad
shape from our point of view.
On Tue, Mar 27, 2018 at 8:15 AM, liwei (CM) wrote:
> Hi, Arnd
>
> At present our ufs module mainly has four clocks from the outside:
> hclk_ufs: main clock of ufs controller ,freq is 207.5MHz
> cfg_phy_clk: configuration clock of MPHY, freq is 51.875MHz
> ref_phy_clk: reference clock of MPHY
On Tue, Mar 27, 2018 at 12:05:23PM -0400, Mathieu Desnoyers wrote:
> diff --git a/kernel/sched/sched.h b/kernel/sched/sched.h
> index fb5fc458547f..66b070444a7e 100644
> --- a/kernel/sched/sched.h
> +++ b/kernel/sched/sched.h
> @@ -1249,6 +1249,7 @@ static inline void __set_task_cpu(struct task_str
I am leaving Axis, so this address will bounce in the not too
distant future.
Fortunately, I will still be working with the community.
Signed-off-by: Niklas Cassel
---
MAINTAINERS | 2 --
1 file changed, 2 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 1f8cc197f829..27f79a94a20a 100
On Wed, Mar 28, 2018 at 02:29:46PM +0200, Peter Zijlstra wrote:
> > +static int rseq_get_rseq_cs(struct task_struct *t,
> > + unsigned long *start_ip,
> > + unsigned long *post_commit_offset,
> > + unsigned long *abort_ip,
> > +
During probe check whether the vdd-io regulator of sdhc platform device
can support 1.8V and 3V and store this information as a capability of
platform device.
Signed-off-by: Vijay Viswanath
---
drivers/mmc/host/sdhci-msm.c | 36 +++-
1 file changed, 35 insertions(
>From the HPG:
In some platform, SDCC controller can be connected to either an eMMC device or
an SD card. The PADs for SD card are dual-voltage that support 3v/1.8v. Those
PADs have a control signal (io_pad_pwr_switch/mode18 ) that indicates whether
the PAD works in 3v or 1.8v.
For SD usage the d
From: Krishna Konda
The PADs for SD card are dual-voltage that support 3v/1.8v. Those PADs
have a control signal (io_pad_pwr_switch/mode18 ) that indicates
whether the PAD works in 3v or 1.8v.
SDHC core on msm platforms should have IO_PAD_PWR_SWITCH bit set/unset
based on actual voltage used fo
On Wed 28-03-18 01:34:24, Li,Rongqing wrote:
> OK, I see this commit, I will test the latest kernel
>
> commit 1c610d5f93c709df56787f50b3576704ac271826
> Author: Andrey Ryabinin
> Date: Thu Mar 22 16:17:42 2018 -0700
Yes, that should fix your memcg OOM
--
Michal Hocko
SUSE Labs
On Mon, Mar 26, 2018 at 02:57:35PM -0400, Steven Rostedt wrote:
> On Mon, 26 Mar 2018 10:53:13 +0200
> Andrea Parri wrote:
>
> > > --- a/kernel/smp.c
> > > +++ b/kernel/smp.c
> > > @@ -724,6 +724,30 @@ void kick_all_cpus_sync(void)
> > > }
> > > EXPORT_SYMBOL_GPL(kick_all_cpus_sync);
> > >
>
Hi Fabio,
On 28/03/2018 13:05, Fabio Estevam wrote:
> Hi Gustavo,
>
> On Wed, Mar 28, 2018 at 8:38 AM, Gustavo Pimentel
> wrote:
>
>> diff --git a/drivers/pci/dwc/pcie-designware-host.c
>> b/drivers/pci/dwc/pcie-designware-host.c
>> index 550fdbb..03e9b82 100644
>> --- a/drivers/pci/dwc/pcie-d
On Wed, Mar 21, 2018 at 02:13:33PM -0500, Yazen Ghannam wrote:
> From: Yazen Ghannam
>
> It's possible that a system can be used without any DRAM populated on
> one or more physical Dies on multi-die systems. Firmware will not
> enable DRAM ECC on Dies without DRAM. Users will then see a message
+linux-ia64
On 3/27/2018 11:02 AM, Paul E. McKenney wrote:
> On Tue, Mar 27, 2018 at 02:11:27PM +0100, Will Deacon wrote:
>> The section of memory-barriers.txt that describes the dma_Xmb() barriers
>> has an incorrect example claiming that a wmb() is required after writing
>> to coherent memory in
On 28/03/2018 12:29, Alexander Dahl wrote:
> Hello Daniel,
>
> Am Dienstag, 27. März 2018, 13:30:22 CEST schrieb Daniel Lezcano:
>> Can you can give a rough amount for the irq rate on the timer ?
>
> I used itop [1] now to get a rough estimate. First with kernel v4.14.29-rt25
> (fully preempt RT
+Arnd
On Wed, Mar 28, 2018 at 3:32 AM, Libor Pechacek wrote:
> Support for CRIS and Meta was dropped.
>
> Signed-off-by: Libor Pechacek
> Fixes: bb6fb6dfcc17 ("metag: Remove arch/metag/")
> Fixes: c690eddc2f3b ("CRIS: Drop support for the CRIS port")
> Cc: James Hogan
> Cc: Jesper Nilsson
> Cc
On 03/27/2018 07:13 PM, Davidlohr Bueso wrote:
> On Tue, 27 Mar 2018, Waiman Long wrote:
>
>> Add a new master LOCK_DEBUGGING Kconfig option to turn on all the lock
>> debugging options except the selftests and the torture tests.
>
> For what purpose?
>
> I'm not sure we want yet another config deb
On Mon 26-03-18 15:22:32, Joe Perches wrote:
> mm/*.c files use symbolic and octal styles for permissions.
>
> Using octal and not symbolic permissions is preferred by many as more
> readable.
>
> https://lkml.org/lkml/2016/8/2/1945
>
> Prefer the direct use of octal for permissions.
>
> Done u
After issuing a request an endless loop was used to read the
completion state from memory which is asynchronously updated
by the ZIP coprocessor.
Add an upper bound to the retry attempts to prevent a CPU getting stuck
forever in case of an error. Additionally, add a read memory barrier
and a small
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