On Mon, Feb 12, 2018 at 06:37:43PM +0100, Peter Zijlstra wrote:
> On Mon, Feb 12, 2018 at 05:11:31PM +, Mel Gorman wrote:
> > +static void
> > +update_wa_numa_placement(struct task_struct *p, int prev_cpu, int target)
> > +{
> > + unsigned long interval;
> > +
> > + if (!static_branch_likel
From: Jean-Michel Hautbois
The ADV7604 has thirteen 256-byte maps that can be accessed via the main
I²C ports. Each map has it own I²C address and acts as a standard slave
device on the I²C bus.
Allow a device tree node to override the default addresses so that
address conflicts with other devic
From: Kieran Bingham
The ADV7511 has four 256-byte maps that can be accessed via the main I²C
ports. Each map has it own I²C address and acts as a standard slave
device on the I²C bus.
Extend the device tree node bindings to be able to override the default
addresses so that address conflicts wit
From: Kieran Bingham
Back in 2014, Jean-Michel provided patches [0] to implement a means of
describing software defined I2C addresses for devices through the DT nodes.
The patch to implement the function "i2c_new_secondary_device()" was integrated,
but the corresponding driver update didn't get
The number of high slices a process might use now depends on its
address space size, and what allocation address it has requested.
This patch uses that limit throughout call chains where possible,
rather than use the fixed SLICE_NUM_HIGH for bitmap operations.
This saves some cost for processes th
Calculating the slice mask can become a signifcant overhead for
get_unmapped_area. This patch adds a struct slice_mask for
each page size in the mm_context, and keeps these in synch with
the slices psize arrays and slb_addr_limit.
This saves about 30% kernel time on a single-page mmap/munmap micro
Pass around const pointers to struct slice_mask where possible, rather
than copies of slice_mask, to reduce stack and call overhead.
checkstack.pl gives, before:
0x0de4 slice_get_unmapped_area [slice.o]: 656
0x1b4c is_hugepage_only_range [slice.o]:512
0x075c slice
The slice_mask cache was a basic conversion which copied the slice
mask into caller's structures, because that's how the original code
worked. In most cases the pointer can be used directly instead, saving
a copy and an on-stack structure.
This also converts the slice_mask bit operation helpers to
Rather than build slice masks from a range then use that to check for
fit in a candidate mask, implement slice_check_range_fits that checks
if a range fits in a mask directly.
This allows several structures to be removed from stacks, and also we
don't expect a huge range in a lot of these cases, s
From: Kieran Bingham
The ADV7511 has four 256-byte maps that can be accessed via the main I²C
ports. Each map has it own I²C address and acts as a standard slave
device on the I²C bus.
Allow a device tree node to override the default addresses so that
address conflicts with other devices on the
On 02/12/18 04:21, Bean Huo (beanhuo) wrote:
I am looking at UFS error handling, but I didn't notice re-issues
requests with UTP error to the host controller. According UFS host
spec, "host software either completes the request that had the error
and requests still outstanding with error to highe
From: Kieran Bingham
The r8a7792 Wheat board has two ADV7513 devices sharing a single i2c
bus, however in low power mode the ADV7513 will reset it's slave maps to
use the hardware defined default addresses.
The ADV7511 driver was adapted to allow the two devices to be registered
correctly - but
From: Jean-Michel Hautbois
The ADV7604 has thirteen 256-byte maps that can be accessed via the main
I²C ports. Each map has it own I²C address and acts as a standard slave
device on the I²C bus.
Extend the device tree node bindings to be able to override the default
addresses so that address con
As a helper function exists for calculating register offsets lets use
that rather than open coding with the reg_stride.
Signed-off-by: Charles Keepax
---
drivers/base/regmap/regmap.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/base/regmap/regmap.c b/drivers/base/r
The current implementation is broken for regmaps that have a reg_stride,
since it doesn't take the stride into account. Correct this by using the
helper function to calculate the register offset.
Fixes: f01ee60fffa4 ("regmap: implement register striding")
Signed-off-by: Charles Keepax
---
driver
A bulk read can be implemented either through regmap_raw_read, or
by reading each register individually using regmap_read. Both
regmap_read and regmap_bulk_read should return values in native
endian. In the individual case the current implementation calls
format_val to put the data into the output
The cache pointer points to the actual memory used by the cache, as the
comparison here is looking for the type of the cache it should check
against cache_type.
Fixes: 1ea975cf1ef5 ("regmap: Add a function to check if a regmap register is
cached")
Signed-off-by: Charles Keepax
---
drivers/base/
On 07/02/18 14:32, Marc Zyngier wrote:
> From: Robin Murphy
>
> Juno's GICv2m implementation consists of four frames providing 32
> interrupts each. Since it is possible to plug in enough PCIe endpoints
> to consume more than 32 MSIs, and the driver already has a bodge to
> handle multiple fram
On 12/02/18 13:02, Steven Rostedt wrote:
> On Mon, 12 Feb 2018 18:43:12 +0100
> Juri Lelli wrote:
>
> > However, this surely needs to be fixed here. It's tracking the sum of
> > all tasks' (across CPUs) bandwidth admitted on the system, so that's why
> > it's called dl_total_bw. Incremented when
On Sun, Dec 03, 2017 at 12:31:01PM -0800, syzbot wrote:
> syzkaller has found reproducer for the following crash on
> 4131d5166185d0d75b5f1d4bf362a9e0bac05598
> git://git.cmpxchg.org/linux-mmots.git/master
> compiler: gcc (GCC) 7.1.1 20170620
> .config is attached
> Raw console output is attached.
Hey,
When I try to boot my A31s (Bananapi M2) u-boot is showing only Starting
kernel ... . After enabling the earlyprintk I could capture this log: [1].
After reverting those 5 commits from Chen-Yu I was able to boot again:
clk: sunxi-ng: Support fixed post-dividers on NM style clocks
7d333e
On 12/02/18 18:17, Sudeep Holla wrote:
On 07/02/18 14:32, Marc Zyngier wrote:
From: Robin Murphy
Juno's GICv2m implementation consists of four frames providing 32
interrupts each. Since it is possible to plug in enough PCIe endpoints
to consume more than 32 MSIs, and the driver already has a
On 02/12/2018 07:11 PM, Kieran Bingham wrote:
[...]
> + /*
> + * The adv75xx resets its addresses to defaults during low power power
> + * mode. Because we have two ADV7513 devices on the same bus, we must
> + * change both of them away from the defaults so that they do not
> +
On Thu, Feb 08, 2018 at 02:13:27PM +, Colin King wrote:
> From: Colin Ian King
>
> The function btrfs_test_extent_map requires a void argument to be ANSI C
> compliant and so it matches the prototype in fs/btrfs/tests/btrfs-tests.h
>
> Cleans up sparse warning:
> fs/btrfs/tests/extent-map-te
Hi Robin,
On 12/02/18 18:22, Robin Murphy wrote:
> On 12/02/18 18:17, Sudeep Holla wrote:
>>
>>
>> On 07/02/18 14:32, Marc Zyngier wrote:
>>> From: Robin Murphy
>>>
>>> Juno's GICv2m implementation consists of four frames providing 32
>>> interrupts each. Since it is possible to plug in enough PC
Hi Sudeep,
On 12/02/18 18:17, Sudeep Holla wrote:
>
>
> On 07/02/18 14:32, Marc Zyngier wrote:
>> From: Robin Murphy
>>
>> Juno's GICv2m implementation consists of four frames providing 32
>> interrupts each. Since it is possible to plug in enough PCIe endpoints
>> to consume more than 32 MSIs,
On Mon, 2018-02-12 at 11:54 -0500, bfie...@fieldses.org wrote:
> On Sat, Feb 10, 2018 at 01:41:55AM +, Trond Myklebust wrote:
> > On Fri, 2018-02-09 at 23:06 -0200, Thiago Rafael Becker wrote:
> > > When investigating reasons for nfs failures, packet dumps arei
> > > eventually used.
> > > Find
Hi Lars,
Thanks for your review!
On 12/02/18 18:24, Lars-Peter Clausen wrote:
> On 02/12/2018 07:11 PM, Kieran Bingham wrote:
> [...]
>> +/*
>> + * The adv75xx resets its addresses to defaults during low power power
>> + * mode. Because we have two ADV7513 devices on the same bus, we
On 02/11/2018 06:18 PM, Jaedon Shin wrote:
> Since commit ad67b74d2469 ("printk: hash addresses printed with %p")
> pointers are being hashed when printed. Displaying the virtual memory at
> bootup time is not helpful. so delete the prints.
>
> Signed-off-by: Jaedon Shin
Acked-by: Florian Fainel
On Mon, Feb 12, 2018 at 06:11:02PM +0100, Dmitry Vyukov wrote:
> The commit on which it was triggered already includes this fix. So
> there must be another bug.
Any chance of bisecting it?
nvme cq irq is freed based on queue_count. When the sq/cq creation
fails, irq will not be setup. free_irq will warn 'Try to free
already-free irq'.
To fix it, we only increase online_queues when adminq/sq/cq are
created and associated irq is setup. Then suspend queues based
on online_queues.
S
On Mon, Feb 12, 2018 at 05:50:12PM +, Chris Wilson wrote:
> Quoting Lyude Paul (2018-02-12 17:46:11)
> > On Sun, 2018-02-11 at 10:38 +0100, Lukas Wunner wrote:
> > > Introduce a helper to determine if the current task is an output poll
> > > worker.
> > >
> > > This allows us to fix a long-sta
Thanks, I picked this up for 4.17 (unless someone thinks
this is 4.16-rc material?)
On 02/10/2018 02:17 AM, Alexey Skidanov wrote:
Current ion defined allocation ioctl doesn't allow to specify the requested
allocation alignment. CMA heap allocates buffers aligned on buffer size
page order.
Sometimes, the alignment requirement is less restrictive. In such cases,
providing specif
Currently, we will unquiesce the queues after the controller is
shutdown to avoid residual requests to be stuck. In fact, we can
do it more cleanly, just wait freeze and drain the queue in
nvme_dev_disable and finally leave the queues quiesced.
Does this fix a bug? What is the benefit of leavi
On 12 February 2018 at 18:04, Gustavo A. R. Silva
wrote:
> Hi Ard,
>
> On 02/08/2018 03:54 AM, Ard Biesheuvel wrote:
>>
>> On 7 February 2018 at 16:00, Gustavo A. R. Silva
>> wrote:
>>>
>>> Add suffix ULL to constant 9 in order to give the compiler complete
>>> information about the proper arithm
Many users of the mailbox controllers depend on the shared memory
between the two end points to exchange the main data while using simple
doorbell mechanism to alert the end points of the presence of a message.
This patch defines device tree bindings to represent such shared memory
in a generic wa
The power protocol is intended for management of power states of various
power domains. The power domain management protocol provides commands to
describe the protocol version, discover the implementation specific
attributes, set and get the power state of a domain.
This patch adds support for the
The cpufreq core provides option for drivers to implement fast_switch
callback which is invoked for frequency switching from interrupt context.
This patch adds support for fast_switch callback in SCMI cpufreq driver
by making use of polling based SCMI transfer. It also sets the flag
fast_switch_po
Looks good,
Reviewed-by: Sagi Grimberg
Create a driver to add support for SoC sensors exported by the System
Control Processor (SCP) via the System Control and Management Interface
(SCMI). The supported sensor types is one of voltage, temperature,
current, and power.
The sensor labels and values provided by the SCP are exported via the
Looks good,
Reviewed-by: Sagi Grimberg
On some ARM based systems, a separate Cortex-M based System Control
Processor(SCP) provides the overall power, clock, reset and system
control including CPU DVFS. SCMI Message Protocol is used to
communicate with the SCP.
This patch adds a cpufreq driver for such systems using SCMI interface
to dr
In order to maintain the channel information per protocol, we need
some sort of list or hashtable to hold all this information. IDR
provides sparse array mapping of small integer ID numbers onto arbitrary
pointers. In this case the arbitrary pointers can be pointers to the
channel information.
Thi
It's useful to know the maximum types of sensor supported by hwmon
framework. It can be used to allocate some data structures when sorting
the monitors based on their type.
This will be used by scmi hwmon support.
Cc: linux-hw...@vger.kernel.org
Acked-by: Guenter Roeck
Signed-off-by: Sudeep Holl
This looks fine to me, but I really want Keith and/or Christoph to have
a look as well.
This patch hooks up the support for device power domain provided by
SCMI using the Linux generic power domain infrastructure.
Cc: Kevin Hilman
Reviewed-by: Ulf Hansson
Signed-off-by: Sudeep Holla
---
drivers/firmware/Kconfig | 13 +++
drivers/firmware/arm_scmi/Makefile
On Mon 12-02-18 17:16:40, Eugeniu Rosca wrote:
> Hi Michal,
>
> On Mon, Feb 12, 2018 at 04:03:14PM +0100, Michal Hocko wrote:
> > On Sat 03-02-18 13:24:22, Eugeniu Rosca wrote:
> > [...]
> > > That said, I really hope this won't be the last comment in the thread
> > > and appropriate suggestions w
On some ARM based systems, a separate Cortex-M based System Control
Processor(SCP) provides the overall power, clock, reset and system
control. System Control and Management Interface(SCMI) Message Protocol
is defined for the communication between the Application Cores(AP)
and the SCP.
This patch
In order to implement fast CPU DVFS switching, we need to perform all
DVFS operations atomically. Since SCMI transfer already provide option
to choose between pooling vs interrupt driven(default), we can opt for
polling based transfers for set,get performance domain operations.
This patch adds opt
It would be useful to have options to perform some SCMI transfers
atomically by polling for the completion flag instead of interrupt
driven. The SCMI specification has option to disable the interrupt and
poll for the completion flag in the shared memory.
This patch adds support for polling based S
On 2/12/18 8:25 AM, Thomas Gleixner wrote:
On Tue, 6 Feb 2018, Yang Shi wrote:
+ /*
+* Reuse objs from the global free list, they will be reinitialized
+* when allocating
+*/
+ while (obj_nr_tofree > 0 && (obj_pool_free < obj_pool_min_free)) {
+
In order to support per-protocol channels if available, we need to
factor out all the mailbox channel information(Tx/Rx payload and
channel handle) out of the main SCMI instance information structure.
This patch refactors the existing channel information into a separate
chan_info structure.
Cc: A
Now that we have basic support for all the protocols in the
specification, let's probe them individually and initialise them.
Cc: Arnd Bergmann
Cc: Greg Kroah-Hartman
Signed-off-by: Sudeep Holla
---
drivers/firmware/arm_scmi/driver.c | 51 +-
1 file changed,
The SCMI is intended to allow OSPM to manage various functions that are
provided by the hardware platform it is running on, including power and
performance functions. SCMI provides two levels of abstraction, protocols
and transports. Protocols define individual groups of system control and
manageme
The sensor protocol provides functions to manage platform sensors, and
provides the commands to describe the protocol version and the various
attribute flags. It also provides commands to discover various sensors
implemented and managed by the platform, read any sensor synchronously
or asynchronous
The clock protocol is intended for management of clocks. It is used to
enable or disable clocks, and to set and get the clock rates. This
protocol provides commands to describe the protocol version, discover
various implementation specific attributes, describe a clock, enable
and disable a clock an
The base protocol describes the properties of the implementation and
provide generic error management. The base protocol provides commands
to describe protocol version, discover implementation specific
attributes and vendor/sub-vendor identification, list of protocols
implemented and the various ag
The performance protocol is intended for the performance management of
group(s) of device(s) that run in the same performance domain. It
includes even the CPUs. A performance domain is defined by a set of
devices that always have to run at the same performance level.
For example, a set of CPUs that
The SCMI specification encompasses various protocols. However, not every
protocol has to be present on a given platform/implementation as not
every protocol is relevant for it.
Furthermore, the platform chooses which protocols it exposes to a given
agent. The only protocol that must be implemented
This patch adds devicetree binding for System Control and Management
Interface (SCMI) Message Protocol used between the Application Cores(AP)
and the System Control Processor(SCP). The MHU peripheral provides a
mechanism for inter-processor communication between SCP's M3 processor
and AP.
SCP offe
On Mon, Feb 12, 2018 at 11:10:41AM +0100, Jean Delvare wrote:
> Hi Guneter,
>
> Sorry for the delay :(
>
> On Sat, 30 Dec 2017 08:50:57 -0800, Guenter Roeck wrote:
> > Accesses to SB800_PIIX4_SMB_IDX can occur from multiple drivers.
> > Use request_muxed_region() to ensure synchronization.
>
> W
Hi all,
ARM System Control and Management Interface(SCMI) is more flexible and
easily extensible than any of the existing interfaces. Many vendors were
involved in the making of this formal specification and is now published[1].
There is a strong trend in the industry to provide micro-controllers
On 2/12/18 7:54 AM, Thomas Gleixner wrote:
On Mon, 12 Feb 2018, Thomas Gleixner wrote:
On Tue, 6 Feb 2018, Yang Shi wrote:
+ /*
+* The objs on the pool list might be allocated before the work is
+* run, so recheck if pool list it full or not, if not fill pool
+*
On Mon, Feb 12, 2018 at 09:01:46AM -0600, Bjorn Helgaas wrote:
> On Sun, Feb 11, 2018 at 10:25:25AM +0100, Lukas Wunner wrote:
> > On Sat, Feb 10, 2018 at 08:48:15PM -0600, Bjorn Helgaas wrote:
> > > 7570a333d8b0 ("PCI: Add pcie_hp=nomsi to disable MSI/MSI-X for pciehp
> > > driver") added the "pci
On Mon, Feb 12, 2018 at 4:45 AM, Lukas Wunner wrote:
> On Mon, Feb 12, 2018 at 09:03:26AM +, Mike Lothian wrote:
>> On 12 February 2018 at 03:39, Lukas Wunner wrote:
>> > On Mon, Feb 12, 2018 at 12:35:51AM +, Mike Lothian wrote:
>> > > I've not been able to reproduce the original problem
The ISL12026 is a combination RTC and EEPROM device with I2C
interface. The standard RTC driver interface is provided. The EEPROM
is accessed via the NVMEM interface via the "eeprom0" directory in the
sysfs entry for the device.
Signed-off-by: David Daney
---
.../devicetree/bindings/rtc/isil,i
On Mon, Feb 12, 2018 at 08:05:22PM +0530, Himanshu Jha wrote:
> But these should be done when we have *more* instances.
>
> For eg:
> I added a tab space in function static int adis16201_read_raw() argument
> to match open parentheses in this patch. But I also added tabs while
> removing and addi
Changes since v1:
Added changes in these files:
drivers/infiniband/hw/usnic/usnic_transport.c
drivers/staging/lustre/lnet/lnet/lib-socket.c
drivers/target/iscsi/iscsi_target_login.c
drivers/vhost/net.c
fs/dlm/lowcomms.c
fs/ocfs2/cluster/tcp.c
security/tomoyo/network.c
On 02/12/2018 10:59 AM, David Daney wrote:
The ISL12026 is a combination RTC and EEPROM device with I2C
interface. The standard RTC driver interface is provided. The EEPROM
is accessed via the NVMEM interface via the "eeprom0" directory in the
sysfs entry for the device.
Signed-off-by: David D
Hi Thomas,
On 1/16/2018 3:38 AM, Thomas Gleixner wrote:
> On Mon, 15 Jan 2018, Hindman, Gavin wrote:
>>> From: linux-kernel-ow...@vger.kernel.org [mailto:linux-kernel-
>>> ow...@vger.kernel.org] On Behalf Of Thomas Gleixner
>>> On Fri, 17 Nov 2017, Reinette Chatre wrote:
2) The most recent k
On 02/12/2018 10:45 AM, Ard Biesheuvel wrote:
> On 12 February 2018 at 18:04, Gustavo A. R. Silva
> wrote:
>> Hi Ard,
>>
>> On 02/08/2018 03:54 AM, Ard Biesheuvel wrote:
>>>
>>> On 7 February 2018 at 16:00, Gustavo A. R. Silva
>>> wrote:
Add suffix ULL to constant 9 in order to give the
On Mon, Feb 12, 2018 at 08:43:58PM +0200, Sagi Grimberg wrote:
>
> > Currently, we will unquiesce the queues after the controller is
> > shutdown to avoid residual requests to be stuck. In fact, we can
> > do it more cleanly, just wait freeze and drain the queue in
> > nvme_dev_disable and finally
On 02/12/2018 08:42 PM, Laura Abbott wrote:
> On 02/10/2018 02:17 AM, Alexey Skidanov wrote:
>> Current ion defined allocation ioctl doesn't allow to specify the
>> requested
>> allocation alignment. CMA heap allocates buffers aligned on buffer size
>> page order.
>>
>> Sometimes, the alignment r
On 12 February 2018 at 19:10, Florian Fainelli wrote:
> On 02/12/2018 10:45 AM, Ard Biesheuvel wrote:
>> On 12 February 2018 at 18:04, Gustavo A. R. Silva
>> wrote:
>>> Hi Ard,
>>>
>>> On 02/08/2018 03:54 AM, Ard Biesheuvel wrote:
On 7 February 2018 at 16:00, Gustavo A. R. Silva
w
Hi Raghavendra,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on v4.15]
[also build test ERROR on next-20180212]
[cannot apply to tip/perf/core]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https
On 02/12/2018 11:11 AM, Ard Biesheuvel wrote:
> On 12 February 2018 at 19:10, Florian Fainelli wrote:
>> On 02/12/2018 10:45 AM, Ard Biesheuvel wrote:
>>> On 12 February 2018 at 18:04, Gustavo A. R. Silva
>>> wrote:
Hi Ard,
On 02/08/2018 03:54 AM, Ard Biesheuvel wrote:
>
>
On Mon, 2018-02-12 at 18:29 +0100, Peter Zijlstra wrote:
> On Mon, Feb 12, 2018 at 02:58:56PM +, Mel Gorman wrote:
> > diff --git a/kernel/sched/fair.c b/kernel/sched/fair.c
> > index c1091cb023c4..28c8d9c91955 100644
> > --- a/kernel/sched/fair.c
> > +++ b/kernel/sched/fair.c
> > @@ -5747,7 +5
This looks good.
Reviewed-by: Keith Busch
On 12/02/18 18:27, Marc Zyngier wrote:
Hi Sudeep,
On 12/02/18 18:17, Sudeep Holla wrote:
On 07/02/18 14:32, Marc Zyngier wrote:
From: Robin Murphy
Juno's GICv2m implementation consists of four frames providing 32
interrupts each. Since it is possible to plug in enough PCIe endpoints
to con
Looks good.
Reviewed-by: Keith Busch
On Mon, Feb 12, 2018 at 1:37 AM, Ingo Molnar wrote:
>
> Ok, so this does not look _that_ complicated, and the .text savings are
> significant:
Honestly, I think we should do it. 3kB of assembly code is noticeable.
Also, that patch actually allows more cleanups and simplifications.
Look at the "i
On Mon, Feb 12, 2018 at 08:47:47PM +0200, Sagi Grimberg wrote:
> This looks fine to me, but I really want Keith and/or Christoph to have
> a look as well.
This looks fine to me as well.
Reviewed-by: Keith Busch
On Mon, Feb 12, 2018 at 6:47 AM, Yonghong Song wrote:
>
>
> On 2/11/18 11:18 AM, Mathieu Malaterre wrote:
>>
>> Hi,
>>
>> On Sun, Feb 11, 2018 at 5:54 PM, Alexei Starovoitov
>> wrote:
>>>
>>> On Sun, Feb 11, 2018 at 7:24 AM, Mathieu Malaterre
>>> wrote:
Alexei,
Could you plea
On Wed, 2018-02-07 at 10:00 -0600, Gustavo A. R. Silva wrote:
> Add suffix ULL to constant 9 in order to give the compiler complete
> information about the proper arithmetic to use. Notice that this
> constant is used in a context that expects an expression of type
> unsigned long long (64 bits, un
Hello maintainers of ,
As discussed earlier in this thread, I propose this patch to stable.
It fixes the issue, which exists since v2.6.34.
Best Regards,
Kirill
On 02/12/18 09:08, Takashi Iwai wrote:
> On Thu, 08 Feb 2018 07:21:36 +0100,
> Kirill Marinushkin wrote:
>> On 02/07/18 06:45, Taka
L.S.,
The Debian kernel-package tool make-kpkg for easy building of upstream kernels
on Debian fails with linux 4.16-rc1.
The tool (perl script) while invoked with:
make-kpkg --initrd --append_to_version -20180212 kernel_image
On a git tree with a .config from the previous kernel release
From: Denys Vlasenko
Date: Mon, 12 Feb 2018 20:00:20 +0100
> Changes since v1:
> Added changes in these files:
> drivers/infiniband/hw/usnic/usnic_transport.c
> drivers/staging/lustre/lnet/lnet/lib-socket.c
> drivers/target/iscsi/iscsi_target_login.c
> drivers/vhost/net.c
> fs
Looks good.
Reviewed-by: Keith Busch
Thanks Keith, appiled to nvme-4.17
We want to check for xfers that are over 30 microseconds. Rather than
find how many µs a xfer will take, instead find how many bytes can be
transferred in 30 µs. The latter must be less than 32 bits (since our
clock speed is limited to 32 bits), while the former involves 64 bit
quantities and mor
On 02/12/2018 04:28 AM, Michael Ellerman wrote:
> Randy Dunlap writes:
>
>> From: Randy Dunlap
>>
>> Currently #includes for no obvious
>> reason. It looks like it's only a convenience, so remove kmemleak.h
>> from slab.h and add to any users of kmemleak_*
>> that don't already #include it.
>
On Mon, Feb 12, 2018 at 05:57:31PM +0300, Dan Carpenter wrote:
> On Mon, Feb 12, 2018 at 08:05:22PM +0530, Himanshu Jha wrote:
> > But these should be done when we have *more* instances.
> >
> > For eg:
> > I added a tab space in function static int adis16201_read_raw() argument
> > to match open
Hi,
On 12-02-18 00:36, Chanwoo Choi wrote:
On 2018년 02월 12일 08:26, Hans de Goede wrote:
Commit 41d600274fbf ("extcon: int3496: process id-pin first so that we
start with the right status") starts the work on the workqueue before
registration to make sure we've a valid cable state directly after
tree: https://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git x86/pti
head: 5a10e729bc0aa9420a23a70b169eadd229c27bc1
commit: f09d160992d129b6d8fada7543761d40f5b33596 [19/20] x86/entry/64: Get rid
of the ALLOC_PT_GPREGS_ON_STACK and SAVE_AND_CLEAR_REGS macros
config: x86_64-randconfig-ne0-0
Make the axp288_pwr_up_down_info array const char * const, this leads
to the following section size changes:
.text 0x674 -> 0x664
.data 0x148 -> 0x0f0
.rodata 0x0b4 -> 0x114
Signed-off-by: Hans de Goede
---
drivers/extcon/extcon-axp288.c | 4 ++--
1 file changed, 2 insertions(+), 2 de
Some other drivers may be waiting for our extcon to show-up (exiting their
probe methods with -EPROBE_DEFER until we show up).
These drivers will typically get the cable state directly after getting
the extcon, this commit changes the int3496 code to process the id-pin
before registering the extco
Redoing the charger type detection to give the usb-role-switch code time
to properly set the role-switch is no good for mainline, since the
usb-role-switch code is not yet in mainline (my bad, sorry).
Also once we've that code there are better ways to fix this which are
not prone to racing as doin
Macro-ify function save and restore. These will be used in new functions
added for scatter/gather update operations.
Signed-off-by: Dave Watson
---
arch/x86/crypto/aesni-intel_asm.S | 53 ++-
1 file changed, 24 insertions(+), 29 deletions(-)
diff --git a/arc
Use macro operations to merge implemetations of INITIAL_BLOCKS,
since they differ by only a small handful of lines.
Use macro counter \@ to simplify implementation.
Signed-off-by: Dave Watson
---
arch/x86/crypto/aesni-intel_asm.S | 298 ++
1 file changed, 48
Reduce code duplication by introducting GCM_INIT macro. This macro
will also be exposed as a function for implementing scatter/gather
support, since INIT only needs to be called once for the full
operation.
Signed-off-by: Dave Watson
---
arch/x86/crypto/aesni-intel_asm.S | 84 +++---
601 - 700 of 1074 matches
Mail list logo
