On Tue, Jan 09, 2018 at 07:04:04PM +, Suzuki K Poulose wrote:
> We allocate the entry level page tables for stage2 when the
> VM is created. This doesn't give us the flexibility of configuring
> the physical address space size for a VM. In order to allow
> the VM to choose the required size, we
Add g/s_parm framerate support by calling subdev
g/s_frame_interval ops.
This allows user to control sensor framerate by
calling ioctl G/S_PARM.
Signed-off-by: Hugues Fruchet
---
version 2:
- Rebase on Hans branch to use new helpers:
See https://www.mail-archive.com/linux-media@vger.kernel.
On Tue, Jan 09, 2018 at 07:04:02PM +, Suzuki K Poulose wrote:
> On a 4-level page table pgd entry can be empty, unlike a 3-level
> page table. Remove the spurious WARN_ON() in stage_get_pud().
Acked-by: Christoffer Dall
>
> Cc: Marc Zyngier
> Cc: Christoffer Dall
> Signed-off-by: Suzuki K
On Tue, Jan 09, 2018 at 07:04:00PM +, Suzuki K Poulose wrote:
> Add a helper to convert ID_AA64MMFR0_EL1:PARange to they physical
*the*
> size shift. Limit the size to the maximum supported by the kernel.
Is this just a cleanup or are we ac
On 2018-02-08 06:28, Kai-Heng Feng wrote:
> Without btcoex_enable, WiFi activies make both WiFi and Bluetooth
> unstable if there's a bluetooth connection.
>
> Enable this option when bt_ant_diversity is disabled.
>
> BugLink: https://bugs.launchpad.net/bugs/1746164
> Signed-off-by: Kai-Heng Feng
Thanks Hans,
v2 sent, rebased on your helpers !
Best regards,
Hugues.
On 02/07/2018 06:52 PM, Hans Verkuil wrote:
> On 02/07/2018 06:43 PM, Hugues Fruchet wrote:
>> Add g/s_parm framerate support by calling subdev
>> g/s_frame_interval ops.
>> This allows user to control sensor framerate by
>> cal
On Fri, Feb 02, 2018 at 06:05:09PM -0500, Steven Rostedt wrote:
> From: "Steven Rostedt (VMware)"
>
> Add a special type "symbol" that will use %pS to display the field of a
> function based event.
>
> Signed-off-by: Steven Rostedt (VMware)
> ---
> Documentation/trace/function-based-events.rst
On Wed, Feb 07, 2018 at 06:15:58PM +, Suzuki K Poulose wrote:
> On 07/02/18 10:38, Dave Martin wrote:
> >On Wed, Jan 31, 2018 at 06:27:57PM +, Suzuki K Poulose wrote:
> >>KPTI is treated as a system wide feature, where we enable the feature
> >>when all the CPUs on the system suffers from t
On 08/02/18 11:00, Christoffer Dall wrote:
On Tue, Jan 09, 2018 at 07:04:00PM +, Suzuki K Poulose wrote:
Add a helper to convert ID_AA64MMFR0_EL1:PARange to they physical
*the*
size shift. Limit the size to the maximum supported by the
On Tue, Jan 09, 2018 at 07:04:10PM +, Suzuki K Poulose wrote:
> Allow the guests to choose a larger physical address space size.
> The default and minimum size is 40bits. A guest can change this
> right after the VM creation, but before the stage2 entry page
> tables are allocated (i.e, before
Hi Suzuki,
On Tue, Jan 09, 2018 at 07:03:55PM +, Suzuki K Poulose wrote:
> On arm64 we have a static limit of 40bits of physical address space
> for the VM with KVM. This series lifts the limitation and allows the
> VM to configure the physical address space upto 52bit on systems
> where it is
On Wed, Feb 07, 2018 at 03:24:03PM -0500, Steven Rostedt wrote:
SNIP
> +
> +void create_function_event_file(struct dentry *d_tracer)
> +{
> + struct dentry *d;
> +
> + d = trace_create_file("function_events", 0644, d_tracer, NULL,
> + &func_event_fops);
> + W
On 07/02/18 15:10, Christoffer Dall wrote:
Hi Suzuki,
On Tue, Jan 09, 2018 at 07:03:57PM +, Suzuki K Poulose wrote:
Add helpers for encoding/decoding 52bit address in GICv3 ITS BASER
register. When ITS uses 64K page size, the 52bits of physical address
are encoded in BASER[47:12] as follows
On Wed, Feb 07, 2018 at 03:24:13PM -0500, Steven Rostedt wrote:
> From: "Steven Rostedt (VMware)"
>
> Add a special type "symbol" that will use %pS to display the field of a
> function based event.
>
> Signed-off-by: Steven Rostedt (VMware)
> ---
> Documentation/trace/function-based-events.rst
On Thu, Feb 08, 2018 at 11:08:18AM +, Suzuki K Poulose wrote:
> On 08/02/18 11:00, Christoffer Dall wrote:
> >On Tue, Jan 09, 2018 at 07:04:00PM +, Suzuki K Poulose wrote:
> >>Add a helper to convert ID_AA64MMFR0_EL1:PARange to they physical
> >
On (02/08/18 02:25), Minchan Kim wrote:
[..]
> > > if (PageTransHuge(page)) {
> > > - if (IS_ENABLED(CONFIG_THP_SWAP))
> > > - get_swap_pages(1, true, &entry);
> > > + /* Frontswap doesn't support THP */
> > > + if (!frontswap_enabled()) {
> > > +
I can comment on one part here:
On Thu, Feb 08, 2018 at 12:18:44PM +0100, Christoffer Dall wrote:
> Wasn't this also the decision taken for IOMMU page table allocation, and
> why was that the right approach for the IOMMU but not for KVM stage 2
> page tables? Is there room for reuse of the IOMMU
The num-interpolated-steps property specifies the number of
interpolated steps between each value of brightness-level table. This is
useful for high resolution PWMs to not have to list out every possible
value in the brightness-level array.
Signed-off-by: Enric Balletbo i Serra
Acked-by: Daniel T
When you want to change the brightness using a PWM signal, one thing you
need to consider is how human perceive the brightness. Human perceive
the brightness change non-linearly, we have better sensitivity at low
luminance than high luminance, so to achieve perceived linear dimming,
the brightness
Dear all,
This series is a third patchset integrating the requested changes.
The first and second patch what tries to solve is the problem of
granularity for high resolution PWMs. The idea is simple interpolate
between 2 brightness values so we can have a high PWM duty cycle (a
16 bits PWM is up
The patch 'backlight: pwm_bl: compute brightness of LED linearly to
human eye' introduced a default brightness-levels table that is used
when brightness-levels is not available in the dts. So move
brightness-levels and default-brightness-level to be optional.
Signed-off-by: Enric Balletbo i Serra
Setting num-interpolated-steps in the dts will allow you to have linear
interpolation between values of brightness-levels. This way a high
resolution pwm duty cycle can be used without having to list out every
possible value in the dts. This system also allows for gamma corrected
values.
The most
On Wed, Feb 07, 2018 at 06:34:37PM +, Suzuki K Poulose wrote:
> On 07/02/18 10:38, Dave Martin wrote:
> >On Wed, Jan 31, 2018 at 06:27:58PM +, Suzuki K Poulose wrote:
> >>The kernel detects and uses some of the features based on the boot
> >>CPU and expects that all the following CPUs confo
On 08/02/18 11:20, Suzuki K Poulose wrote:
On 07/02/18 15:10, Christoffer Dall wrote:
Hi Suzuki,
On Tue, Jan 09, 2018 at 07:03:57PM +, Suzuki K Poulose wrote:
Add helpers for encoding/decoding 52bit address in GICv3 ITS BASER
register. When ITS uses 64K page size, the 52bits of physical ad
On 08/02/18 11:35, Dave Martin wrote:
On Wed, Feb 07, 2018 at 06:34:37PM +, Suzuki K Poulose wrote:
On 07/02/18 10:38, Dave Martin wrote:
On Wed, Jan 31, 2018 at 06:27:58PM +, Suzuki K Poulose wrote:
* 3) Verification: When a CPU is brought online (e.g, by user or by the
kernel),
>From 361d37a7d36978020dfb4c11ec1f4800937ccb68 Mon Sep 17 00:00:00 2001
From: Tetsuo Handa
Date: Thu, 8 Feb 2018 10:35:35 +0900
Subject: [PATCH v2] lockdep: Fix fs_reclaim warning.
Dave Jones reported fs_reclaim lockdep warnings.
WARNING: possible
Hi,
On Thu, Dec 07, 2017 at 11:33:47AM +, Miodrag Dinic wrote:
> > On Wed, Dec 06, 2017 at 05:50:52PM +, Maciej W. Rozycki wrote:
> > > What problem are you trying to solve anyway? Is it not something that
> > > can be handled with the `execstack' utility?
> >
> > The commit message st
On 02/08/18 11:46, Philipp Zabel wrote:
> On Wed, 2018-02-07 at 23:19 +0100, Hans Verkuil wrote:
>> On 02/07/2018 11:05 PM, Tim Harvey wrote:
>>> On Wed, Feb 7, 2018 at 1:09 AM, Hans Verkuil wrote:
On 02/07/18 09:22, Hans Verkuil wrote:
> On 02/07/2018 12:29 AM, Tim Harvey wrote:
>> M
Some 32bits guest OS can use the CNTP timer, however KVM does not
handle the accesses, injecting a fault instead.
Use the proper handlers to emulate the EL1 Physical Timer (CNTP)
register accesses of AArch32 guests.
Signed-off-by: Jérémy Fanguède
Signed-off-by: Alvise Rigo
---
arch/arm64/kvm/s
On Thu, Feb 08, 2018 at 10:53:52AM +, Suzuki K Poulose wrote:
> On 07/02/18 10:39, Dave Martin wrote:
> >On Wed, Jan 31, 2018 at 06:28:03PM +, Suzuki K Poulose wrote:
> >>Some capabilities have different criteria for detection and associated
> >>actions based on the matching criteria, even
On 02/08/18 12:56, Hans Verkuil wrote:
> On 02/08/18 11:46, Philipp Zabel wrote:
>> On Wed, 2018-02-07 at 23:19 +0100, Hans Verkuil wrote:
>>> On 02/07/2018 11:05 PM, Tim Harvey wrote:
On Wed, Feb 7, 2018 at 1:09 AM, Hans Verkuil wrote:
> On 02/07/18 09:22, Hans Verkuil wrote:
>> On 0
On Wed, Jan 31, 2018 at 06:28:03PM +, Suzuki K Poulose wrote:
> Some capabilities have different criteria for detection and associated
> actions based on the matching criteria, even though they all share the
> same capability bit. So far we have used multiple entries with the same
> capability
On 02/08/2018 01:25 AM, Vladislav Valtchev wrote:
> On Wed, 2018-02-07 at 22:01 +0800, Zamir SUN wrote:
>>
>> While just a note for this, in Fedora 27:
>>
>> $ if command -v swig; then echo 1; else echo 0; fi
>> /usr/bin/swig
>> 1
>>
>> Actually this test has the same problem as of `which swig` -
On 08/02/18 12:04, Dave Martin wrote:
On Wed, Jan 31, 2018 at 06:28:03PM +, Suzuki K Poulose wrote:
Some capabilities have different criteria for detection and associated
actions based on the matching criteria, even though they all share the
same capability bit. So far we have used multiple
On 08/02/18 11:57, Jérémy Fanguède wrote:
> Some 32bits guest OS can use the CNTP timer, however KVM does not
> handle the accesses, injecting a fault instead.
>
> Use the proper handlers to emulate the EL1 Physical Timer (CNTP)
> register accesses of AArch32 guests.
>
> Signed-off-by: Jérémy Fan
- pbonz...@redhat.com wrote:
> On 08/02/2018 06:13, Chao Gao wrote:
> > Although L2 is in halt state, it will be in the active state after
> > VM entry if the VM entry is vectoring. Halting the vcpu here means
> > the event won't be injected to L2 and this decision isn't reported
> > to L1. T
On 07/02/18 10:38, Dave Martin wrote:
On Wed, Jan 31, 2018 at 06:27:55PM +, Suzuki K Poulose wrote:
So far we have had separate routes for triggering errata and feature
capability detection. Also, we never allowed "features" based on local
CPU and "errata" based on System wide safe registers
On Mon, 29 Jan 2018 14:11:35 +1000, Andrew Cooks wrote:
> On 29/12/17 19:44, Andy Shevchenko wrote:
> > On Tue, Dec 5, 2017 at 4:17 AM, Andrew Cooks
> > wrote:
> >> Using TCA6424A with i2c-piix4 bus driver requires byte-at-a-time IO,
> >> because the i2c-piix4 driver (and probably some SMBus co
So far we have restricted the scopes for the capabilities
as follows :
1) Errata workaround check are run all CPUs (i.e, always
SCOPE_LOCAL_CPU)
2) Arm64 features are run only once after the sanitised
feature registers are available using the SCOPE_SYSTEM.
This prevents detecting cpu fea
We can now handle each capability entry independent of whether
it is a feature or an errata workaround. This patch consolidates
the handling of the capabilities, by grouping them, to streamline
the code flow.
Cc: Dave Martin
Signed-off-by: Suzuki K Poulose
---
arch/arm64/kernel/cpufeature.c | 9
On 07/02/18 10:39, Dave Martin wrote:
On Wed, Jan 31, 2018 at 06:28:04PM +, Suzuki K Poulose wrote:
We defend against branch predictor training based exploits by
taking specific actions (based on the CPU model) to invalidate
the Branch predictor buffer (BPB). This is implemented by per-CPU
p
Hi Stephen,
On Thu, Feb 08, 2018 at 07:33:01AM +1100, Stephen Rothwell wrote:
> Hi all,
>
> Commit
>
> d8ed9600581d ("netfilter: remove useless prototype")
>
> is missing a Signed-off-by from its committer.
That's my fault, sorry about that, it was unintentional.
On Mon, Jan 15, 2018 at 12:47:32PM +0800, Wang YanQing wrote:
> So that beautifiers wanting to resolve kernel function addresses to
> names can do its work, and when we use "perf report" for output of
> "perf kmem record", we will get kernel symbol output.
>
> Signed-off-by: Wang YanQing
Acked-b
This is try to support SFC found on Rockchip RV1108 platform.
Thanks for Cyrille's review, this version trys to address all
his concern in V7 [0].
Feature:
(1) Support x1, x2, x4 data bits mode
(2) Support up to 4 chip select
(3) Support two independent clock domain: AHB clock and SPI clock
(4) S
From: Shawn Lin
Add Rockchip SFC(serial flash controller) driver.
Signed-off-by: Shawn Lin
Signed-off-by: Andy Yan
Acked-by: Marek Vasut
---
Changes in v8:
- remove unused macro SFC_CMD_TRAN_BYTES_MASK
- set max transfer length to 15.5KB
- remove unnecessary buffer align check
- remove the
From: Shawn Lin
Add binding document for the Rockchip serial flash controller.
Signed-off-by: Shawn Lin
Acked-by: Marek Vasut
Acked-by: Rob Herring
Signed-off-by: Andy Yan
---
Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3
Enable the sfc support for rv1108 evaluation board.
Signed-off-by: Andy Yan
---
Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/arm/boot/dts/rv1108-evb.dts | 10 ++
arch/arm/boot/dts/rv1108
On 08/02/18 12:19, Suzuki K Poulose wrote:
> On 07/02/18 10:39, Dave Martin wrote:
>> On Wed, Jan 31, 2018 at 06:28:04PM +, Suzuki K Poulose wrote:
>>> We defend against branch predictor training based exploits by
>>> taking specific actions (based on the CPU model) to invalidate
>>> the Branch
Horiguchi-san,
Naoya Horiguchi writes:
> Hi Punit,
>
> On Mon, Feb 05, 2018 at 03:05:43PM +, Punit Agrawal wrote:
>> Naoya Horiguchi writes:
>>
[...]
>> >
>> > You can easily reproduce this by calling madvise(MADV_HWPOISON) twice on
>> > a 1GB hugepage. This happens because get_user_page
On Thu, Feb 08, 2018 at 11:29:49AM +0100, Paolo Bonzini wrote:
>On 08/02/2018 06:13, Chao Gao wrote:
>> Although L2 is in halt state, it will be in the active state after
>> VM entry if the VM entry is vectoring. Halting the vcpu here means
>> the event won't be injected to L2 and this decision isn
On 08/02/18 12:01, Dave Martin wrote:
On Thu, Feb 08, 2018 at 10:53:52AM +, Suzuki K Poulose wrote:
On 07/02/18 10:39, Dave Martin wrote:
On Wed, Jan 31, 2018 at 06:28:03PM +, Suzuki K Poulose wrote:
Some capabilities have different criteria for detection and associated
actions based o
On Tue, Feb 06, 2018 at 09:38:09PM +0200, Andy Shevchenko wrote:
> On Mon, Feb 5, 2018 at 6:25 PM, Niklas Cassel wrote:
> > On Thu, Feb 01, 2018 at 02:00:40PM -0500, Jingoo Han wrote:
> >> On Thursday, February 1, 2018 1:58 PM, Andy Shevchenko wrote:
> >> >
> >> > On Thu, Feb 1, 2018 at 6:11 PM, N
pci_epc_set_bar() can be called with flag PCI_BASE_ADDRESS_MEM_TYPE_64,
and can thus request a BAR size larger than 4 GB.
However, the pcie-designware-ep.c driver currently doesn't handle
BAR sizes larger than 4 GB. (Since we are only writing the BAR_mask[x]
register and not the BAR_mask[x+1] regi
Signed-off-by: Yunlong Song
---
fs/f2fs/gc.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/fs/f2fs/gc.c b/fs/f2fs/gc.c
index b9d93fd..2095630 100644
--- a/fs/f2fs/gc.c
+++ b/fs/f2fs/gc.c
@@ -692,6 +692,7 @@ static void move_data_block(struct inode *inode, block_t
bidx,
fio.op = REQ
PCI endpoint fixes to improve the way 64-bit BARs are handled.
There are still future improvements that could be made:
pci-epf-test.c always allocates space for
6 BARs, even when using 64-bit BARs (which
really only requires us to allocate 3 BARs).
pcitest.sh will print "NOT OKAY" for BAR1,
BAR
A 64-bit BAR uses the succeeding BAR for the upper bits, therefore
we cannot call pci_epc_set_bar() on a BAR that follows a 64-bit BAR.
If pci_epc_set_bar() is called with flag PCI_BASE_ADDRESS_MEM_TYPE_64,
it has to be up to the controller driver to write both BAR[x] and BAR[x+1]
(and BAR_mask[x]
A 64-bit BAR uses the succeeding BAR for the upper bits,
so we cannot simply call pci_ioremap_bar() on every single BAR.
Ignore BARs that does not have a valid resource length.
pci :01:00.0: BAR 4: assigned [mem 0xc030-0xc031 64bit]
pci :01:00.0: BAR 2: assigned [mem 0xc032-0x
On 02/07/18 at 01:48pm, Eric W. Biederman wrote:
> ebied...@xmission.com (Eric W. Biederman) writes:
> > Now that I see that I agree in essence with this patch series.
> > I don't agree with the implemenation details.
> >
> > Can you please split disable_IO_APIC and switch_to_legacy_irq_mode
> > i
> On 8. Feb 2018, at 13:17, David Woodhouse wrote:
>
>
> From: David Woodhouse
> Subject: [RFC PATCH 2/4] KVM: x86: Reduce retpoline performance impact in
> slot_handle_level_range()
> Date: 7. February 2018 at 01:03:12 GMT+1
> To: t...@linutronix.de, torva...@linux-foundation.org, x...@kerne
On Wed, 2018-02-07 at 20:46 +0100, Yves-Alexis Perez wrote:
> Maybe. I tried with removing the MTU setting, and I get (on ping again)
>
> févr. 07 20:44:01 scapa kernel: mtu: 1266
>
> which means I would get -EINVAL on standards kernels, which is not really good
> either.
Actually after rebootin
On Tue, Feb 06, 2018 at 09:26:15PM +, Winkler, Tomas wrote:
> >
> > On Sun, Jan 28, 2018 at 09:17:53PM +, Winkler, Tomas wrote:
> > >
> > > >
> > > > On Sun, Jan 28, 2018 at 09:51:00AM +0200, Tomas Winkler wrote:
> > > >
> > > > > diff --git a/include/linux/tpm.h b/include/linux/tpm.h inde
>
> On Tue, Feb 06, 2018 at 09:26:15PM +, Winkler, Tomas wrote:
> > >
> > > On Sun, Jan 28, 2018 at 09:17:53PM +, Winkler, Tomas wrote:
> > > >
> > > > >
> > > > > On Sun, Jan 28, 2018 at 09:51:00AM +0200, Tomas Winkler wrote:
> > > > >
> > > > > > diff --git a/include/linux/tpm.h b/inclu
On 02/06/2018 07:23 PM, Vincent Guittot wrote:
> [...]
> @@ -7826,8 +7842,8 @@ static inline void update_sg_lb_stats(struct lb_env
> *env,
> for_each_cpu_and(i, sched_group_span(group), env->cpus) {
> struct rq *rq = cpu_rq(i);
>
> - if (env->flags & LBF_NOHZ_STAT
Hi,
On Thursday 08 February 2018 06:03 PM, Niklas Cassel wrote:
> A 64-bit BAR uses the succeeding BAR for the upper bits, therefore
> we cannot call pci_epc_set_bar() on a BAR that follows a 64-bit BAR.
>
> If pci_epc_set_bar() is called with flag PCI_BASE_ADDRESS_MEM_TYPE_64,
Not related to $p
Currently, data in RX FIFO is read based on UART_LSR register state even
if RDI and RLSI interrupts are disabled in UART_IER register.
This is because when IRQ handler is called due to TX FIFO empty event,
RX FIFO is serviced based on UART_LSR register status instead of
UART_IIR status. This defeat
AMD SME claims one bit from physical address to indicate whether the
page is encrypted or not. To achieve that we clear out the bit from
__PHYSICAL_MASK.
The capability to adjust __PHYSICAL_MASK is required beyond AMD SME.
For instance for upcoming Intel Multi-Key Total Memory Encryption.
Let's f
omap_8250_throttle() is called when tty RX buffer is about to overflow
and can no longer keep up with the rate at which UART is receiving data.
So, the expectation of this callback, is that UART stops RX and asserts
HW flow control to signal the sender to stop sending more data.
omap_8250_throttle(
This series contains couple of fixes related to throttling of 8250 uart
port when tty buffer is under pressure.
Vignesh R (2):
serial: 8250: Don't service RX FIFO if interrupts are disabled
serial: 8250: 8250_omap: Fix throttling when DMA is enabled
drivers/tty/serial/8250/8250_omap.c | 11
On Thursday 08 February 2018 03:24 PM, Bartosz Golaszewski wrote:
> 2018-02-08 10:30 GMT+01:00 Sekhar Nori :
>> On Wednesday 07 February 2018 07:15 PM, Bartosz Golaszewski wrote:
>>> + /*
>>> + * DaVinci always uses a single clock for power-management. We assume
>>> + * it's the first
Linus reported that GCC-7.3 generated a switch-table construct that
confused objtool. It turns out that, in particular due to KASAN, it is
possible to have unrelated .rodata usage in between the .rodata setup
for the switch-table and the following indirect jump.
The simple linear reverse search f
From: Tejun Heo
We mark for waking up klogd whenever we see a new message sequence in
the main loop. However, the actual wakeup is always at the end of the
function and we can easily test for the wakeup condition when we do
the final should-we-repeat check.
Move the wake_klogd condition check o
On Thu, Feb 08, 2018 at 02:29:57PM +0800, Kai Heng Feng wrote:
> A user with i386 instead of AMD64 machine reports [1] that commit
> 19809c2da28a ("mm, vmalloc: use __GFP_HIGHMEM implicitly”) causes a
> regression.
> BUG_ON(PageHighMem(pg)) in drivers/media/common/saa7146/saa7146_core.c always
>
By following best practice described in
Documentation/watchdog/watchdog-kernel-api.txt, it also let us to set
timout-sec property in devicetree.
Signed-off-by: Marcus Folkesson
---
Documentation/devicetree/bindings/watchdog/fsl-imx-wdt.txt | 2 ++
drivers/watchdog/imx2_wdt.c
Hi,
[ dri-devel ML & arch/[score,um] Maintainers added to Cc: ]
On Friday, February 02, 2018 08:59:57 AM Christian Borntraeger wrote:
> On 02/01/2018 07:41 PM, Farhan Ali wrote:
> > The 'commit e25df1205f37 ("[S390] Kconfig: menus with depends on
> > HAS_IOMEM.")'
> > added the HAS_IOMEM depend
Hi Philippe,
On Saturday, 3 February 2018 00:41:26 EET Philippe CORNU wrote:
> On 01/29/2018 11:40 AM, Laurent Pinchart wrote:
> > On Monday, 29 January 2018 12:17:37 EET Philippe CORNU wrote:
> >> On 01/29/2018 10:46 AM, Laurent Pinchart wrote:
> >>> On Thursday, 25 January 2018 17:55:04 EET Phil
On Thu, Feb 08, 2018 at 12:46:53PM +, Valentin Schneider wrote:
> On 02/06/2018 07:23 PM, Vincent Guittot wrote:
> > [...]
> > @@ -7826,8 +7842,8 @@ static inline void update_sg_lb_stats(struct lb_env
> > *env,
> > for_each_cpu_and(i, sched_group_span(group), env->cpus) {
> > s
On Thu, Feb 08, 2018 at 04:09:36AM -0800, Liran Alon wrote:
>
>- pbonz...@redhat.com wrote:
>
>> On 08/02/2018 06:13, Chao Gao wrote:
>> > Although L2 is in halt state, it will be in the active state after
>> > VM entry if the VM entry is vectoring. Halting the vcpu here means
>> > the event wo
On 6 January 2018 at 11:51, Li Wei wrote:
> add Hisilicon ufs driver code.
>
> Signed-off-by: Li Wei
> Signed-off-by: Geng Jianfeng
> Signed-off-by: Zang Leigang
> Signed-off-by: Yu Jianfeng
Tested this on 4.15 on Hikey 960. Works, but notice the inline comment
below about
MODULE_DEVICE_TABLE
This checks for a comparison using < or > between two constants,
considering both explicit constants (1, 2, etc) and macros defined
with #define. False positives are possible in the latter case, when
a macro may have multiple possible definitions and it is indeed
necessary to check the value. The
On Thu, Feb 8, 2018 at 10:54 AM, Xin Long wrote:
> On Thu, Feb 8, 2018 at 6:58 AM, syzbot
> wrote:
>> Hello,
>>
>> syzbot hit the following crash on upstream commit
>> a2e5790d841658485d642196dbb0927303d6c22f (Wed Feb 7 06:15:42 2018 +)
>> Merge branch 'akpm' (patches from Andrew)
>>
>> So fa
2018-02-08 13:56 GMT+01:00 Sekhar Nori :
> On Thursday 08 February 2018 03:24 PM, Bartosz Golaszewski wrote:
>> 2018-02-08 10:30 GMT+01:00 Sekhar Nori :
>>> On Wednesday 07 February 2018 07:15 PM, Bartosz Golaszewski wrote:
+ /*
+ * DaVinci always uses a single clock for power-ma
On Wednesday, January 31, 2018 08:51:23 PM Mathieu Malaterre wrote:
> Bartlomiej,
>
> On Wed, Jan 31, 2018 at 12:57 PM, Bartlomiej Zolnierkiewicz
> wrote:
> > On Tuesday, January 30, 2018 02:14:10 PM Mathieu Malaterre wrote:
> >> Bartlomiej,
> >>
> >> On Wed, Jan 3, 2018 at 3:47 PM, Bartlomiej Zo
On Thu, Feb 8, 2018 at 10:28 AM, Jan Kara wrote:
> On Wed 07-02-18 07:52:29, Andi Kleen wrote:
>> > #0: (&bdev->bd_mutex){+.+.}, at: [<40269370>]
>> > __blkdev_put+0xbc/0x7f0 fs/block_dev.c:1757
>> > 1 lock held by blkid/19199:
>> > #0: (&bdev->bd_mutex){+.+.}, at: []
> On 5 Feb 2018, at 13.15, Matias Bjørling wrote:
>
> Implement the geometry data structures for 2.0 and enable a drive
> to be identified as one, including exposing the appropriate 2.0
> sysfs entries.
>
> Signed-off-by: Matias Bjørling
> ---
> drivers/lightnvm/core.c | 2 +-
> drivers/n
On 8 February 2018 at 13:46, Valentin Schneider
wrote:
> On 02/06/2018 07:23 PM, Vincent Guittot wrote:
>> [...]
>> @@ -7826,8 +7842,8 @@ static inline void update_sg_lb_stats(struct lb_env
>> *env,
>> for_each_cpu_and(i, sched_group_span(group), env->cpus) {
>> struct rq *rq
On 2018/2/8 18:20, Rafael J. Wysocki wrote:
On Thursday, February 8, 2018 11:13:10 AM CET Chris Wilson wrote:
Quoting Rafael J. Wysocki (2018-02-08 09:51:41)
On Thursday, January 25, 2018 11:13:41 AM CET Jia-Ju Bai wrote:
After checking all possible call chains to acpi_os_execute here,
my to
stm32_vrefbuf_enable() wrongly checks VRR bit: 0 stands for not ready,
1 for ready. It currently checks the opposite.
This makes enable routine to exit immediately without waiting for ready
flag.
Fixes: 0cdbf481e927 ("regulator: Add support for stm32-vrefbuf")
Signed-off-by: Fabrice Gasnier
---
On Thu, Feb 08, 2018 at 11:20:02AM +, Suzuki K Poulose wrote:
> On 07/02/18 15:10, Christoffer Dall wrote:
> >Hi Suzuki,
> >
> >On Tue, Jan 09, 2018 at 07:03:57PM +, Suzuki K Poulose wrote:
> >>Add helpers for encoding/decoding 52bit address in GICv3 ITS BASER
> >>register. When ITS uses 64
On Wed, Feb 07, 2018 at 06:36:47PM -0800, Derek Basehore wrote:
> This adds documentation for the new reset-on-suspend property. This
> property enables saving and restoring the ITS for when it loses state
> in system suspend.
>
> Signed-off-by: Derek Basehore
> ---
> Documentation/devicetree/bi
Hi Krzysztof,
On 2018-01-30 22:18, Krzysztof Kozlowski wrote:
Hi,
Changes since v1:
1. New patch (1/4) calling devm_of_platform_populate() in PMU driver,
following Rob's advice.
2. The DTS patches moving reboot/poweroff nodes (3/4 and 4/4) now depend
on this.
Tested-by: Marek Szyprows
On Thu, Feb 08, 2018 at 09:46:53AM +0100, Pavel Machek wrote:
> On Tue 2018-01-09 16:27:30, Jarkko Sakkinen wrote:
> > On Thu, Jan 04, 2018 at 03:17:24PM +0100, Cedric Blancher wrote:
> > > So how does this protect against the MELTDOWN attack (CVE-2017-5754)
> > > and the MELTATOMBOMBA4 worm which
Since schedutil kernel thread directly set priority to 0, the macro
SUGOV_KTHREAD_PRIORITY is not used. So remove it.
Cc: Vikram Mulukutla
Cc: Vincent Guittot
Cc: Daniel Lezcano
Signed-off-by: Leo Yan
---
kernel/sched/cpufreq_schedutil.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/k
Hi Alex,
On 07/02/18 17:57, Alex Williamson wrote:
> On Wed, 7 Feb 2018 16:46:19 +0100
> Auger Eric wrote:
>
>> Hi Alex,
>>
>> On 07/02/18 01:08, Alex Williamson wrote:
>>> The ioeventfd here is actually irqfd handling of an ioeventfd such as
>>> supported in KVM. A user is able to pre-program
> What about Pentium II and 3? I'm using 5 such machines (and also a Pentium
> MMX). I've tried a spectre test before and it wasn't reading anything useful.
> Don't know about meltdown. Is there a complete test program? (The web is so
> full of crap that even google can't find anything useful.)
On 08/02/2018 13:09, Liran Alon wrote:
> - pbonz...@redhat.com wrote:
>> On 08/02/2018 06:13, Chao Gao wrote:
>>> Because virtual interrupt delivery may wake L2 vcpu, if VID is
>>> enabled, do the same thing -- don't halt L2.
>>
>> This second part seems wrong to me, or at least overly general.
On Wed, Feb 07, 2018 at 01:45:00AM +0800, John Garry wrote:
SNIP
> +static void fixup_field(char *from, char **to)
> +{
> + *to = malloc(strlen(from));
> +
> + strcpy(*to, from);
> +}
> +
> +#define EVENT_PREFIX "event="
> +
> +#define TRY_FIXUP_FIELD(string) do { if (es->string && !
On Wed, Feb 07, 2018 at 01:45:00AM +0800, John Garry wrote:
SNIP
> @@ -366,6 +367,67 @@ static int print_events_table_entry(void *data, char
> *name, char *event,
> return 0;
> }
>
> +struct event_struct {
> + char *name;
> + char *event;
> + char *desc;
> + char *long_d
On Wed, Feb 07, 2018 at 01:45:00AM +0800, John Garry wrote:
SNIP
> static void print_events_table_suffix(FILE *outfp)
> {
> fprintf(outfp, "{\n");
> @@ -407,6 +469,52 @@ static char *real_event(const char *name, char *event)
> return event;
> }
>
> +static void fixup_field(char *
On Wed, Feb 07, 2018 at 01:45:00AM +0800, John Garry wrote:
SNIP
> @@ -940,6 +1090,7 @@ int main(int argc, char *argv[])
> const char *output_file;
> const char *start_dirname;
> struct stat stbuf;
> + struct event_struct *es1, *es2;
>
> prog = basename(argv[0]);
>
On Wed, Feb 07, 2018 at 01:45:00AM +0800, John Garry wrote:
SNIP
> + rc = nftw(ldirname, preprocess_arch_std_files, get_maxfds(), 0);
> + if (rc && verbose) {
> + pr_info("%s: Error preprocessing arch standard files %s\n",
> + prog, ldirname);
> +
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