On 01/31/2018 10:46 AM, Tomasz Figa wrote:
> On Wed, Jan 31, 2018 at 5:47 PM, Hans Verkuil wrote:
>> On 01/31/2018 09:10 AM, Tomasz Figa wrote:
>>> Hi Hans,
>>>
>>> Sorry for joining the party late.
>>>
>>> On Wed, Jan 31, 2018 at 4:50 PM, Hans Verkuil wrote:
On 01/30/2018 07:31 AM, Alexandr
On Wed, Jan 31, 2018 at 09:53:10AM +0100, Dmitry Vyukov wrote:
> On Wed, Jan 31, 2018 at 8:28 AM, Ingo Molnar wrote:
> > * Will Deacon wrote:
> >> e.g. for atomic[64]_read, your asm-generic header looks like:
> >>
> >> #ifndef _LINUX_ATOMIC_INSTRUMENTED_H
> >> #define _LINUX_ATOMIC_INSTRUMENTED_H
Current dpc driver acknowledge the interrupt in deferred work, which works
okay since LPI are edge triggered.
But when RP does not have MSI support, port service driver falls back to
legacy GIC SPI interrupts, and with current code we do not acknowledge the
interrupt and we get dpc interrupt storm.
On Thu, 25 Jan 2018, Petr Mladek wrote:
> From: Jason Baron
>
> We are going to add a feature called atomic replace. It will allow to
> create a patch that would replace all already registered patches.
>
> The replaced patches will stay registered because they are typically
> unregistered by so
Linus,
Please pull the siginfo-linus branch from the git tree:
git://git.kernel.org/pub/scm/linux/kernel/git/ebiederm/user-namespace.git
siginfo-linus
HEAD: f20239c0d2d720d7deb8a40fd05c31849ddc8293 mm/memory_failure: update
powerpc for memory_failure() API change
I had a brain fart whe
Hi Daniel,
On Wed, Jan 31, 2018 at 10:57 AM, Daniel Baluta wrote:
> AK5558 is a 32-bit, 768 kHZ sampling, differential input ADC
> for digital audio systems.
>
> Datasheet is available at:
>
> https://www.akm.com/akm/en/file/datasheet/AK5558VN.pdf
>
> Initial patch includes support for normal and
On Wed, Jan 31, 2018 at 10:30:44AM -0500, David Miller wrote:
> From: Christian Brauner
> Date: Mon, 29 Jan 2018 18:07:20 +0100
>
> > - Backwards Compatibility:
> > If userspace wants to determine whether RTM_NEWLINK supports the
> > IFLA_IF_NETNSID property they should first send an RTM_GETL
Now that we have serial[1], pinctrl[2] and clock[3]
drivers for SDM845 SoC out on the lists, heres the
basic dts files needed to boot a SDM845 based MTP
board to a ramfs based serial console shell.
[1] https://patchwork.ozlabs.org/cover/860251/
[2] https://patchwork.kernel.org/patch/10157143/
[3]
Add the qup uart node and geni se instance needed to
support the serial console on the MTP.
Signed-off-by: Rajendra Nayak
---
arch/arm64/boot/dts/qcom/sdm845-mtp.dts | 42 +
arch/arm64/boot/dts/qcom/sdm845.dtsi| 21 +
2 files changed, 63 insert
Add a skeletal sdm845 SoC dtsi and MTP board dts/dtsi files
Signed-off-by: Rajendra Nayak
---
arch/arm64/boot/dts/qcom/Makefile | 1 +
arch/arm64/boot/dts/qcom/sdm845-mtp.dts | 13 ++
arch/arm64/boot/dts/qcom/sdm845.dtsi| 277
3 files changed, 291 in
Document the compatible string for the Kryo385 cpus found in qualcomm
SoCs.
Signed-off-by: Rajendra Nayak
---
Documentation/devicetree/bindings/arm/cpus.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/arm/cpus.txt
b/Documentation/devicetree/bindings/arm
On Wed, Jan 31, 2018 at 09:48:55PM +0530, Oza Pawandeep wrote:
> Current dpc driver acknowledge the interrupt in deferred work, which works
> okay since LPI are edge triggered.
> But when RP does not have MSI support, port service driver falls back to
> legacy GIC SPI interrupts, and with current c
On Tue, Jan 30 2018 at 18:11 +, Marc Zyngier wrote:
On 30/01/18 17:56, Lina Iyer wrote:
Hi Mark,
On Wed, Jan 24 2018 at 14:20 +, Marc Zyngier wrote:
Hi Lina, Archana,
On 23/01/18 17:56, Lina Iyer wrote:
From : Archana Sathyakumar
The Power Domain Controller (PDC) hardware block on
On Wed, Jan 31, 2018 at 12:44:41PM -0200, Eduardo Habkost wrote:
> Also, if anybody don't like it, users can already specify, e.g.,
> "Broadwell,-hle,-rtm" or "Skylake,+spec_ctrl".
>
> QEMU only adds have the -noTSX and -IBRS CPU for convenience of
> management systems that don't know how to check
From: Borislav Petkov
So this does not fix an existing problem but a hypothetical one. The
below fires on an old Frankenstein distro kernel and I'm sending it
only because it is obviously The Right Thing(tm). And in case we change
things in the vdso in the future and thus manage to generate an in
The AK4458 is a 32-bit 8ch Premium DAC that corresponds
to a 768kHz PCM input and an 11.2MHz DSD input at maximum.
It supports I2S, DSD and TDM modes with 24 or 32 bit MSB
or 16, 24, 32 LSB formats. Its datasheet is available here:
https://www.akm.com/akm/en/file/datasheet/AK4458VN.pdf
Signed-off-
On Wed, Jan 31, 2018 at 8:33 AM, Borislav Petkov wrote:
> From: Borislav Petkov
>
> So this does not fix an existing problem but a hypothetical one. The
> below fires on an old Frankenstein distro kernel and I'm sending it
> only because it is obviously The Right Thing(tm). And in case we change
On 31/01/18 16:24, Lina Iyer wrote:
> On Tue, Jan 30 2018 at 18:11 +, Marc Zyngier wrote:
>> On 30/01/18 17:56, Lina Iyer wrote:
>>> Hi Mark,
>>>
>>> On Wed, Jan 24 2018 at 14:20 +, Marc Zyngier wrote:
Hi Lina, Archana,
On 23/01/18 17:56, Lina Iyer wrote:
> From : Archana
> -Original Message-
> From: Pali Rohár [mailto:pali.ro...@gmail.com]
> Sent: Wednesday, January 31, 2018 3:08 AM
> To: Andy Shevchenko
> Cc: Limonciello, Mario ; Darren Hart
> ; LKML ; Platform Driver
>
> Subject: Re: [PATCH] platform/x86: dell-laptop: Allocate buffer on heap
> rather t
Hey Linus,
Here is the PULL request for v4.16-rc1. This time is smallish update with
updates mainly to drivers.
The following changes since commit 2610acf46b9ed528ec2cacd717bc9d354e452b73:
dmaengine: fsl-edma: disable clks on all error paths (2017-12-15 09:53:04
+0530)
are available in the g
On Mon, Jan 29, 2018 at 5:09 AM, Rafael J. Wysocki wrote:
> On Fri, Jan 26, 2018 at 10:48 AM, Andy Shevchenko
> wrote:
>> On Fri, Jan 19, 2018 at 10:58 AM, Rajneesh Bhardwaj
>> wrote:
>>> From: Srinivas Pandruvada
>>>
>>> Export lpit_read_residency_count_address(), so that it can be used from
>
On Wed, Jan 31, 2018 at 4:29 AM, Jeff Layton wrote:
>
> Do you mind just taking it directly? I don't have anything else queued
> up for this cycle.
Done.
I wonder if "false for same, true for different" calling convention
makes much sense, but it matches the old "0 for same" so obviously
makes f
On Wed, Jan 31, 2018 at 12:49 AM, Eric Biggers wrote:
>
> If devpts_ptmx_path() returns an error code, then devpts_mntget()
> dereferences an ERR_PTR():
Thanks, applied.
Linus
Fix function name prefix for naming consistency.
Signed-off-by: olivier moysan
---
sound/soc/stm/stm32_spdifrx.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/sound/soc/stm/stm32_spdifrx.c b/sound/soc/stm/stm32_spdifrx.c
index b9bdefc..42ad2ae 100644
--- a/sound/soc/s
This patchset changes spdifrx dai name and fixes a typo issue.
Olivier Moysan (2):
ASoC: stm32: spdifrx: fix typo in function name.
ASoC: stm32: spdifrx: Use default dai name
sound/soc/stm/stm32_spdifrx.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
--
1.9.1
Use dai name provided by framework from dev_name() function.
Signed-off-by: olivier moysan
---
sound/soc/stm/stm32_spdifrx.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/sound/soc/stm/stm32_spdifrx.c b/sound/soc/stm/stm32_spdifrx.c
index 42ad2ae..373df4f 100644
--- a/sound/soc/stm/stm32_sp
On Wed, Jan 31, 2018 at 5:10 AM, KarimAllah Ahmed wrote:
> + vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap,
> MSR_IA32_PRED_CMD,
> + MSR_TYPE_W);
Why not disable this intercept eagerly, rather than lazily? Unlike
MSR_IA32_SPEC_CTR
On 01/30/2018 09:50 PM, Eric Leblond wrote:
> Hello Daniel,
>
> No problem with the delay in the answer. I'm doing far worse.
>
> Here is an updated version:
> - add if_link.h in uapi and remove the definition
> - fix a commit message
> - remove uapi from a include
Fyi, this still needs to wait
On Wed, Jan 31, 2018 at 6:46 PM, wrote:
>> > for allocation: ..._alloc_request()
>> > for filling: _fill_request() / _prepare_request()
>> >
>> > or alike.
>> >
>> > _set_arguments() not good enough to me.
>>
>> Ok. Then we need to stick with 5 arguments... What about name
>> dell_fill_request()
Hi,
On Wed, Jan 31, 2018 at 7:16 AM, Sean Paul wrote:
> On Wed, Jan 31, 2018 at 7:54 AM, Lucas Stach wrote:
>> Am Dienstag, den 30.01.2018, 21:29 +0100 schrieb Thierry Escande:
>>> From: Sean Paul
>>>
>>> Change the mode for Sharp lq123p1jx31 panel to something more
>>> rockchip-friendly such
On Wed, Jan 31, 2018 at 8:20 AM, Rajneesh Bhardwaj
wrote:
> Recently sent patch 'platform/x86: intel_pmc_core: Remove unused EXPORTED
> API' missed to remove the header file 'arch/x86/include/asm/pmc_core.h'
> which was solely used to declare the EXPORTED API
> 'intel_pmc_slp_s0_counter_read'. Thi
On 31/01/2018 11:50, Jim Mattson wrote:
>> + if (to_vmx(vcpu)->save_spec_ctrl_on_exit) {
>> + nested_vmx_disable_intercept_for_msr(
>> + msr_bitmap_l1, msr_bitmap_l0,
>> + MSR_IA32_PRED_CMD,
>> +
On Wed, Jan 31, 2018 at 6:20 PM, Fabio Estevam wrote:
> Hi Daniel,
Fabio, +1 to your review. It seems it repeats some of the points I made.
>> + ak5558->pdn_gpio = of_get_named_gpio(np, "ak5558,pdn-gpio", 0);
>
> It does not match the property in the binding doc: asahi-kasei,pdn-gpios
Bt
On Wed, Jan 31, 2018 at 03:20:09PM +0200, Cosmin-Gabriel Samoila wrote:
This looks pretty good overall, I've got some issues below but nothing
too major:
> +static int ak4458_i2c_remove(struct i2c_client *i2c)
> +{
> + ak4458_remove(&i2c->dev);
> + pm_runtime_disable(&i2c->dev);
It's wei
On Wed, Jan 31, 2018 at 08:35:30AM -0800, Andy Lutomirski wrote:
> Hmm. I'm okay with this, but I'd also be okay doing nothing and
> figuring out WTF happened if an upstream kernel fails to build like
> this.
Oh sure, I'm sending it only as an FYI to show that something like this
*might* happen s
On Wednesday 31 January 2018 18:53:19 Andy Shevchenko wrote:
> On Wed, Jan 31, 2018 at 6:46 PM, wrote:
>
> >> > for allocation: ..._alloc_request()
> >> > for filling: _fill_request() / _prepare_request()
> >> >
> >> > or alike.
> >> >
> >> > _set_arguments() not good enough to me.
> >>
> >> Ok.
On Wed, Jan 31, 2018 at 02:20:31PM -0200, Fabio Estevam wrote:
> On Wed, Jan 31, 2018 at 10:57 AM, Daniel Baluta wrote:
> > + dev_err(&i2c->dev, "%s(%d)\n", __func__, __LINE__);
> You certainly do not want an error message on every probe :-)
Sometimes you've just got to be honest with peo
On 01/31/2018 05:50 PM, Jim Mattson wrote:
On Wed, Jan 31, 2018 at 5:10 AM, KarimAllah Ahmed wrote:
+ vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap,
MSR_IA32_PRED_CMD,
+ MSR_TYPE_W);
Why not disable this intercept eagerly, rat
From: Ladi Prosek
The assist page has been used only for the paravirtual EOI so far, hence
the "APIC" in the MSR name. Renaming to match the Hyper-V TLFS where it's
called "Virtual VP Assist MSR".
Signed-off-by: Ladi Prosek
Signed-off-by: Vitaly Kuznetsov
---
arch/x86/include/uapi/asm/hyperv.
Virtual Processor Assist Pages usage allows us to do optimized EOI
processing for APIC, enable Enlightened VMCS support in KVM and more.
struct hv_vp_assist_page is defined according to the Hyper-V TLFS v5.0b.
Signed-off-by: Vitaly Kuznetsov
---
arch/x86/hyperv/hv_init.c | 33 ++
L1 might want to use SECONDARY_EXEC_DESC, so we must not clear the VMCS
bit if UMIP is not being emulated.
We must still set the bit when emulating UMIP as the feature can be
passed to L2 where L0 will do the emulation and because L2 can change
CR4 without a VM exit, we should clear the bit if UMI
The definitions are according to the Hyper-V TLFS v5.0. KVM on Hyper-V will
use these.
Signed-off-by: Vitaly Kuznetsov
---
arch/x86/include/uapi/asm/hyperv.h | 203 +
1 file changed, 203 insertions(+)
diff --git a/arch/x86/include/uapi/asm/hyperv.h
b/arch/x8
Enlightened VMCS is just a structure in memory, the main benefit
besides avoiding somewhat slower VMREAD/VMWRITE is using clean field
mask: we tell the underlying hypervisor which fields were modified
since VMEXIT so there's no need to inspect them all.
Tight CPUID loop test shows significant spee
TLFS 5.0 says: "Support for an enlightened VMCS interface is reported with
CPUID leaf 0x4004. If an enlightened VMCS interface is supported,
additional nested enlightenments may be discovered by reading the CPUID
leaf 0x400A (see 2.4.11)."
Signed-off-by: Vitaly Kuznetsov
---
arch/x86/in
When running nested KVM on Hyper-V it's possible to use so called
'Enlightened VMCS' and do normal memory reads/writes instead of
doing VMWRITE/VMREAD instructions. In addition, clean field mask
provides a huge room for optimization on L0's side.
Tight CPUID loop test shows significant speedup (cu
On Wed, Jan 31, 2018 at 7:06 PM, Pali Rohár wrote:
> On Wednesday 31 January 2018 18:53:19 Andy Shevchenko wrote:
>> On Wed, Jan 31, 2018 at 6:46 PM, wrote:
>> >> Ok. Then we need to stick with 5 arguments... What about name
>> >> dell_fill_request()? E.g.
>> > + struct calling_interface
On 31/01/2018 12:11, KarimAllah Ahmed wrote:
> On 01/31/2018 05:50 PM, Jim Mattson wrote:
>> On Wed, Jan 31, 2018 at 5:10 AM, KarimAllah Ahmed
>> wrote:
>>
>>> + vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap,
>>> MSR_IA32_PRED_CMD,
>>> +
On 31/01/2018 12:12, Radim Krčmář wrote:
> L1 might want to use SECONDARY_EXEC_DESC, so we must not clear the VMCS
> bit if UMIP is not being emulated.
>
> We must still set the bit when emulating UMIP as the feature can be
> passed to L2 where L0 will do the emulation and because L2 can change
>
On 01/31/2018 05:55 PM, Paolo Bonzini wrote:
On 31/01/2018 11:50, Jim Mattson wrote:
+ if (to_vmx(vcpu)->save_spec_ctrl_on_exit) {
+ nested_vmx_disable_intercept_for_msr(
+ msr_bitmap_l1, msr_bitmap_l0,
+ MSR_IA32_PR
#syz test: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
master
From e7d73362ed378499795f27e2da6184d0b242b89c Mon Sep 17 00:00:00 2001
From: Joel Fernandes
Date: Wed, 24 Jan 2018 09:47:23 -0800
Subject: [PATCH] ashmem: Fix lockdep issue during llseek
ashmem_mutex create a chain
I had a few cases of mount getting stuck in an infinite loop.
This happens when bdev->bd_inode->i_blkbits gets modified (for
example by bd_set_size()) while *_fill_super() is between
sb_min_blocksize() and sb_bread(), and the new value is inconsistent
with the block size used in fill_super().
When
> I removed the blank line at EOF,
> then applied to linux-kbuild/misc.
I have taken another look at this script for the semantic patch language.
I imagined that I could refactor the shown SmPL disjunctions a bit.
But I noticed then that these SmPL rules contain a development mistake.
The deletio
On Wed, Jan 31, 2018 at 4:43 PM, David Miller wrote:
> From: Masahiro Yamada
> Date: Thu, 1 Feb 2018 00:37:27 +0900
>
>> 2018-02-01 0:32 GMT+09:00 David Miller :
>>> From: Ulf Magnusson
>>> Date: Tue, 30 Jan 2018 20:05:23 +0100
>>>
In preparation for adding a warning ("kconfig: Warn if help
Looking at SVM now...
On 31/01/2018 08:10, KarimAllah Ahmed wrote:
> diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c
> index f40d0da..89495cf 100644
> --- a/arch/x86/kvm/svm.c
> +++ b/arch/x86/kvm/svm.c
> @@ -529,6 +529,7 @@ struct svm_cpu_data {
> struct kvm_ldttss_desc *tss_desc;
>
From: Colin Ian King
Currently an out of range dev->nr is detected by just reporting the
issue and later on an out-of-bounds read on array card occurs because
of this. Fix this by checking the upper range of dev->nr with the size
of array card (removes the hard coded size), move this check earlie
On Fri, Jan 26, 2018 at 02:39:47PM +0200, Andy Shevchenko wrote:
> On Fri, Jan 19, 2018 at 10:58 AM, Rajneesh Bhardwaj
> wrote:
> > Add CPUID of Cannonlake (CNL) processors to Intel family list.
> >
> > Cc: Dave Hansen
> > Cc: Thomas Gleixner
> > cc: Ingo Molnar
> > Cc: "H. Peter Anvin"
> > Cc
On 30/01/2018 11:23, Radim Krčmář wrote:
> 2018-01-27 09:50+0100, Paolo Bonzini:
>> Place the MSR bitmap in struct loaded_vmcs, and update it in place
>> every time the x2apic or APICv state can change. This is rare and
>> the loop can handle 64 MSRs per iteration, in a similar fashion as
>> neste
On Mon, Jan 29, 2018 at 05:45:50PM +, Marc Zyngier wrote:
> Although we've implemented PSCI 1.0 and 1.1, nothing can select them
> Since all the new PSCI versions are backward compatible, we decide to
> default to the latest version of the PSCI implementation. This is no
> different from doing
On Wed, 31 Jan 2018, SF Markus Elfring wrote:
> > I removed the blank line at EOF,
> > then applied to linux-kbuild/misc.
>
> I have taken another look at this script for the semantic patch language.
> I imagined that I could refactor the shown SmPL disjunctions a bit.
> But I noticed then that
On Wed, Jan 31, 2018 at 8:55 AM, Paolo Bonzini wrote:
> In fact this MSR can even be passed down unconditionally, since it needs
> no save/restore and has no ill performance effect on the sibling
> hyperthread.
I'm a bit surprised to hear that IBPB has no ill performance impact on
the sibling hy
Hi Philipp,
On Mon, Jan 29, 2018 at 12:29:04AM +0100, Philipp Rossak wrote:
> Allwinner H3 features a thermal sensor like the one in A33, but has its
> register re-arranged, the clock divider moved to CCU (originally the
> clock divider is in ADC) and added a pair of bus clock and reset.
>
> Allw
This is mostly updates of the usual driver suspects: arcmsr,
scsi_debug, mpt3sas, lpfc, cxlflash, qla2xxx, aacraid, megaraid_sas,
hisi_sas. We also have a rework of the libsas hotplug handling to make
it more robust, a slew of 32 bit time conversions and fixes, and a host
of the usual minor update
On Wed, 2018-01-31 at 11:17 +0100, Peter Zijlstra wrote:
> On Wed, Jan 31, 2018 at 10:22:49AM +0100, Rafael J. Wysocki wrote:
> > On Tuesday, January 30, 2018 2:15:31 PM CET Peter Zijlstra wrote:
> > > IA32_HWP_REQUEST has "Minimum_Performance", "Maximum_Performance"
> > > and
> > > "Desired_Perfor
On Wed, 31 Jan 2018, Rajneesh Bhardwaj wrote:
> On Fri, Jan 26, 2018 at 02:39:47PM +0200, Andy Shevchenko wrote:
> > On Fri, Jan 19, 2018 at 10:58 AM, Rajneesh Bhardwaj
> > wrote:
> > > Add CPUID of Cannonlake (CNL) processors to Intel family list.
> > >
> > > Cc: Dave Hansen
> > > Cc: Thomas Gl
On 31/01/18 17:38, Andrew Jones wrote:
> On Mon, Jan 29, 2018 at 05:45:50PM +, Marc Zyngier wrote:
>> Although we've implemented PSCI 1.0 and 1.1, nothing can select them
>> Since all the new PSCI versions are backward compatible, we decide to
>> default to the latest version of the PSCI implem
On 01/30/2018 05:57 PM, Joel Fernandes wrote:
Signed-off-by: Rohit Jain
---
kernel/sched/fair.c | 38 --
1 file changed, 28 insertions(+), 10 deletions(-)
diff --git a/kernel/sched/fair.c b/kernel/sched/fair.c
index 26a71eb..ce5ccf8 100644
--- a/kernel/
There is no longer a need for the buffer to be defined in
first 4GB physical address space.
Furthermore there may be race conditions with multiple different functions
working on a module wide buffer causing incorrect results.
Fixes: 549b4930f057658dc50d8010e66219233119a4d8
Suggested-by: Pali Roha
On Wed, Jan 31, 2018 at 04:46:20AM +, Al Viro wrote:
> MSG and REMOVE are never triggered, so it's all down to {WR{NORM,BAND},RDHUP}.
Actually, POLLREMOVE is an amusing story (FSVO amusing): it's a part of
UnixWare /dev/poll ABI. It had _not_ lasted in Linux - epoll_ctl()
EPOLL_CTL_DEL is us
Hi Philipp,
On Mon, Jan 29, 2018 at 12:29:07AM +0100, Philipp Rossak wrote:
> For adding newer sensor some basic rework of the code is necessary.
>
> This commit reworks the code and allows the sampling start/end code and
> the position of value readout register to be altered. Later the start/end
>> Will the rule set be more consistent then?
>
> If E1 is not bound by the kem_cache_alloc rule, then it will match anything.
How much was such a software behaviour intended by the discussed SmPL script?
> The user can check if it is appropriate.
How does such an information fit to expectatio
Some headers are not needed since the driver can be built as module.
Remove them.
While here, sort headers alphabetically.
Signed-off-by: Andy Shevchenko
---
drivers/platform/x86/intel-vbtn.c | 8 +++-
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/drivers/platform/x86/intel-
Replace License short header by SPDX identifier.
Signed-off-by: Andy Shevchenko
---
drivers/platform/x86/intel-vbtn.c | 12 +---
1 file changed, 1 insertion(+), 11 deletions(-)
diff --git a/drivers/platform/x86/intel-vbtn.c
b/drivers/platform/x86/intel-vbtn.c
index 69bc39f8d61d..b703d6
On Wed, 2018-01-31 at 08:46 -0800, Linus Torvalds wrote:
> On Wed, Jan 31, 2018 at 4:29 AM, Jeff Layton wrote:
> >
> > Do you mind just taking it directly? I don't have anything else queued
> > up for this cycle.
>
> Done.
>
Thanks...and also many thanks for spotting the original issue. I agre
Hi Suravee,
On 31/01/18 01:48, Suravee Suthikulpanit wrote:
Currently, iommu_unmap and iommu_unmap_fast return unmapped
pages with size_t. However, the actual value returned could
be error codes (< 0), which can be misinterpreted as large
number of unmapped pages. Therefore, change the return t
It's 'optional' instead of 'optinal'.
Signed-off-by: Matthias Lange
---
include/sound/ac97/regs.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/sound/ac97/regs.h b/include/sound/ac97/regs.h
index 4bb86d3..9a4fa0c 100644
--- a/include/sound/ac97/regs.h
+++ b/include/
On Wed, Jan 31, 2018 at 05:45:56PM +, Marc Zyngier wrote:
> On 31/01/18 17:38, Andrew Jones wrote:
> > On Mon, Jan 29, 2018 at 05:45:50PM +, Marc Zyngier wrote:
> >> Although we've implemented PSCI 1.0 and 1.1, nothing can select them
> >> Since all the new PSCI versions are backward compat
It's 'optional' instead of 'optinal'.
Signed-off-by: Matthias Lange
---
arch/arm/include/asm/dma-mapping.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/include/asm/dma-mapping.h
b/arch/arm/include/asm/dma-mapping.h
index daf8374..34d8d3e 100644
--- a/arch/a
On Wed, Jan 24, 2018 at 03:21:11PM -0800, Jolly Shah wrote:
> Add documentation to describe Xilinx ZynqMP firmware driver
> bindings. Firmware driver provides an interface to firmware
> APIs. Interface APIs can be used by any driver to communicate
> to PMUFW (Platform Management Unit).
>
> Signed-
Hi Rob,
Thanks for the review,
> -Original Message-
> From: Rob Herring [mailto:r...@kernel.org]
> Sent: Tuesday, January 30, 2018 9:08 AM
> To: Jolly Shah
> Cc: ard.biesheu...@linaro.org; mi...@kernel.org;
> gre...@linuxfoundation.org; m...@codeblueprint.co.uk;
> sudeep.ho...@arm.com; hk
Pavel,
I assume you are working on the fix.
Do you have any progress ?
Koki
>>-Original Message-
>>From: Mel Gorman [mailto:mgor...@techsingularity.net]
>>Sent: Wednesday, December 06, 2017 5:50 AM
>>To: Pavel Tatashin
>>Cc: Michal Hocko ; YASUAKI ISHIMATSU
>>; Andrew Morton ;
>>Linux M
> On Wed, Jan 31, 2018 at 8:55 AM, Paolo Bonzini wrote:
>
> > In fact this MSR can even be passed down unconditionally, since it needs
> > no save/restore and has no ill performance effect on the sibling
> > hyperthread.
>
> I'm a bit surprised to hear that IBPB has no ill performance impact on
Kredit? so schnell wie möglich? unkompliziert und seriös ? Bei uns genau
richtig. Wir arbeiten europaweit. Wir vermitteln Kredite und Darlehen zu fairen
Konditionen. Durch unsere seriöse, kompetente und ehrliche Kreditberatung haben
wir über Jahre eine starke Position auf dem Markt.
The 'dev' pointer is directly available in gxbb and axg clock
controller, so consistently use it instead of going the through the
'pdev' pointer once in while
Signed-off-by: Jerome Brunet
---
drivers/clk/meson/axg.c | 8
drivers/clk/meson/gxbb.c | 2 +-
2 files changed, 5 insertions(+)
meson8b cpu_clk has been replaced by a set of divider and mux clocks.
meson_cpu_clk is no longer used and can be removed
Signed-off-by: Jerome Brunet
---
drivers/clk/meson/Makefile | 2 +-
drivers/clk/meson/clk-cpu.c | 178
drivers/clk/meson/clkc.h
Meson clock controllers needs to move the classical iomem registers to
regmap. This is triggered because the HHI controllers found on the GXBB
and GXL host more than just clocks. To properly handle this, we would
like to migrate HHI to syscon. Also GXBB AO clock controller already use
regmap, AXG A
On gxbb and axg, try to get the hhi regmap from the parent DT node, which
should be the HHI system controller once the necessary changes have been
made in amlogic's DTs
Until then, if getting regmap through the system controller fails, the
clock controller will fall back to the old way, requesting
aoclk_gate_regmap has been replaced by meson's clk_regmap.
It is no longer necessary so, remove it
Signed-off-by: Jerome Brunet
---
drivers/clk/meson/gxbb-aoclk-regmap.c | 46 ---
drivers/clk/meson/gxbb-aoclk.h| 10
2 files changed, 56 deletions(-
Rework meson mpll driver to use clk_regmap and move meson8b, gxbb
and axg clocks using meson_clk_mpll to clk_regmap
Signed-off-by: Jerome Brunet
---
drivers/clk/meson/axg.c | 245 +--
drivers/clk/meson/clk-mpll.c | 102 +++---
drivers/clk/
The mpll clock is a kind of fractional divider which can gate.
When the RW operation have been added, enable/disable ops have been
mistakenly inserted in this driver. These ops are essentially a
poor copy/paste of generic gate ops.
This change remove the gate ops from the mpll driver and insert a
Rework meson pll driver to use clk_regmap and move meson8b, gxbb and
axg's clock using meson_clk_pll to clk_regmap.
This rework is not just about clk_regmap, there a serious clean-up of
the driver code:
* Add lock and reset field: Previously inferred from the n field.
* Simplify the reset logic: C
Instead of migrating meson cpu_clk to clk_regmap, like the other meson
clock drivers, we take advantage of the massive rework to get rid of it
completely, and solve (the first part) of the related FIXME notice.
As pointed out in the code comments, the cpu_clk should be modeled with
dividers and mu
/0day-ci/linux/commits/Marc-Zyngier/arm64-Add-SMCCC-v1-1-support-and-CVE-2017-5715-Spectre-variant-2-mitigation/20180131-234336
base: https://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux.git
for-next/core
config: arm64-defconfig (attached as .config)
compiler: aarch64-linux-gnu-gcc (Debian
Rework meson audio divider driver to use clk_regmap and move gxbb
clock using meson_clk_audio_divider to clk_regmap.
Signed-off-by: Jerome Brunet
---
drivers/clk/meson/clk-audio-divider.c | 63 +++
drivers/clk/meson/clkc.h | 5 +--
drivers/clk/meson/
Meson clock drivers are using struct parm to describe each field of the
clock provider. Providing helpers to access these field with regmap helps
keep drivers readable
Signed-off-by: Jerome Brunet
---
drivers/clk/meson/clkc.h | 16
1 file changed, 16 insertions(+)
diff --git a/
Drop the gxbb ao specific regmap based clock and use the
meson clk_regmap based clock instead.
Signed-off-by: Jerome Brunet
---
drivers/clk/meson/Kconfig | 1 +
drivers/clk/meson/Makefile | 2 +-
drivers/clk/meson/gxbb-aoclk.c | 20 ++--
drivers/clk/meson/gxbb-aoclk.h
Move meson8b, gxbb and axg clocks using clk_mux to clk_regmap
Also remove a few useless tables in the process
Signed-off-by: Jerome Brunet
---
drivers/clk/meson/axg.c | 60 -
drivers/clk/meson/gxbb.c| 312 +---
drivers/clk/meson/meson8b.c
Move meson8b, gxbb and axg clocks using clk_divider to clk_regmap
Signed-off-by: Jerome Brunet
---
drivers/clk/meson/axg.c | 61 ++---
drivers/clk/meson/gxbb.c| 217 ++--
drivers/clk/meson/meson8b.c | 23 ++---
3 files changed, 142 insert
Hi Linus,
This merge cycle, we're again some substantive changes to XFS. Metadata
verifiers have been restructured to provide more detail about which part
of a metadata structure failed checks, and we've enhanced the new online
fsck feature to cross-reference extent allocation information with th
This change register a regmap in meson8b, gxbb and axg controllers.
The clock are still accessing their registers directly through iomem.
Once all clocks handled by these controllers have been move to regmap,
the regmap register will be removed and replaced with a syscon request.
Signed-off-by: Je
2018-01-31 12:37-0500, Paolo Bonzini:
> On 30/01/2018 11:23, Radim Krčmář wrote:
> > 2018-01-27 09:50+0100, Paolo Bonzini:
> >> Place the MSR bitmap in struct loaded_vmcs, and update it in place
> >> every time the x2apic or APICv state can change. This is rare and
> >> the loop can handle 64 MSRs
301 - 400 of 704 matches
Mail list logo
