From: Dave Hansen
In preparation to adding additional PCID flushing, abstract the
loading of a new ASID into CR3.
[ PeterZ: Split out from big combo patch ]
Signed-off-by: Dave Hansen
Signed-off-by: Peter Zijlstra (Intel)
Signed-off-by: Ingo Molnar
Signed-off-by: Thomas Gleixner
Cc: Andy Lu
From: Peter Zijlstra
We can use PCID to retain the TLBs across CR3 switches; including those now
part of the user/kernel switch. This increases performance of kernel
entry/exit at the cost of more expensive/complicated TLB flushing.
Now that we have two address spaces, one for kernel and one for
From: Dave Hansen
Kernel page table isolation requires to have two PGDs. One for the kernel,
which contains the full kernel mapping plus the user space mapping and one
for user space which contains the user space mappings and the minimal set
of kernel mappings which are required by the architectu
From: Andy Lutomirski
Shrink vmalloc space from 16384TiB to 12800TiB to enlarge the hole starting
at 0xff90 to be a full PGD entry.
A subsequent patch will use this hole for the pagetable isolation LDT
alias.
Signed-off-by: Andy Lutomirski
Signed-off-by: Thomas Gleixner
Cc: Kees C
From: Andy Lutomirski
Make VSYSCALLs work fully in PTI mode.
Signed-off-by: Andy Lutomirski
Signed-off-by: Thomas Gleixner
Cc: Kees Cook
Cc: Peter Zijlstra
Cc: Brian Gerst
Cc: David Laight
Cc: Borislav Petkov
---
arch/x86/entry/vsyscall/vsyscall_64.c |6 +--
arch/x86/include/asm/vsy
From: Thomas Gleixner
init_espfix_bsp() needs to be invoked before the page table isolation
initialization. Move it into mm_init() which is the place where pti_init()
will be added.
While at it get rid of the #ifdeffery and provide proper stub functions.
Signed-off-by: Thomas Gleixner
---
arc
On Thu, Dec 21, 2017 at 12:05:40AM +0300, Dmitry Osipenko wrote:
> On 20.12.2017 23:16, Thierry Reding wrote:
> > On Wed, Dec 20, 2017 at 11:01:49PM +0300, Dmitry Osipenko wrote:
> >> On 20.12.2017 21:01, Thierry Reding wrote:
> >>> On Wed, Dec 20, 2017 at 06:46:11PM +0300, Dmitry Osipenko wrote:
>
From: Hugh Dickins
The BTS and PEBS buffers both have their virtual addresses programmed into
the hardware. This means that any access to them is performed via the page
tables. The times that the hardware accesses these are entirely dependent
on how the performance monitoring hardware events ar
From: Thomas Gleixner
The Intel PEBS/BTS debug store is a design trainwreck as it expects virtual
addresses which must be visible in any execution context.
So it is required to make these mappings visible to user space when kernel
page table isolation is active.
Provide enough room for the buff
From: Andy Lutomirski
Map the ESPFIX pages into user space when PTI is enabled.
Signed-off-by: Andy Lutomirski
Signed-off-by: Thomas Gleixner
Cc: Kees Cook
Cc: Peter Zijlstra
Cc: Brian Gerst
Cc: David Laight
Cc: Borislav Petkov
---
arch/x86/mm/pti.c | 11 +++
1 file changed, 11
From: Dave Hansen
First, it's nice to remove the magic numbers.
Second, PAGE_TABLE_ISOLATION is going to consume half of the available ASID
space. The space is currently unused, but add a comment to spell out this
new restriction.
Signed-off-by: Dave Hansen
Signed-off-by: Thomas Gleixner
Sig
On Wed, 20 Dec 2017, Thomas Gleixner wrote:
> From: Vlastimil Babka
>
> CONFIG_PAGE_TABLE_ISOLATION is relatively new and intrusive feature that may
> still have some corner cases which could take some time to manifest and be
> fixed. It would be useful to have Oops messages indicate whether it
From: Thomas Gleixner
Share the entry text PMD of the kernel mapping with the user space
mapping. If large pages are enabled this is a single PMD entry and at the
point where it is copied into the user page table the RW bit has not been
cleared yet. Clear it right away so the user space visible m
From: Thomas Gleixner
The (irq)entry text must be visible in the user space page tables. To allow
simple PMD based sharing, make the entry text PMD aligned.
Signed-off-by: Thomas Gleixner
Signed-off-by: Ingo Molnar
Cc: Andy Lutomirski
Cc: Boris Ostrovsky
Cc: Borislav Petkov
Cc: Brian Gerst
From: Thomas Gleixner
Force the entry through the trampoline only when PTI is active. Otherwise
go through the normal entry code.
Signed-off-by: Thomas Gleixner
Signed-off-by: Ingo Molnar
Reviewed-by: Borislav Petkov
Cc: Andy Lutomirski
Cc: Boris Ostrovsky
Cc: Brian Gerst
Cc: Dave Hansen
From: Dave Hansen
There are effectively two ASID types:
1. The one stored in the mmu_context that goes from 0..5
2. The one programmed into the hardware that goes from 1..6
This consolidates the locations where converting between the two (by doing
a +1) to a single place which gives us a nice
From: Andy Lutomirski
Provide infrastructure to:
- find a kernel PMD for a mapping which must be visible to user space for
the entry/exit code to work.
- walk an address range and share the kernel PMD with it.
This reuses a small part of the original KAISER patches to populate the
user sp
On 12/20/2017 4:41 PM, Andi Kleen wrote:
On Wed, Dec 20, 2017 at 11:42:51AM -0800, kan.li...@linux.intel.com wrote:
From: Kan Liang
The userspace RDPMC usage never works for large PEBS since the large
PEBS is introduced by
commit b8241d20699e ("perf/x86/intel: Implement batched PEBS interrup
From: Dave Hansen
In clone_pgd_range() copy the init user PGDs which cover the kernel half of
the address space, so a process has all the required kernel mappings
visible.
[ tglx: Split out from the big kaiser dump and folded Andys simplification ]
Signed-off-by: Dave Hansen
Signed-off-by: Ing
From: Peter Zijlstra
atomic64_inc_return() already implies smp_mb() before and after.
Signed-off-by: Peter Zijlstra (Intel)
Signed-off-by: Ingo Molnar
Signed-off-by: Thomas Gleixner
Cc: Andy Lutomirski
Cc: Boris Ostrovsky
Cc: Borislav Petkov
Cc: Brian Gerst
Cc: Dave Hansen
Cc: David Laig
From: Dave Hansen
PAGE_TABLE_ISOLATION needs to switch to a different CR3 value when it
enters the kernel and switch back when it exits. This essentially needs to
be done before leaving assembly code.
This is extra challenging because the switching context is tricky: the
registers that can be c
From: Thomas Gleixner
Add the initial files for kernel page table isolation, with a minimal init
function and the boot time detection for this misfeature.
Signed-off-by: Thomas Gleixner
Signed-off-by: Ingo Molnar
Reviewed-by: Borislav Petkov
Cc: Andy Lutomirski
Cc: Boris Ostrovsky
Cc: Brian
> On Dec 20, 2017, at 1:25 PM, Peter Zijlstra wrote:
>
> On Wed, Dec 20, 2017 at 06:10:11PM +, Song Liu wrote:
>> I think there is one more thing to change:
>
> OK, folded that too; it should all be at:
>
> git://git.kernel.org/pub/scm/linux/kernel/git/peterz/queue.git perf/core
>
> Can
From: Dave Hansen
Global pages stay in the TLB across context switches. Since all contexts
share the same kernel mapping, these mappings are marked as global pages
so kernel entries in the TLB are not flushed out on a context switch.
But, even having these entries in the TLB opens up something
From: Thomas Gleixner
The LDT is inheritet independent of fork or exec, but that makes no sense
at all because exec is supposed to start the process clean.
The reason why this happens is that init_new_context_ldt() is called from
init_new_context() which obviously needs to be called for both for
Put the cpu_entry_area into a separate p4d entry. The fixmap gets too bug
and 0-day already hit a case where the fixmap ptes were cleared by
cleanup_highmap().
Aside of that the fixmap API is a pain as it's all backwards.
Signed-off-by: Thomas Gleixner
---
Documentation/x86/x86_64/mm.txt
From: Thomas Gleixner
Many x86 CPUs leak information to user space due to missing isolation of
user space and kernel space page tables. There are many well documented
ways to exploit that.
The upcoming software migitation of isolating the user and kernel space
page tables needs a misfeature flag
Separate the cpu_entry_area code out of cpu/common.c and the fixmap.
Signed-off-by: Thomas Gleixner
---
arch/x86/include/asm/cpu_entry_area.h | 52 +
arch/x86/include/asm/fixmap.h | 41 -
arch/x86/kernel/cpu/common.c | 94 ---
For flushing the TLB, the ASID which has been programmed into the hardware
must be known. That differs from what is in 'cpu_tlbstate'.
Add functions to transform the 'cpu_tlbstate' values into to the one
programmed into the hardware (CR3).
It's not easy to include mmu_context.h into tlbflush.h,
The recent cpu_entry_area changes fail to compile on 32bit when BIGSMP=y
and NR_CPUS=512 because the fixmap area becomes too big.
Limit the number of CPUs with BIGSMP to 64, which is already way to big for
32bit, but it's at least a working limitation.
Signed-off-by: Thomas Gleixner
---
arch/x8
From: Peter Zijlstra
Per popular request..
Signed-off-by: Peter Zijlstra (Intel)
Signed-off-by: Ingo Molnar
Signed-off-by: Thomas Gleixner
Cc: Andy Lutomirski
Cc: Boris Ostrovsky
Cc: Borislav Petkov
Cc: Brian Gerst
Cc: Dave Hansen
Cc: David Laight
Cc: Denys Vlasenko
Cc: Eduardo Valenti
From: Peter Zijlstra
Commit: ec400ddeff20 ("x86/microcode_intel_early.c: Early update ucode on
Intel's CPU") grubbed into tlbflush internals without coherent explanation.
Since it says its precaution and the SDM doesn't mention anything like
this, take it out back.
Signed-off-by: Peter Zijlstra
From: Andy Lutomirski
If something goes wrong with pagetable setup, vsyscall=native will
accidentally fall back to emulation. Make it warn and fail so that we
notice.
Signed-off-by: Andy Lutomirski
Signed-off-by: Ingo Molnar
Signed-off-by: Thomas Gleixner
Cc: Borislav Petkov
Cc: Brian Gerst
From: Peter Zijlstra
Signed-off-by: Peter Zijlstra (Intel)
Signed-off-by: Ingo Molnar
Signed-off-by: Thomas Gleixner
Cc: Andy Lutomirski
Cc: Boris Ostrovsky
Cc: Borislav Petkov
Cc: Brian Gerst
Cc: Dave Hansen
Cc: David Laight
Cc: Denys Vlasenko
Cc: Eduardo Valentin
Cc: Greg KH
Cc: H.
From: Dave Hansen
If the kernel oopses while on the trampoline stack, it will print
"" even if SYSENTER is not involved. That is rather confusing.
The "SYSENTER" stack is used for a lot more than SYSENTER now. Give it a
better string to display in stack dumps, and rename the kernel code to
mat
From: Thomas Gleixner
The check for a present page in printk_prot():
if (!pgprot_val(prot)) {
/* Not present */
is bogus. If a PTE is set to PAGE_NONE then the pgprot_val is not zero and
the entry is decoded in bogus ways, e.g. as RX GLB. That is confusing when
analyzing
From: Peter Zijlstra
The LDT is duplicated on fork() and on exec(), which is wrong as exec()
should start from a clean state, i.e. without LDT. To fix this the LDT
duplication code will be moved into arch_dup_mmap() which is only called
for fork().
This introduces a locking problem. arch_dup_mma
From: Andy Lutomirski
The old docs had the vsyscall range wrong* and were missing the fixmap.
Fix both.
There used to be 8 MB reserved for future vsyscalls, but that's long gone.
Signed-off-by: Andy Lutomirski
Signed-off-by: Thomas Gleixner
Cc: Kees Cook
Cc: Peter Zijlstra
Cc: Brian Gerst
Changes since V163:
- Moved the cpu entry area out of the fixmap because that caused failures
due to fixmap size and cleanup_highmap() zapping fixmap PTEs.
- Moved all cpu entry area related code into separate files. The
hodgepodge in cpu/common.c was really not appropriate.
- Fold
From: Andy Lutomirski
The kernel is very erratic as to which pagetables have _PAGE_USER set. The
vsyscall page gets lucky: it seems that all of the relevant pagetables are
among the apparently arbitrary ones that set _PAGE_USER. Rather than
relying on chance, just explicitly set _PAGE_USER.
Th
The address hints are a trainwreck. The array entry numbers have to kept
magically in sync with the actual hints, which is doomed as some of the
array members are initialized at runtime via the entry numbers.
Designated initializers have been around before this code was
implemented
Use the en
This patch adds a new sysfs group, namely health, via:
/sys/devices/soc/X.ufshc/health/
This directory contains the below entries, each of which shows an 8-bytes
hex number representing different meanings defined by JEDEC specfication.
Users can simply read these entries to check how their un
On Tue, Dec 19, 2017 at 05:11:38PM -0800, Dan Williams wrote:
> On Fri, Nov 10, 2017 at 1:08 AM, Christoph Hellwig wrote:
> >> + struct {
> >> + /*
> >> + * ZONE_DEVICE pages are never on an lru or handled
> >> by
> >> + *
tree: https://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git WIP.x86/pti
head: 448c49e07e52076586e9e706212298d865ad7a27
commit: f443b8fc21e63b63b3064974c27ab78cbcb39c07 [21/54] x86/cpu_entry_area:
Move it to a separate unit
config: x86_64-randconfig-x011-201751 (attached as .config)
compi
On 21.12.2017 01:02, Thierry Reding wrote:
> On Thu, Dec 21, 2017 at 12:05:40AM +0300, Dmitry Osipenko wrote:
>> On 20.12.2017 23:16, Thierry Reding wrote:
>>> On Wed, Dec 20, 2017 at 11:01:49PM +0300, Dmitry Osipenko wrote:
On 20.12.2017 21:01, Thierry Reding wrote:
> On Wed, Dec 20, 2017
Hi Linus
I'm working on gpio for an AMD Family 16h Model 30h system[1]. The SoC is the
same as the GX412-TC used in the PC Engines APU2.
There is an out-of-tree gpio driver (gpio-amd) for this SoC in the meta-amd
yocto layer[2].
Another driver (gpio-sb8xx) was submitted for upstream inclusion,
On 12/19/2017 11:36 AM, Peter Zijlstra wrote:
On Fri, Dec 08, 2017 at 12:07:54PM -0800, subhra mazumdar wrote:
+static inline void
+sd_context_switch(struct sched_domain *sd, struct rq *rq, int util)
+{
+ struct sched_group *sg_cpu;
+
+ /* atomically add/subtract the util */
+
On Wed, 20 Dec 2017, Thomas Gleixner wrote:
> +++ b/arch/x86/mm/cpu_entry_area.c
> @@ -0,0 +1,102 @@
> +// SPDX-License-Identifier: GPL-2.0
> +
Lacks an
#include as 0-day noticed
> +#include
> +#include
> +#include
> +#include
> +#include
Thanks,
tglx
From: Eric Biggers
pcrypt is using the old way of freeing instances, where the ->free()
method specified in the 'struct crypto_template' is passed a pointer to
the 'struct crypto_instance'. But the crypto_instance is being
kfree()'d directly, which is incorrect because the memory was actually
al
On Wed, Dec 20, 2017 at 1:24 PM, Ross Zwisler
wrote:
> On Wed, Dec 20, 2017 at 01:16:49PM -0800, Matthew Wilcox wrote:
>> On Wed, Dec 20, 2017 at 12:22:21PM -0800, Dave Hansen wrote:
>> > On 12/20/2017 10:19 AM, Matthew Wilcox wrote:
>> > > I don't know what the right interface is, but my laptop h
On Mon, Nov 27, 2017 at 12:42 AM, Wu Hao wrote:
Hi Hao,
> +
> +enum port_feature_id {
> + PORT_FEATURE_ID_HEADER = 0x0,
> + PORT_FEATURE_ID_ERROR = 0x1,
> + PORT_FEATURE_ID_UMSG = 0x2,
> + PORT_FEATURE_ID_PR = 0x3,
> + PORT_FEATURE_ID_STP = 0x4,
> + PORT_FEATU
tree: https://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git WIP.x86/pti
head: 448c49e07e52076586e9e706212298d865ad7a27
commit: 8b65ec93225592fbc35ab8107fd880e505aae1ef [22/54] x86/cpu_entry_area:
Move it out of fixmap
config: i386-randconfig-x016-201751 (attached as .config)
compiler: gc
On Mon, Nov 27, 2017 at 12:42 AM, Wu Hao wrote:
> +
> +PORT
> +
> +A port represents the interface between the static FPGA fabric (the "blue
> +bitstream") and a partially reconfigurable region containing an AFU (the
> "green
> +bitstream"). It controls the communication from SW to the accele
On Mon, Dec 18, 2017 at 07:25:41AM +0100, Stephan Mueller wrote:
> Am Montag, 18. Dezember 2017, 06:50:01 CET schrieb syzbot:
>
> Hi,
>
> > Hello,
> >
> > syzkaller hit the following crash on
> > 41d8c16909ebda40f7b4982a7f5e2ad102705ade
> > git://git.kernel.org/pub/scm/linux/kernel/git/next/linu
On Tue, Dec 19, 2017 at 11:48:01PM -0800, syzbot wrote:
> Hello,
>
> syzkaller hit the following crash on
> 032b4cc8ff84490c4bc7c4ef8c91e6d83a637538
> git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/master
> compiler: gcc (GCC) 7.1.1 20170620
> .config is attached
> Raw console ou
On 21.12.2017 01:23, Dmitry Osipenko wrote:
> On 21.12.2017 01:02, Thierry Reding wrote:
>> On Thu, Dec 21, 2017 at 12:05:40AM +0300, Dmitry Osipenko wrote:
>>> On 20.12.2017 23:16, Thierry Reding wrote:
On Wed, Dec 20, 2017 at 11:01:49PM +0300, Dmitry Osipenko wrote:
> On 20.12.2017 21:01
On Wed, Dec 20, 2017 at 12:51:01PM -0800, syzbot wrote:
> Hello,
>
> syzkaller hit the following crash on
> 6084b576dca2e898f5c101baef151f7bfdbb606d
> git://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/master
> compiler: gcc (GCC) 7.1.1 20170620
> .config is attached
> Raw console o
On Wed, Dec 20, 2017 at 6:38 AM, Jan Kara wrote:
> On Tue 19-12-17 17:11:38, Dan Williams wrote:
>> On Fri, Nov 10, 2017 at 1:08 AM, Christoph Hellwig wrote:
>> >> + struct {
>> >> + /*
>> >> + * ZONE_DEVICE pages are never on an lru or handled
On Wed, Dec 20, 2017 at 02:29:56PM -0800, Dan Williams wrote:
> On Wed, Dec 20, 2017 at 1:24 PM, Ross Zwisler
> wrote:
> > On Wed, Dec 20, 2017 at 01:16:49PM -0800, Matthew Wilcox wrote:
> >> On Wed, Dec 20, 2017 at 12:22:21PM -0800, Dave Hansen wrote:
> >> > On 12/20/2017 10:19 AM, Matthew Wilcox
On 12/20/2017 01:53 AM, Michal Hocko wrote:
> On Wed 20-12-17 05:33:36, Naoya Horiguchi wrote:
>> I have one comment on the code path from mbind(2).
>> The callback passed to migrate_pages() in do_mbind() (i.e. new_page())
>> calls alloc_huge_page_noerr() which currently doesn't call
>> SetPageHug
The original purpose of the per-superblock d_anon list was to
keep disconnected dentries in the cache between consecutive
requests to the NFS server. Dentries can be disconnected if
a client holds a file open and repeatedly performs IO on it,
and if the server drops the dentry, whether due to mem
Tejun Heo writes:
> Hello,
>
> Applied the following to cgroup/for-4.15-fixes. Will push out to
> linus later this week. I could reproduce the problem reliably and am
> pretty sure this is the right fix but I'd greatly appreciate if you
> guys can confirm the fix too.
Fixed here as well, 4.14
ARC gcc prior to GNU 2018.03 release didn't have a target specific
__builtin_trap() implementation, generating default abort() call.
Implement the abort() call - emulating what newer gcc does for the same,
as suggested by Arnd.
Signed-off-by: Vineet Gupta
---
arch/arc/kernel/traps.c | 9 +++
Vineet Gupta (2):
ARC: handle gcc generated __builtin_trap()
ARC: handle gcc generated __builtin_trap for older compiler
arch/arc/kernel/traps.c| 14 ++
arch/arc/kernel/troubleshoot.c | 3 +++
2 files changed, 17 insertions(+)
--
2.7.4
gcc toggle -fisolate-erroneous-paths-dereference (default at -O2
onwards) isolates faulty code paths such as null pointer access, divide
by zero etc by emitting __builtin_trap()
Newer ARC gcc generates TRAP_S 5 instruction correspondingly which this
patch handles. If user mode, the task is termina
From: Fenghua Yu
L2 data and L2 code are added as new resources in rdt_resources_all[]
and data in the resources are configured.
When L2 CDP is enabled, the schemata will have the two resources in
this format:
L2DATA:l2id0=;l2id1=;
L2CODE:l2id0=;l2id1=;
Signed-off-by: Fe
From: Fenghua Yu
With more flag bits in /proc/cpuinfo for RDT, it's better to classify the
bits for readability.
Some previously missing bits are added as well.
Signed-off-by: Fenghua Yu
---
Documentation/x86/intel_rdt_ui.txt | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff
From: Fenghua Yu
Bit 0 in MSR IA32_L2_QOS_CFG (0xc82) is L2 CDP enable bit. By default,
the bit is zero, i.e. L2 CAT is enabled, and L2 CDP is disabled. When
the resctrl mount parameter "cdpl2" is given, the bit is set as 1 and L2
CDP is enabled.
In L2 CDP mode, the L2 CAT mask MSRs are re-mappe
From: Fenghua Yu
L2 CDP can be turned on or off by kernel parameter "rdt=".
If "rdt=l2cdp", L2 CDP is turned on.
If "rdt=!l2cdp", L2 CDP is turned off.
Signed-off-by: Fenghua Yu
---
Documentation/admin-guide/kernel-parameters.txt | 3 ++-
arch/x86/kernel/cpu/intel_rdt.c | 2 ++
From: Fenghua Yu
A new mount parameter "cdpl2" is added to enable L2 CDP in documentation.
The legacy mount parameter "cdp" is still used to enable L3 CDP.
L2 and L3 CDP can be enabled separately.
Signed-off-by: Fenghua Yu
---
Documentation/x86/intel_rdt_ui.txt | 8 ++--
1 file changed, 6
From: Fenghua Yu
L2 CDP enables isolation and prioritization of code and data individually
within the L2 cache. The feature is enumerated in
CPUID.(EAX=0x10, ECX=2):ECX.CDP[bit 2] and enabled in bit 0 of MSR
IA32_L2_QOS_CFG at address 0xc82.
As with L3 CDP, when L2 CDP is enabled, each CLOS is m
From: Fenghua Yu
L2 Code and Data Prioritization (CDP) is enumerated in
CPUID(EAX=0x10, ECX=0x2):ECX.bit2
Signed-off-by: Fenghua Yu
---
arch/x86/include/asm/cpufeatures.h | 1 +
arch/x86/kernel/cpu/scattered.c| 1 +
2 files changed, 2 insertions(+)
diff --git a/arch/x86/include/asm/cpufea
On Thu, Dec 21, 2017 at 09:45:40AM +1100, NeilBrown wrote:
> -c/ Helper routines to allocate anonymous dentries, and to help attach
> + prefix. If the refcount on a dentry with this flag set
> + becomes zero, the dentry is immediately discarded, rather than being
> + kept in the dcache. If
Hi,
Using netconsole, I was able to capture a hard lockup that seems to be
related to cgroups, on a Fedora kernel based on v4.14.4.
By my analysis, from the 16 CPUs below, 14 are on css_set_lock, one is
inside css_task_iter_advance, and the last one stuck trying to send an
IPI, I guess because al
Hi all,
Today's linux-next merge of the net-next tree got a conflict in:
drivers/net/ethernet/netronome/nfp/bpf/main.c
between commit:
d3f89b98e391 ("nfp: bpf: keep track of the offloaded program")
from the net tree and commit:
bd0b2e7fe611 ("net: xdp: make the stack take care of the te
On Mon, Dec 18, 2017 at 11:36:01AM -0800, syzbot wrote:
> Hello,
>
> syzkaller hit the following crash on
> 6084b576dca2e898f5c101baef151f7bfdbb606d
> git://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/master
> compiler: gcc (GCC) 7.1.1 20170620
> .config is attached
FYI, in linux-
On 12/20/2017 01:59 PM, Alexey Dobriyan wrote:
> struct proc_dir_entry became bit messy over years:
>
> * move 16-bit ->mode_t before namelen to get rid of padding
> * make ->in_use first field: it seems to be most used resulting in
> smaller code on x86_64 (defconfig):
>
> add/remove: 0/
On 20.12.2017 13:06, Linus Walleij wrote:
> On Tue, Dec 19, 2017 at 12:07 AM, Maciej S. Szmigiero
> wrote:
>> On 18.12.2017 22:22, Linus Walleij wrote:
>
(..)
+static void winbond_gpio_warn_conflict(unsigned int idx, const char
*otherdev)
+{
+ pr_warn(WB_GPIO_DRIVER_NAM
On Wed, Dec 20 2017, Matthew Wilcox wrote:
> On Thu, Dec 21, 2017 at 09:45:40AM +1100, NeilBrown wrote:
>> -c/ Helper routines to allocate anonymous dentries, and to help attach
>> + prefix. If the refcount on a dentry with this flag set
>> + becomes zero, the dentry is immediately discarded,
On Thu, Dec 21, 2017 at 09:45:40AM +1100, NeilBrown wrote:
> -c/ Helper routines to allocate anonymous dentries, and to help attach
> + prefix. If the refcount on a dentry with this flag set
> + becomes zero, the dentry is immediately discarded, rather than being
> + kept in the dcache. If
On Wed, Dec 20, 2017 at 07:47:41PM +, Joao Pinto wrote:
>
> Hello to all,
>
> Às 5:34 PM de 12/20/2017, Lorenzo Pieralisi escreveu:
> > On Wed, Dec 20, 2017 at 12:29:21AM +0100, Niklas Cassel wrote:
> >> This is a series that adds:
> >> - PCI endpoint mode support in the ARTPEC-6 driver.
> >>
On 12/20/2017 02:57 PM, Fenghua Yu wrote:
> From: Fenghua Yu
>
> L2 data and L2 code are added as new resources in rdt_resources_all[]
> and data in the resources are configured.
>
> When L2 CDP is enabled, the schemata will have the two resources in
> this format:
> L2DATA:l2id0=;l2id1=
On Thu, Dec 21, 2017 at 12:59:23AM +0200, Dan Aloni wrote:
> Hi,
>
> Using netconsole, I was able to capture a hard lockup that seems to be
> related to cgroups, on a Fedora kernel based on v4.14.4.
>
> By my analysis, from the 16 CPUs below, 14 are on css_set_lock, one is
> inside css_task_iter_
> > When L2 CDP is enabled, the schemata will have the two resources in
> > this format:
> > L2DATA:l2id0=;l2id1=;
> > L2CODE:l2id0=;l2id1=;
>
> Hi,
>
> What do the represent?
The represents CBM (Cache Bit Mask) values in the schemata, similar to all
others (L2
pmu_format_value() does not always return the correct value when the
default format attribute value is overwritten on the perf command line.
This happens because in pmu_format_value(), the default value is not
actually being overwritten by the new value, but only bits either set
in the new or the
Currently, the maximum value of every format attribute is not being
correctly set.
For eg:
cat /sys/devices/cpu/format/umask
config:8-15
This implies the max_value of umask should be 0xff
./perf stat –e cpu/umask=0x100/ sleep 1
Performance counter stats for '../rets-128.bin':
0
Intel processor changes necessitated UV4 HUB Global Address Memory
(GAM) fixes to accommodate support for those processors. This patch
deals with the updated address range change from 46 to 52 bits in UV4A.
Signed-off-by: Mike Travis
Signed-off-by: Andrew Banman
---
arch/x86/include/asm/uv/uv_
Along with the fixes in UV4A (rev2) MMRs, the code to access those
MMRs also was modified by the fixes. UV3, UV4, and UV4A no longer
have compatible setups for Global Address Memory (GAM). Correct the
new mistakes.
Signed-off-by: Mike Travis
Signed-off-by: Andrew Banman
---
arch/x86/kernel/ap
Regenerate uv_mmrs.h file to accommodate fixes to UV4A MMRs.
Signed-off-by: Mike Travis
Signed-off-by: Andrew Banman
---
arch/x86/include/asm/uv/uv_mmrs.h | 615 +-
1 file changed, 533 insertions(+), 82 deletions(-)
diff --git a/arch/x86/include/asm/uv/uv_mm
This patchset handles the fixes made to the UV4 HUB for upcoming Intel
processors as there are some interface changes.
* Update uv_mmrs.h to prep for fixed defines for UV4A.
* Updates to handle UV4 vs. UV4A (fixed) arches.
* Updates to handle UV4 GAM (global addressable memory) MMRs
Add references to enable access to fixed UV4A (rev2) HUB MMRs.
Signed-off-by: Mike Travis
Signed-off-by: Andrew Banman
---
arch/x86/include/asm/uv/uv_hub.h | 14 ++
arch/x86/include/asm/uv/uv_mmrs.h | 1 +
arch/x86/kernel/apic/x2apic_uv_x.c | 2 ++
3 files changed, 17 insertion
Fixes to accommodate Intel Processor changes for UV4A broadcast assist unit
(BAU) MMRs.
Signed-off-by: Mike Travis
Signed-off-by: Andrew Banman
---
arch/x86/include/asm/uv/uv_mmrs.h | 59 +--
1 file changed, 38 insertions(+), 21 deletions(-)
diff --git a/arc
Hello, Shakeel.
On Wed, Dec 20, 2017 at 12:15:46PM -0800, Shakeel Butt wrote:
> > I don't understand how this invariant is useful across different
> > backing swap devices and availability. e.g. Our OOM decisions are
> > currently not great in that the kernel can easily thrash for a very
> > long
On 12/20/2017 12:09 PM, Corentin Labbe wrote:
> This patch implement a generic way to get statistics about all crypto
> usages.
>
> Signed-off-by: Corentin Labbe
> ---
> crypto/Kconfig | 11 +++
> crypto/ahash.c | 18 +
> crypto/algapi.c| 186
>
On 12/20/2017 12:09 PM, Corentin Labbe wrote:
> Add an example tool for getting easily crypto statistics.
>
> Signed-off-by: Corentin Labbe
> ---
> tools/crypto/cryptostat | 40
> 1 file changed, 40 insertions(+)
> create mode 100755 tools/crypto/cryptos
Upcoming Intel CascadeLake and IceLake processors have some architecture
changes that required fixes in the UV4 HUB bringing that chip to
revision 2. The nomenclature for that new chip is "UV4A".
This patch fixes the references for the expanded MMR definitions in the
previous (automated) patch.
Replaces hard-coded node ID shift for the descriptor base mmr to fix
initialization on UV4A while maintaining previous architectures.
Signed-off-by: Andrew Banman
Acked-by: Mike Travis
---
arch/x86/include/asm/uv/uv_bau.h | 1 -
arch/x86/platform/uv/tlb_uv.c| 3 ++-
2 files changed, 2 inse
On Tue, 2017-12-12 at 11:01 -0800, Tejun Heo wrote:
> Currently, blk-mq timeout path synchronizes against the usual
> issue/completion path using a complex scheme involving atomic
> bitflags, REQ_ATOM_*, memory barriers and subtle memory coherence
> rules. Unfortunatley, it contains quite a few ho
On Mon, Dec 18, 2017 at 11:36:01AM -0800, syzbot wrote:
> Hello,
>
> syzkaller hit the following crash on
> 6084b576dca2e898f5c101baef151f7bfdbb606d
> git://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/master
> compiler: gcc (GCC) 7.1.1 20170620
> .config is attached
> Raw console o
Hi all,
After merging the net-next tree, today's linux-next build (x86_64
allmodconfig) failed like this:
drivers/net/netdevsim/bpf.c: In function 'nsim_bpf_setup_tc_block_cb':
drivers/net/netdevsim/bpf.c:127:7: error: 'TC_CLSBPF_REPLACE' undeclared (first
use in this function)
case TC_CLSBPF_
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