From: Suren Baghdasaryan
Overflow on memcpy is possible in kernel driver for st21nfca's
NFC HCI layer when handling connectivity events if aid_len or
params_len are bigger than the buffer size.
Memory leak is possible when parameter tag is invalid.
Signed-off-by: Suren Baghdasaryan
Signed-off-b
From: Suren Baghdasaryan
When handling SHDLC I-Frame commands "pipe" field used for indexing
into an array should be checked before usage. If left unchecked it
might access memory outside of the array of size NFC_HCI_MAX_PIPES(127).
Signed-off-by: Suren Baghdasaryan
Signed-off-by: Amit Pundir
On Tue, Dec 19, 2017 at 10:31 AM, AKASHI Takahiro
wrote:
> On Mon, Dec 18, 2017 at 02:29:05PM +0530, Bhupesh SHARMA wrote:
>>
>> [snip..]
>>
>> [0.00] linux,usable-memory-range base e80, size 2000
>> [0.00] - e80 , 2000
>> [0.00] linux,usable-memory-range
From: Suren Baghdasaryan
Out of bounds kernel accesses in st21nfca's NFC HCI layer
might happen when handling ATR_REQ events if user-specified
atr_req->length is bigger than the buffer size. In
that case memcpy() inside st21nfca_tm_send_atr_res() will
read extra bytes resulting in OOB read from t
+ Kai
One more thing:
On Wed, Dec 20, 2017 at 11:51:14AM -0800, Brian Norris wrote:
> Hi Greg,
>
> On Mon, Dec 18, 2017 at 04:47:58PM +0100, Greg Kroah-Hartman wrote:
> > 4.4-stable review patch. If anyone has any objections, please let me know.
>
> I'm sorry, but I already objected to this on
Hi,
On 12/16/2017 05:54 AM, SF Markus Elfring wrote:
> From: Markus Elfring
> Date: Sat, 16 Dec 2017 14:21:04 +0100
>
> Replace the specification of data structures by variable references
> as the parameter for the operator "sizeof" to make the corresponding size
> determination a bit safer acco
Update the IOMMU default domain address width to 57 bits. This would
enable the IOMMU to do upto 5-levels of paging for second level
translations - IOVA translation requests without PASID.
Even though the maximum supported address width is being increased to
57, __iommu_calculate_agaw() would set
Hi All,
Upcoming hardware plans to introduce support for 5-level paging[1]. The support
for CPU 5-level paging has already been merged in kernel v4.14. The following
patches add support for Intel IOMMU 5-level paging. The patches are based on
the Intel Virtualization Technology for Directed I/O sp
If the CPU has support for 5-level paging enabled and the IOMMU also
supports 5-level paging then enable the 5-level paging mode for first-
level translations - used when SVM is enabled.
Signed-off-by: Sohil Mehta
---
drivers/iommu/intel-svm.c | 15 +--
1 file changed, 13 insertions(
On 12/20/2017 1:13 PM, Borislav Petkov wrote:
> On Thu, Dec 07, 2017 at 05:33:52PM -0600, Tom Lendacky wrote:
>> In preparation for encrypting more than just the kernel during early
>> boot processing, centralize the use of the PMD flag settings based
>> on the type of mapping desired. When 4KB al
Add a check to verify IOMMU 5-level paging support. If the CPU supports
supports 5-level paging but the IOMMU does not support it then disable
SVM by not allocating PASID tables.
Signed-off-by: Sohil Mehta
---
drivers/iommu/intel-svm.c | 4
include/linux/intel-iommu.h | 1 +
2 files chang
Add a check to verify IOMMU 1GB page support. If the CPU supports 1GB
pages but the IOMMU does not support it then disable SVM by not
allocating PASID tables.
Signed-off-by: Sohil Mehta
---
drivers/iommu/intel-svm.c | 4
include/linux/intel-iommu.h | 1 +
2 files changed, 5 insertions(+)
Hi Simon,
Commit
26c31cc8c397 ("arm64: dts: renesas: r8a7795: add usb3_phy node")
is missing a Signed-off-by from its committer.
--
Cheers,
Stephen Rothwell
On 20.12.2017 21:01, Thierry Reding wrote:
> On Wed, Dec 20, 2017 at 06:46:11PM +0300, Dmitry Osipenko wrote:
>> Commit 7772fdaef939 ("drm/tegra: Support ARGB and ABGR formats") broke
>> DRM's MODE_ADDFB IOCTL on Tegra20/30, because IOCTL uses XRGB format if
>> requested FB depth is 24bpp. As a res
On Tue, Dec 19, 2017 at 11:00 PM, Philippe Ombredanne
wrote:
> Andrey,
>
> On Wed, Dec 20, 2017 at 5:00 AM, Andrey Smirnov
> wrote:
>> Add a driver for RAVE Supervisory Processor, an MCU implementing
>> various bits of housekeeping functionality (watchdoging, backlight
>> control, LED control, et
Each crypto algorithm "cra_name" can have multiple implementation called
"cra_driver_name".
If two different implementation have the same cra_driver_name, nothing
can easily differentiate them.
Furthermore the mechanism for getting a crypto algorithm with its
implementation name (crypto_alg_match()
Hello
This patch is a try to implement a generic crypto driver statistics.
The goal is to have an "ifconfig" for crypto device.
Some driver tried to implement this via a debugfs interface.
My proposed way is to embed this in the crypto framework by registering
a /sys/kernel/crypto tree and creat
Add an example tool for getting easily crypto statistics.
Signed-off-by: Corentin Labbe
---
tools/crypto/cryptostat | 40
1 file changed, 40 insertions(+)
create mode 100755 tools/crypto/cryptostat
diff --git a/tools/crypto/cryptostat b/tools/crypto/cry
This patch implement a generic way to get statistics about all crypto
usages.
Signed-off-by: Corentin Labbe
---
crypto/Kconfig | 11 +++
crypto/ahash.c | 18 +
crypto/algapi.c| 186 +
crypto/rng.c
On 12/14/2017 10:34 PM, Haiyue Wang wrote:
This patch adds a simple device driver to expose the KCS interface on
Aspeed SOCs (AST2400 and AST2500) as a character device. Such SOCs are
commonly used as BMCs (BaseBoard Management Controllers) and this driver
implements the BMC side of the KCS inter
It is possible for a device to stop using buffers without pushing them
back to the driver. This is the case for example with the 9p virtio
device: if the driver flushes an in-flight request, the 9p specification
specification [*] mandates the server to "to purge the pending response".
The reply to
On Wed, Dec 20, 2017 at 11:37 AM, Tejun Heo wrote:
> Hello, Shakeel.
>
> On Tue, Dec 19, 2017 at 02:39:19PM -0800, Shakeel Butt wrote:
>> Suppose a user wants to run multiple instances of a specific job on
>> different datacenters and s/he has budget of 100MiB for each instance.
>> The instances a
Remove FSF address otherwise checkpatch will flag my next patch.
Signed-off-by: Cheah Kok Cheong
---
kernel/padata.c | 4
1 file changed, 4 deletions(-)
diff --git a/kernel/padata.c b/kernel/padata.c
index 57c0074..9d91909 100644
--- a/kernel/padata.c
+++ b/kernel/padata.c
@@ -14,10 +14,6
It is already included in module.h, see
commit f50169324df4 ("module.h: split out the EXPORT_SYMBOL into export.h")
for their relationship.
Signed-off-by: Cheah Kok Cheong
---
kernel/padata.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/kernel/padata.c b/kernel/padata.c
index 9d91909..e265
Hi Bart,
On 12/20, Bart Van Assche wrote:
> On Wed, 2017-12-20 at 11:16 -0800, Jaegeuk Kim wrote:
> > From: Jaegeuk Kim
>
> Hello Jaegeuk,
>
> For future patch series submissions, please include a cover letter that
> explains
> the purpose of the patch series and please also document the chang
On Wed, Dec 20, 2017 at 06:46:10PM +0300, Dmitry Osipenko wrote:
> HW reset isn't actually broken on Tegra20, but there is a dependency on
> first display controller to be taken out of reset for the second to be
> enabled successfully.
>
> Signed-off-by: Dmitry Osipenko
> ---
>
> Change log:
>
On Wed, Dec 20, 2017 at 11:01:49PM +0300, Dmitry Osipenko wrote:
> On 20.12.2017 21:01, Thierry Reding wrote:
> > On Wed, Dec 20, 2017 at 06:46:11PM +0300, Dmitry Osipenko wrote:
> >> Commit 7772fdaef939 ("drm/tegra: Support ARGB and ABGR formats") broke
> >> DRM's MODE_ADDFB IOCTL on Tegra20/30, b
On Wed, Dec 20, 2017 at 06:46:13PM +0300, Dmitry Osipenko wrote:
> iommu_map_sg() doesn't return a error value, but a size of the requested
> IOMMU mapping or zero in case of error.
>
> Signed-off-by: Dmitry Osipenko
> ---
> drivers/gpu/drm/tegra/gem.c | 15 +++
> 1 file changed, 7 i
On Wed, Dec 20, 2017 at 06:46:14PM +0300, Dmitry Osipenko wrote:
> host1x_syncpt_wait() takes timeout value in jiffies, but DRM passes it in
> milliseconds.
>
> Signed-off-by: Dmitry Osipenko
> ---
> drivers/gpu/drm/tegra/drm.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
Applied,
On Wed, Dec 20, 2017 at 06:46:12PM +0300, Dmitry Osipenko wrote:
> Older Tegra's do not support RGBA format for the cursor, but instead
> overlay plane could be used for it. Since there is no much use for the
> overlays on a regular desktop and HW-accelerated cursor is much nicer
> than the jerky S
Bpftool determines it's own version based on the kernel
version, which is picked from the linux/version.h header.
It's strange to use the version of the installed kernel
headers, and makes much more sense to use the version
of the actual source tree, where bpftool sources are.
This patch adds $(s
On Wed, Dec 20, 2017 at 9:15 PM, Cheah Kok Cheong wrote:
> Remove FSF address otherwise checkpatch will flag my next patch.
>
> Signed-off-by: Cheah Kok Cheong
> ---
> kernel/padata.c | 4
> 1 file changed, 4 deletions(-)
>
> diff --git a/kernel/padata.c b/kernel/padata.c
> index 57c0074..9
On 12/20/2017 10:19 AM, Matthew Wilcox wrote:
> I don't know what the right interface is, but my laptop has a set of
> /sys/devices/system/memory/memoryN/ directories. Perhaps this is the
> right place to expose write_bw (etc).
Those directories are already too redundant and wasteful. I think we
On 12/20/17 12:19 PM, Roman Gushchin wrote:
Bpftool determines it's own version based on the kernel
version, which is picked from the linux/version.h header.
It's strange to use the version of the installed kernel
headers, and makes much more sense to use the version
of the actual source tree,
On Wed, Dec 20, 2017 at 12:15 PM, Shakeel Butt wrote:
> On Wed, Dec 20, 2017 at 11:37 AM, Tejun Heo wrote:
>> Hello, Shakeel.
>>
>> On Tue, Dec 19, 2017 at 02:39:19PM -0800, Shakeel Butt wrote:
>>> Suppose a user wants to run multiple instances of a specific job on
>>> different datacenters and s
://lkml.org/lkml/2017/12/14/736
Suggested-by: Nicholas Mc Guire
Suggested-by: Masahiro Yamada
Signed-off-by: Lukas Bulwahn
---
compile tested on top of next-20171220 with clang and gcc
scripts/basic/fixdep.c | 11 +--
1 file changed, 5 insertions(+), 6 deletions(-)
diff --git a/scripts/basic
On 20.12.2017 23:19, Thierry Reding wrote:
> On Wed, Dec 20, 2017 at 06:46:12PM +0300, Dmitry Osipenko wrote:
>> Older Tegra's do not support RGBA format for the cursor, but instead
>> overlay plane could be used for it. Since there is no much use for the
>> overlays on a regular desktop and HW-acc
On Wed, 20 Dec 2017 20:19:43 +, Roman Gushchin wrote:
> Bpftool determines it's own version based on the kernel
> version, which is picked from the linux/version.h header.
>
> It's strange to use the version of the installed kernel
> headers, and makes much more sense to use the version
> of t
Hello Tejun,
At some point, I'd like to add some details about cgroups v2 "thread
mode" to the cgroup(7) manual page. I think I understand most of the
details by now, but there's one question I still can't work out an
answer to: why does the "domain invalid" cgroup type exist?
I did find the July
On 12/20/2017 01:24 PM, Michael Turquette wrote:
Quoting David Lechner (2017-12-20 10:53:27)
On 12/19/2017 04:29 PM, Michael Turquette wrote:
Hi David,
Quoting David Lechner (2017-12-15 08:29:56)
On 12/12/2017 10:14 PM, David Lechner wrote:
On 12/12/2017 05:43 PM, David Lechner wrote:
If cl
Let's avoid BUG_ON during fill_super, when on-disk was totall corrupted.
Signed-off-by: Jaegeuk Kim
---
fs/f2fs/segment.c | 16
fs/f2fs/segment.h | 22 ++
2 files changed, 30 insertions(+), 8 deletions(-)
diff --git a/fs/f2fs/segment.c b/fs/f2fs/segment.c
in
Dear user
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are currently running at 20.9 GB, you cannot send or receive new messages until
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Everyone:
This patch series is v16 of the driver for supervisory processor found
on RAVE series of devices from ZII. Supervisory processor is a PIC
microcontroller connected to various electrical subsystems on RAVE
devices whose firmware implements protocol to command/qery them.
NOTE:
* This dr
Add a driver for RAVE Supervisory Processor, an MCU implementing
various bits of housekeeping functionality (watchdoging, backlight
control, LED control, etc) on RAVE family of products by Zodiac
Inflight Innovations.
This driver implementes core MFD/serdev device as well as
communication subrouti
This driver provides access to RAVE SP watchdog functionality.
Cc: linux-kernel@vger.kernel.org
Cc: linux-watch...@vger.kernel.org
Cc: cphe...@gmail.com
Cc: Lucas Stach
Cc: Nikita Yushchenko
Cc: Lee Jones
Cc: Greg Kroah-Hartman
Cc: Pavel Machek
Cc: Andy Shevchenko
Cc: Guenter Roeck
Cc: Rob
Using devres infrastructure it is possible to write a serdev driver
that doesn't have any code that needs to be called as a part of
.remove. Add code to make .remove optional.
Cc: linux-kernel@vger.kernel.org
Cc: linux-ser...@vger.kernel.org
Cc: Rob Herring
Cc: cphe...@gmail.com
Cc: Guenter Roeck
Add Device Tree bindings for RAVE SP watchdog drvier - an MFD cell of
parent RAVE SP driver (documented in
Documentation/devicetree/bindings/mfd/zii,rave-sp.txt).
Cc: linux-kernel@vger.kernel.org
Cc: devicet...@vger.kernel.org
Cc: linux-watch...@vger.kernel.org
Cc: cphe...@gmail.com
Cc: Lucas Stac
Add code implementing managed version of serdev_device_open() for
serdev device drivers that "open" the device during driver's lifecycle
only once (e.g. opened in .probe() and closed in .remove()).
Cc: linux-kernel@vger.kernel.org
Cc: linux-ser...@vger.kernel.org
Cc: Rob Herring
Cc: cphe...@gmail
While testing other changes, I discovered that gcc-7.2.1 produces badly
optimized code for aes_encrypt/aes_decrypt. This is especially true when
CONFIG_UBSAN_SANITIZE_ALL is enabled, where it leads to extremely
large stack usage that in turn might cause kernel stack overflows:
crypto/aes_generic.c
On Wed, Dec 20, 2017 at 12:29:21PM -0800, Jakub Kicinski wrote:
> On Wed, 20 Dec 2017 20:19:43 +, Roman Gushchin wrote:
> > Bpftool determines it's own version based on the kernel
> > version, which is picked from the linux/version.h header.
> >
> > It's strange to use the version of the insta
On Tue, Dec 19, 2017 at 03:15:39PM +0530, Kishon Vijay Abraham I wrote:
> DRA72 uses USB3 PHY for the 2nd lane of PCIE. Add dt bindings property
> to indicate if the USB3 PHY should be used for 2nd lane of PCIe.
>
> Signed-off-by: Kishon Vijay Abraham I
> ---
> Documentation/devicetree/bindings/
On Wed, Dec 20, 2017 at 12:26:30PM -0800, Yonghong Song wrote:
>
>
> On 12/20/17 12:19 PM, Roman Gushchin wrote:
> > Bpftool determines it's own version based on the kernel
> > version, which is picked from the linux/version.h header.
> >
> > It's strange to use the version of the installed kern
DEVICE_ATTR is a declaration macro that has a few alternate and
preferred forms like DEVICE_ATTR_RW, DEVICE_ATTR_RO, and DEVICE_ATTR.
As well, many uses of DEVICE_ATTR could use the preferred forms when
the show or store functions are also named in a regular form.
Suggest the preferred forms when
On 20.12.2017 23:16, Thierry Reding wrote:
> On Wed, Dec 20, 2017 at 11:01:49PM +0300, Dmitry Osipenko wrote:
>> On 20.12.2017 21:01, Thierry Reding wrote:
>>> On Wed, Dec 20, 2017 at 06:46:11PM +0300, Dmitry Osipenko wrote:
Commit 7772fdaef939 ("drm/tegra: Support ARGB and ABGR formats") brok
On Wed, 2017-12-13 at 08:21 +0100, Peter Zijlstra wrote:
> On Tue, Dec 12, 2017 at 03:08:00PM -0800, Megha Dey wrote:
> > >
> > > There's work on the way to allow multiple HW PMUs. You'll either have to
> > > wait for that or help in making that happen. What you do not do is
> > > silently hack ar
On Tue, Dec 19, 2017 at 09:24:50PM +0530, Sricharan R wrote:
> From: Stephen Boyd
>
> Adds bindings document for qcom,hfpll instantiated within
> the Krait processor subsystem as separate register region.
>
> Signed-off-by: Stephen Boyd
> ---
> .../devicetree/bindings/clock/qcom,hfpll.txt
On Tue, Dec 19, 2017 at 09:24:55PM +0530, Sricharan R wrote:
> From: Stephen Boyd
>
> The ACC and GCC regions present in KPSSv1 contain registers to
> control clocks and power to each Krait CPU and L2. Documenting
> the bindings here.
>
> Signed-off-by: Stephen Boyd
> ---
> .../devicetree/bind
On Wed, Dec 20, 2017 at 10:19:37AM -0800, Matthew Wilcox wrote:
> On Mon, Dec 18, 2017 at 01:35:47PM -0700, Ross Zwisler wrote:
> > What I'm hoping to do with this series is to just provide a sysfs
> > representation of the HMAT so that applications can know which NUMA nodes to
> > select with exis
On 20 December 2017 at 20:52, Arnd Bergmann wrote:
> While testing other changes, I discovered that gcc-7.2.1 produces badly
> optimized code for aes_encrypt/aes_decrypt. This is especially true when
> CONFIG_UBSAN_SANITIZE_ALL is enabled, where it leads to extremely
> large stack usage that in tu
On Tue, Dec 19, 2017 at 09:24:57PM +0530, Sricharan R wrote:
> From: Stephen Boyd
>
> The Krait clock controller controls the krait CPU and the L2 clocks
> consisting a primary mux and secondary mux. Add document for that.
>
> Signed-off-by: Stephen Boyd
> ---
> .../devicetree/bindings/clock/q
On Wed, Dec 20, 2017 at 12:22:21PM -0800, Dave Hansen wrote:
> On 12/20/2017 10:19 AM, Matthew Wilcox wrote:
> > I don't know what the right interface is, but my laptop has a set of
> > /sys/devices/system/memory/memoryN/ directories. Perhaps this is the
> > right place to expose write_bw (etc).
>
On Wed, Dec 20, 2017 at 09:20:48PM +0100, Philippe Ombredanne wrote:
> On Wed, Dec 20, 2017 at 9:15 PM, Cheah Kok Cheong wrote:
> > Remove FSF address otherwise checkpatch will flag my next patch.
> >
> > Signed-off-by: Cheah Kok Cheong
> > ---
> > kernel/padata.c | 4
> > 1 file changed, 4
On 20/12/2017 20:40, Jim Mattson wrote:
> This doesn't look right to me. Without APIC-register virtualization,
> the only X2APIC MSR intercept that should be disabled is TPR.
Of course... The bitmap that has to be outside the "if" is
*_x2apic_apicv, not *_x2apic. I sent the wrong version of the
On Wed, Dec 20, 2017 at 11:55:33AM +0530, Sricharan R wrote:
> Hi Viresh,
>
> On 12/20/2017 8:56 AM, Viresh Kumar wrote:
> > On 19-12-17, 21:25, Sricharan R wrote:
> >> + cpu@0 {
> >> + compatible = "qcom,krait";
> >> + enable-method = "qcom,kpss-acc-v1";
> >> + device_
> Some observations:
>
> o Your patch fixes no bug nor replaces any depreciated feature.
How do you think about information from the section “14) Allocating memory”
in the document “coding-style.rst” for the shown source code transformation?
> o There will be no functional change; …
Yes. - T
On Tue, Dec 19 2017, Jan Kara wrote:
> On Fri 08-12-17 13:17:31, NeilBrown wrote:
>> On Thu, Dec 07 2017, Amir Goldstein wrote:
>>
>> > On Thu, Dec 7, 2017 at 5:20 AM, NeilBrown wrote:
>> >> On Wed, Dec 06 2017, Linus Torvalds wrote:
>> >>
>> >>> On Thu, Nov 30, 2017 at 12:56 PM, NeilBrown wrot
On Wed, Dec 20, 2017 at 01:16:49PM -0800, Matthew Wilcox wrote:
> On Wed, Dec 20, 2017 at 12:22:21PM -0800, Dave Hansen wrote:
> > On 12/20/2017 10:19 AM, Matthew Wilcox wrote:
> > > I don't know what the right interface is, but my laptop has a set of
> > > /sys/devices/system/memory/memoryN/ direc
On Tue, Dec 19, 2017 at 11:22:40AM -0800, Florian Fainelli wrote:
> Correct the Device Tree bindings for the HIF_CPUBIUCTRL node whose
> compatible string is actually brcm,bcm-cpu-biu-ctrl. Also
> document in the binding the fallback property
> ("brcm,brcmstb-cpu-biu-ctrl") and update the example a
On 18/12/2017 at 12:51:29 +0100, linux-kernel-...@beckhoff.com wrote:
> From: Patrick Bruenn
>
> Neither rtc-imxdi, rtc-mxc nor rtc-snvs are compatible with i.MX53.
>
> This is driver enables support for the low power domain SRTC features:
> - 32-bit MSB of non-rollover time counter
> - 32-bit a
On Wed, Dec 20, 2017 at 06:10:11PM +, Song Liu wrote:
> I think there is one more thing to change:
OK, folded that too; it should all be at:
git://git.kernel.org/pub/scm/linux/kernel/git/peterz/queue.git perf/core
Can you verify it all looks/works right?
On Wed, Dec 20, 2017 at 10:14 PM, Ard Biesheuvel
wrote:
> On 20 December 2017 at 20:52, Arnd Bergmann wrote:
>
> You can use the tcrypt.ko module to benchmark AES.
>
> modprobe tcrypt mode=200 sec=1
Ok, that's what I was looking for. I don't think I'll have time to
analyze this before
my Christm
On 12/20/2017 12:52 PM, Michael S. Tsirkin wrote:
> On Wed, Dec 20, 2017 at 12:07:55PM -0500, Jason Baron wrote:
>>
>>
>> On 12/20/2017 09:57 AM, Michael S. Tsirkin wrote:
>>> On Thu, Dec 14, 2017 at 02:33:53PM -0500, Jason Baron wrote:
If the hypervisor exports the link and duplex speed, le
On Wed, Dec 20, 2017 at 11:42:51AM -0800, kan.li...@linux.intel.com wrote:
> From: Kan Liang
>
> The userspace RDPMC usage never works for large PEBS since the large
> PEBS is introduced by
> commit b8241d20699e ("perf/x86/intel: Implement batched PEBS interrupt
> handling (large PEBS interrupt t
On Tue, Dec 19, 2017 at 03:05:23PM -0600, kevan...@ksu.edu wrote:
> Allwinner a83t has a 1 KB sid block with efuse for security rootkey and
> thermal calibration data, add node to describe it.
>
> a83t-sid is not currently supported by nvmem/sunxi-sid, but it is
> supported in an external driver f
On Wed, Dec 20, 2017 at 01:53:10PM +1030, Joel Stanley wrote:
> These are used to by the device tree to map pin numbers to constants
> required by the GPIO bindings.
>
> Signed-off-by: Joel Stanley
> --
> v3:
> - Remove dtsi includes from this patch, they will come later
> ---
> include/dt-bind
On Wed, Dec 20, 2017 at 09:52:05PM +0100, Arnd Bergmann wrote:
> diff --git a/crypto/aes_generic.c b/crypto/aes_generic.c
> index ca554d57d01e..35f973ba9878 100644
> --- a/crypto/aes_generic.c
> +++ b/crypto/aes_generic.c
> @@ -1331,6 +1331,20 @@ EXPORT_SYMBOL_GPL(crypto_aes_set_key);
> f_rl(
On Wed, Dec 20, 2017 at 11:30:07AM +0100, Hans de Goede wrote:
> Hi Andy, et al,
>
> Here are 2 patches to add entries for 2 more Chuwi tablet models to
> silead_dmi.c. Note that these are for 2 different tablets, even though
> the entries look similar.
>
> I've based this series on top of the re
On Wed, Dec 20, 2017 at 09:26:32AM +0100, Bartosz Golaszewski wrote:
> AT24 EEPROMs have a write-protect pin, which - when pulled high -
> inhibits writes to the upper quadrant of memory (although it has been
> observed that on some chips it disables writing to the entire memory
> range).
>
> On s
On 12/20/2017 02:33 PM, David Lechner wrote:
So, as you can see, we get 4 warnings here. There is no problem with any
clock provider or consumer (as far as I can tell). The bug here is that
spin_trylock_irqsave() always returns true on non-SMP systems, which
messes up the reference counting.
Andrey,
On Wed, Dec 20, 2017 at 9:45 PM, Andrey Smirnov
wrote:
> Everyone:
>
> This patch series is v16 of the driver for supervisory processor found
> on RAVE series of devices from ZII. Supervisory processor is a PIC
> microcontroller connected to various electrical subsystems on RAVE
> devices
On Wed, 20 Dec 2017 20:53:41 +, Roman Gushchin wrote:
> On Wed, Dec 20, 2017 at 12:29:21PM -0800, Jakub Kicinski wrote:
> > On Wed, 20 Dec 2017 20:19:43 +, Roman Gushchin wrote:
> > > Bpftool determines it's own version based on the kernel
> > > version, which is picked from the linux/ver
From: Thomas Gleixner
In order to sanitize the LDT initialization on x86 arch_dup_mmap() must be
allowed to fail. Fix up all instances.
Signed-off-by: Thomas Gleixner
Signed-off-by: Peter Zijlstra (Intel)
Cc: Juergen Gross
Cc: Eduardo Valentin
Cc: Denys Vlasenko
Cc: aligu...@amazon.com
Cc:
From: Peter Zijlstra
Since uv_flush_tlb_others() implements flush_tlb_others() which is
about flushing user mappings, we should use __flush_tlb_single(),
which too is about flushing user mappings.
Signed-off-by: Peter Zijlstra (Intel)
Signed-off-by: Ingo Molnar
Signed-off-by: Thomas Gleixner
From: Peter Zijlstra
__flush_tlb_single() is for user mappings, __flush_tlb_one() for
kernel mappings.
Signed-off-by: Peter Zijlstra (Intel)
Signed-off-by: Ingo Molnar
Signed-off-by: Thomas Gleixner
Cc: Andy Lutomirski
Cc: Boris Ostrovsky
Cc: Borislav Petkov
Cc: Brian Gerst
Cc: Dave Hanse
From: Peter Zijlstra
Unclutter tlbflush.h a little.
Signed-off-by: Peter Zijlstra (Intel)
Signed-off-by: Ingo Molnar
Cc: Andy Lutomirski
Cc: Boris Ostrovsky
Cc: Borislav Petkov
Cc: Brian Gerst
Cc: Dave Hansen
Cc: David Laight
Cc: Denys Vlasenko
Cc: Eduardo Valentin
Cc: Greg KH
Cc: H.
From: Thomas Gleixner
Add two debugfs files which allow to dump the pagetable of the current
task.
current_kernel dumps the regular page table. This is the page table which
is normally shared between kernel and user space. If kernel page table
isolation is enabled this is the kernel space mappin
From: Dave Hansen
If changing the page tables in such a way that an invalidation of all
contexts (aka. PCIDs / ASIDs) is required, they can be actively invalidated
by:
1. INVPCID for each PCID (works for single pages too).
2. Load CR3 with each PCID without the NOFLUSH bit set
3. Load CR3 w
From: Peter Zijlstra
Most NMI/paranoid exceptions will not in fact change pagetables and would
thus not require TLB flushing, however RESTORE_CR3 uses flushing CR3
writes.
Restores to kernel PCIDs can be NOFLUSH, because we explicitly flush the
kernel mappings and now that we track which user PC
From: Thomas Gleixner
Now that the LDT mapping is in a known area when PAGE_TABLE_ISOLATION is
enabled its a primary target for attacks, if a user space interface fails
to validate a write address correctly. That can never happen, right?
The SDM states:
If the segment descriptors in the GDT
From: Dave Hansen
Finally allow CONFIG_PAGE_TABLE_ISOLATION to be enabled.
PARAVIRT generally requires that the kernel not manage its own page tables.
It also means that the hypervisor and kernel must agree wholeheartedly
about what format the page tables are in and what they contain.
PAGE_TABLE
struct proc_dir_entry became bit messy over years:
* move 16-bit ->mode_t before namelen to get rid of padding
* make ->in_use first field: it seems to be most used resulting in
smaller code on x86_64 (defconfig):
add/remove: 0/0 grow/shrink: 7/13 up/down: 24/-67 (-43)
Function
From: Andy Lutomirski
With PTI enabled, the LDT must be mapped in the usermode tables somewhere.
The LDT is per process, i.e. per mm.
An earlier approach mapped the LDT on context switch into a fixmap area,
but that's a big overhead and exhausted the fixmap space when NR_CPUS got
big.
Take adva
From: Andy Lutomirski
Share the cpu entry area so the user space and kernel space page tables
have the same P4D page.
Signed-off-by: Andy Lutomirski
Signed-off-by: Ingo Molnar
Signed-off-by: Thomas Gleixner
Cc: Boris Ostrovsky
Cc: Borislav Petkov
Cc: Brian Gerst
Cc: Dave Hansen
Cc: David
From: Thomas Gleixner
ptdump_walk_pgd_level_checkwx() checks the kernel page table for WX pages,
but does not check the PAGE_TABLE_ISOLATION user space page table.
Restructure the code so that dmesg output is selected by an explicit
argument and not implicit via checking the pgd argument for !NU
From: Dave Hansen
Add the pagetable helper functions do manage the separate user space page
tables.
[ tglx: Split out from the big combo kaiser patch. Folded Andys
simplification and made it out of line as Boris suggested ]
Signed-off-by: Dave Hansen
Signed-off-by: Thomas Gleixner
Sig
From: Vlastimil Babka
CONFIG_PAGE_TABLE_ISOLATION is relatively new and intrusive feature that may
still have some corner cases which could take some time to manifest and be
fixed. It would be useful to have Oops messages indicate whether it was
enabled for building the kernel, and whether it was
From: Dave Hansen
This uses INVPCID to shoot down individual lines of the user mapping
instead of marking the entire user map as invalid. This
could/might/possibly be faster.
This for sure needs tlb_single_page_flush_ceiling to be redetermined;
esp. since INVPCID is _slow_.
A detailed performan
The upcoming support for dumping the kernel and the user space page tables
of the current process would create more random files in the top level
debugfs directory.
Add a page table directory and move the existing file to it.
Signed-off-by: Borislav Petkov
Signed-off-by: Ingo Molnar
Signed-off-
From: Peter Zijlstra
Ideally we'd also use sparse to enforce this separation so it becomes much
more difficult to mess up.
Signed-off-by: Peter Zijlstra (Intel)
Signed-off-by: Ingo Molnar
Signed-off-by: Thomas Gleixner
Cc: Andy Lutomirski
Cc: Boris Ostrovsky
Cc: Borislav Petkov
Cc: Brian G
From: Dave Hansen
With PAGE_TABLE_ISOLATION the user portion of the kernel page tables is
poisoned with the NX bit so if the entry code exits with the kernel page
tables selected in CR3, userspace crashes.
But doing so trips the p4d/pgd_bad() checks. Make sure it does not do
that.
Signed-off-b
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