On Mon, Nov 20, 2017 at 01:18:38PM -0500, Nicolas Pitre wrote:
> On Sun, 19 Nov 2017, Guenter Roeck wrote:
>
> > On 11/19/2017 08:08 PM, Nicolas Pitre wrote:
> > > On Sun, 19 Nov 2017, Guenter Roeck wrote:
> > > > On 11/19/2017 12:36 PM, Nicolas Pitre wrote:
> > > > > On Sat, 18 Nov 2017, Guenter
On Tue, Nov 14, 2017 at 06:36:26PM +0100, Geert Uytterhoeven wrote:
> For the common cases where 1000 is a multiple of HZ, or HZ is a multiple
> of 1000, jiffies_to_msecs() never returns zero when passed a non-zero
> time period.
>
> However, if HZ > 1000 and not an integer multiple of 1000 (e.g.
On Sun, Nov 19, 2017 at 09:28:49PM +, Al Viro wrote:
> On Sun, Nov 19, 2017 at 03:02:10PM -0500, Tim Hansen wrote:
> > Adds hlist_first_rcu and hlist_next_rcu for safe access
> > to the hlist in seq_hlist_next_rcu.
> >
> > Found on linux-next branch, tag next-20171117 with sparse.
>
> Frankly
These were left over from an earlier version of the port.
Signed-off-by: Palmer Dabbelt
---
arch/riscv/kernel/vdso/vdso.lds.S | 2 --
1 file changed, 2 deletions(-)
diff --git a/arch/riscv/kernel/vdso/vdso.lds.S
b/arch/riscv/kernel/vdso/vdso.lds.S
index 8c9dce95c11d..3ac08eebd11d 100644
--- a/
From: Andrew Waterman
The RISC-V ISA allows for instruction caches that are not coherent WRT
stores, even on a single hart. As a result, we need to explicitly flush
the instruction cache whenever marking a dirty page as executable in
order to preserve the correct system behavior.
Local instruct
From: Andrew Waterman
Despite RISC-V having a direct 'fence.i' instruction available to
userspace (which we can't trap!), that's not actually viable when
running on Linux because the kernel might schedule a process on another
hart. There is no way for userspace to handle this without invoking th
From: Andrew Waterman
For now these are just placeholders that execute the syscall. We will
later optimize them to avoid kernel crossings, but we'd like to have the
VDSO entries from the first released kernel version to make the ABI
simpler.
Signed-off-by: Andrew Waterman
Signed-off-by: Palmer
On Thu, Nov 16, 2017 at 03:11:50PM +0100, Enric Balletbo i Serra wrote:
> Setting use-linear-interpolation in the dts will allow you to have linear
> interpolation between values of brightness-levels.
>
> There are now 256 between each of the values of brightness-levels. If
> something is requeste
This patch set contains all the user-visible ABI changes that we currently know
about. There might be a few more as we get through the glibc upstreaming
process, though. Most of the changes are pretty minor:
* Some VDSO symbols that weren't defined were versioned, which doesn't make any
sense.
On Fri, Nov 17, 2017 at 05:24:30PM +0800, Xu YiPing wrote:
> From: Leo Yan
>
> Introduce a binding for the Hi3660 mailbox controller, the mailbox is
> used within application processor (AP), communication processor (CP),
> HIFI and MCU, etc.
>
> Signed-off-by: Leo Yan
> ---
> .../bindings/mail
On Sat, Nov 18, 2017 at 10:37:55AM -0800, Linus Torvalds wrote:
> On Sat, Nov 18, 2017 at 10:09 AM, Andy Shevchenko
> wrote:
> >
> > Here is the collected material against Platform Drivers x86 subsystem.
> > It's rather bit busy cycle for PDx86, mostly due to Dell SMBIOS driver
> > activity.
>
>
AC'97 interface RXD and TXC pins are only used as SoC inputs, let's disable
pad drivers for them so we will be protected if, for example, TCLKDIR is
set by mistake in AUDMUX and causes TXC pin to be configured as an output.
This also changes pull direction on these pins from pull-up to pull-down
t
On 11/20, Chunyan Zhang wrote:
> From: Cai Li
>
> In some cases the clock parent would be set NULL when doing re-parent,
> it will cause a NULL pointer accessing if clk_set trace event is enabled,
> since the trace event function would not check the input parameter.
>
> Signed-off-by: Cai Li
>
When a command is added to the host's error handler command queue, there is a
chance that the error handler will not be woken up. This can happen when one
CPU is running scsi_eh_scmd_add() at the same time as another CPU is running
scsi_device_unbusy() for a different command on the same host.
>From 958f8db089f4b89407fc4b89bccd3eaef585aa96 Mon Sep 17 00:00:00 2001
From: Sukadev Bhattiprolu
Date: Mon, 20 Nov 2017 12:53:15 -0600
Subject: [PATCH 1/1] powerpc/vas, export chip_to_vas_id()
Export the symbol chip_to_vas_id() to fix a build failure when
CONFIG_CRYPTO_DEV_NX_COMPRESS_POWERNV=m.
On Mon, 20 Nov 2017 10:40:40 -0800
Matthew Wilcox wrote:
> > ifeq ($(KBUILD_ENABLE_EXTRA_GCC_CHECKS),)
> > cmd_checkdoc = $(srctree)/scripts/kernel-doc -none $< ;
> > endif
>
> Thanks! v2 below. Jon, could you apply?
Done, thanks.
jon
On Mon, Nov 20, 2017 at 10:21:24AM -0800, Guenter Roeck wrote:
> On Sun, Nov 19, 2017 at 03:59:34PM +0100, Greg Kroah-Hartman wrote:
> > This is the start of the stable review cycle for the 4.14.1 release.
> > There are 31 patches in this series, all will be posted as a response
> > to this one. I
On Mon, Nov 20, 2017 at 08:25:14AM -0800, Guenter Roeck wrote:
> On Mon, Nov 20, 2017 at 03:48:18PM +0100, Greg Kroah-Hartman wrote:
> > On Mon, Nov 20, 2017 at 06:06:57AM -0800, Guenter Roeck wrote:
> > > On 11/19/2017 06:29 AM, Greg Kroah-Hartman wrote:
> > > > This is the start of the stable rev
On Mon, Nov 20, 2017 at 08:31:47AM -0800, Guenter Roeck wrote:
> On Sun, Nov 19, 2017 at 03:32:08PM +0100, Greg Kroah-Hartman wrote:
> > This is the start of the stable review cycle for the 4.4.100 release.
> > There are 59 patches in this series, all will be posted as a response
> > to this one.
On Mon, Nov 20, 2017 at 06:05:55PM +, Will Deacon wrote:
> Please don't confuse this with a reluctance to support clang; I'm keen to
> see that supported,
As an aside; as long as clang doesn't do asm-goto and asm-flag-output
(as examples of features that clang lacks and developers have at tim
On Mon, Nov 20, 2017 at 11:52:32AM +0530, Naresh Kamboju wrote:
> On 19 November 2017 at 20:08, Greg Kroah-Hartman
> wrote:
> > This is the start of the stable review cycle for the 4.9.64 release.
> > There are 72 patches in this series, all will be posted as a response
> > to this one. If anyone
On 11/20, Bjorn Andersson wrote:
> Not all instances of the SDCC core supports changing signal voltage and
> as such will not generate a power interrupt when the software attempts
> to change the voltage. This results in probing the eMMC on some devices
> to take over 2 minutes.
>
> Check that the
On Sun, Nov 19, 2017 at 12:48:51PM -0700, Nathan Chancellor wrote:
> On Sun, Nov 19, 2017 at 03:32:08PM +0100, Greg Kroah-Hartman wrote:
>
> Merged, compiled, and flashed onto my Pixel 2 XL. No initial issues
> noticed in either dmesg or general usage.
Wonderful, thanks for testing.
Just a side
On Mon, Nov 20, 2017 at 06:05:55PM +, Will Deacon wrote:
> This is a thorny issue, but RCU (specifically rcu_dereference but probably
> also some READ_ONCEs) relies on being able to utilise syntactic dependency
> chains to order local accesses to shared variables.
Well, we used to have READ_ON
On Mon, Nov 20, 2017 at 05:35:04PM +0100, Andrea Parri wrote:
> On Fri, Nov 17, 2017 at 07:27:46PM +0800, Boqun Feng wrote:
> > On Wed, Nov 15, 2017 at 08:37:49AM -0800, Paul E. McKenney wrote:
> > > On Tue, Nov 14, 2017 at 09:15:05AM -0800, Paul E. McKenney wrote:
> > > > On Tue, Nov 14, 2017 at 1
From: Romain Perier
Now that all the drivers use dma pool API, we can remove the macro
functions for PCI pool.
Signed-off-by: Romain Perier
Reviewed-by: Peter Senna Tschudin
---
include/linux/pci.h | 9 -
1 file changed, 9 deletions(-)
diff --git a/include/linux/pci.h b/include/linux
by the dma pool API
and remove the defines.
Changes in v15:
- Rebased series onto next-20171120
- Added patch 04/05 for mpt3sas scsi driver
Changes in v14:
- Rebased series onto next-20171018
- Rebased patch 03/05 on latest driver
Changes in v13:
- Rebased series onto next-20170906
- Added a new
From: Romain Perier
The PCI pool API is deprecated. This commit replaces the PCI pool old
API by the appropriate function with the DMA pool API.
Signed-off-by: Romain Perier
---
drivers/net/ethernet/huawei/hinic/hinic_hw_cmdq.c | 10 +-
drivers/net/ethernet/huawei/hinic/hinic_hw_cmdq.h
The PCI pool API is deprecated. This commit replaces the PCI pool old
API by the appropriate function with the DMA pool API.
Signed-off-by: Romain Perier
---
drivers/scsi/mpt3sas/mpt3sas_base.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/scsi/mpt3sas/
From: Romain Perier
The PCI pool API is deprecated. This commit replaces the PCI pool old
API by the appropriate function with the DMA pool API.
Signed-off-by: Romain Perier
Acked-by: Peter Senna Tschudin
Tested-by: Peter Senna Tschudin
---
drivers/block/DAC960.c | 38 ++-
On Mon, Nov 20, 2017 at 06:05:55PM +, Will Deacon wrote:
> Although the current direction of the C++ committee is to prefer
> that dependencies are explicitly "marked", this is not deemed to be
> acceptable for the kernel (in other words, everything is always considered
> "marked").
Yeah, that
From: Romain Perier
The PCI pool API is deprecated. This commit replaces the PCI pool old
API by the appropriate function with the DMA pool API.
Signed-off-by: Romain Perier
Acked-by: Peter Senna Tschudin
Acked-by: Jeff Kirsher
Tested-by: Peter Senna Tschudin
---
drivers/net/ethernet/intel/
In an attempt to make contiguous allocation routines more available to
drivers, I have been experimenting with code similar to that used by
alloc_gigantic_page(). While stressing this code with many other
allocations and frees in progress, I would sometimes notice large 'leaks'
of page ranges.
I
If the call __alloc_contig_migrate_range() in alloc_contig_range
returns -EBUSY, processing continues so that test_pages_isolated()
is called where there is a tracepoint to identify the busy pages.
However, it is possible for busy pages to become available between
the calls to these two routines.
On Mon, Nov 20, 2017 at 08:27:07PM +0100, Greg Kroah-Hartman wrote:
> On Sun, Nov 19, 2017 at 12:48:51PM -0700, Nathan Chancellor wrote:
> > On Sun, Nov 19, 2017 at 03:32:08PM +0100, Greg Kroah-Hartman wrote:
> >
> > Merged, compiled, and flashed onto my Pixel 2 XL. No initial issues
> > noticed i
On Mon, 20 Nov 2017, Mathieu Desnoyers wrote:
> - On Nov 20, 2017, at 12:48 PM, Thomas Gleixner t...@linutronix.de wrote:
> The use-case for 4k memcpy operation is a per-cpu ring buffer where
> the rseq fast-path does the following:
>
> - ring buffer push: in the rseq asm instruction sequence,
On Fri, Nov 17, 2017 at 05:30:48PM -0800, Kees Cook wrote:
> On Fri, Nov 3, 2017 at 5:26 AM, Andy Shevchenko
> wrote:
> > On Thu, Nov 2, 2017 at 9:55 PM, Kees Cook wrote:
> >> On Thu, Oct 5, 2017 at 1:41 AM, Andy Shevchenko
> >> wrote:
> >>> On Thu, Oct 5, 2017 at 3:54 AM, Kees Cook wrote:
> >>
On Sun, 19 Nov 2017 23:35:28 PST (-0800), j.neuschae...@gmx.net wrote:
Hi Palmer,
On Thu, Oct 05, 2017 at 11:16:33AM +0100, Mark Rutland wrote:
[...]
I would *strongly* recommend that from day one, you determine the SMP
bringup mechanism via an enable-method property, and document the
contract
On Mon, Nov 20, 2017 at 11:45 AM, Darren Hart wrote:
> On Fri, Nov 17, 2017 at 05:30:48PM -0800, Kees Cook wrote:
>> On Fri, Nov 3, 2017 at 5:26 AM, Andy Shevchenko
>> wrote:
>> > On Thu, Nov 2, 2017 at 9:55 PM, Kees Cook wrote:
>> >> On Thu, Oct 5, 2017 at 1:41 AM, Andy Shevchenko
>> >> wrote:
From: "Edward A. James"
This series adds two FSI-based device drivers; one for the SBEFIFO and one for
the On-Chip Controller (OCC).
IBM POWER9 processors contain some embedded hardware and software bits
collectively referred to as the self boot engine (SBE). One role of
the SBE is to act as a
From: "Edward A. James"
The OCC is a device embedded on a POWER processor that collects and
aggregates sensor data from the processor and system. The OCC can
provide the raw sensor data as well as perform thermal and power
management on the system.
This driver provides an atomic communications c
From: "Edward A. James"
Add a miscdevice for the occ to allow userspace access through standard
file operations.
Signed-off-by: Edward A. James
---
drivers/fsi/fsi-occ.c | 264 ++
1 file changed, 264 insertions(+)
diff --git a/drivers/fsi/fsi-oc
From: "Edward A. James"
Document the bindings for the P9 OCC device. OCC devices are accessed
through the SBEFIFO.
Signed-off-by: Edward A. James
---
Documentation/devicetree/bindings/fsi/ibm,p9-occ.txt | 18 ++
1 file changed, 18 insertions(+)
create mode 100644 Documentation
From: "Edward A. James"
IBM POWER9 processors contain some embedded hardware and software bits
collectively referred to as the self boot engine (SBE). One role of
the SBE is to act as a proxy that provides access to the registers of
the POWER chip from other (embedded) systems.
The POWER9 chip
From: "Edward A. James"
Add an in-kernel read/write API with exported functions. This is
necessary for other drivers which want to directly interact with the
OCC. Also add a child platform device node for the associated hwmon
device.
Signed-off-by: Edward A. James
---
drivers/fsi/fsi-occ.c |
From: "Edward A. James"
Add a miscdevice for the sbefifo to allow userspace access through
standard file operations.
Signed-off-by: Edward A. James
---
drivers/fsi/fsi-sbefifo.c | 355 ++
1 file changed, 355 insertions(+)
diff --git a/drivers/fsi/fs
On Mon, Nov 20, 2017 at 9:18 AM, Masahiro Yamada
wrote:
>
> I am unhappy about adding a new interface
> for each checker.
>
> The default of CHECK is "sparse", but
> users can override it to use another checker.
>
>
>
> As Decumentation/dev-tools/coccinelle.rst says,
> if you want to use coccinel
From: "Edward A. James"
Refactor the user interface of the SBEFIFO driver to allow for an
in-kernel read/write API. Add exported functions for other drivers to
call, and add an include file with those functions. Also parse the
device tree for child nodes and create child platform devices
accordin
From: "Edward A. James"
Document the bindings for the SBE CFAM device. SBE devices are
located on a CFAM off an FSI bus.
Signed-off-by: Edward A. James
---
.../devicetree/bindings/fsi/ibm,p9-sbefifo.txt | 35 ++
1 file changed, 35 insertions(+)
create mode 100644 Docum
Hi Johannes,
I tested with your patches but situation is still mostly the same.
Spend some time for debugging and found that the problem is squashfs
specific (probably some others fs's too).
The point is that iowait for squashfs reads will be awaited inside
squashfs readpage() callback.
Here
The RISC-V privileged ISA mandates the presence of an SBI, but there's
no reason not to put it in the device tree. This would allow us to
possibly remove the SBI later.
CC: Jonathan Neuschäfer
Signed-off-by: Palmer Dabbelt
---
.../devicetree/bindings/firmware/riscv.sbi.txt | 20 +
RISC-V doesn't currently specify a mechanism for enabling or disabling
CPUs. Instead, we assume that all CPUs are enabled on boot, and if
someone wants to save power we instead put a CPU to sleep via a WFI
loop.
This patch adds "enable-method" to the RISC-V CPU binding, which
currently only has t
Not all instances of the SDCC core supports changing signal voltage and
as such will not generate a power interrupt when the software attempts
to change the voltage. This results in probing the eMMC on some devices
to take over 2 minutes.
Check that the SWITCHABLE_SIGNALING_VOLTAGE bit in MCI_GENE
On Sun 19 Nov 13:35 PST 2017, Jacek Anaszewski wrote:
> Hi Bjorn,
>
> Thanks for the update.
>
> On 11/15/2017 08:13 AM, Bjorn Andersson wrote:
> > This adds the binding document describing the three hardware blocks
> > related to the Light Pulse Generator found in a wide range of Qualcomm
> > P
On Mon, Nov 20, 2017 at 01:55:35PM -0500, Tim Hansen wrote:
> On Sun, Nov 19, 2017 at 09:28:49PM +, Al Viro wrote:
> > On Sun, Nov 19, 2017 at 03:02:10PM -0500, Tim Hansen wrote:
> > > Adds hlist_first_rcu and hlist_next_rcu for safe access
> > > to the hlist in seq_hlist_next_rcu.
> > >
> > >
my name is Mrs. Alice Walton, a business woman an America Citizen and the
heiress to the fortune of Walmart stores, born October 7, 1949. I have a
mission for you worth $100,000,000.00(Hundred Million United State Dollars)
which I intend using for CHARITY
I have a confidential deal to discuss with you, but I want your consent
before I send details.
On Mon, Nov 20, 2017 at 12:48:35PM -0700, Jim Davis wrote:
>
> I'd be nice if people could just specify CHECK and CHECKFLAGS to run
> their favorite checker, but currently CHECKFLAGS seems hardwired for
> running sparse. So something liike
>
> make C=1 CHECK="scripts/checkpatch.pl" CHECKFLAGS="-
On Fri, Nov 17, 2017 at 01:13:10PM -0800, Linus Torvalds wrote:
> So the hardening efforts should instead _start_ from the standpoint of
> "let's warn about what looks dangerous, and maybe in a _year_ when
> we've warned for a long time, and we are confident that we've actually
> caught all the nor
On Fri, 10 Nov 2017, Dave Hansen wrote:
This should be folded into the previous patch.
> b/arch/x86/include/asm/pgtable_64.h | 94
> +++-
> 1 file changed, 61 insertions(+), 33 deletions(-)
>
> diff -puN arch/x86/include/asm/pgtable_64.h~kaiser-set-pgd-careful
On Fri, Nov 17, 2017 at 12:43 AM, Hans Verkuil wrote:
> diff --git a/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c
> b/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c
> index 3a33075dbb22..56a6a1fa 100644
> --- a/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c
> +++ b/drivers/gpu/drm/bridge/adv7511/
Am 20.11.2017 18:40, schrieb Colin King:
> From: Colin Ian King
>
> The assignment of DIV to itself is redundant and can be removed.
>
> Signed-off-by: Colin Ian King
> ---
> drivers/usb/serial/iuu_phoenix.c | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/drivers/usb/serial/iuu_phoe
On 2017-11-20 05:32, Frank Rowand wrote:
Hi Ulf,
On 11/19/17 23:23, Frank Rowand wrote:
adding devicetree list, devicetree maintainers
On 11/18/17 12:59, Ulf Samuelsson wrote:
I noticed when checking out the OpenWRT support for the board that they have a
method to avoid having to pass the
On Sat, Nov 18, 2017 at 01:21:39PM +1000, Nicholas Piggin wrote:
> Do you have any kind of numbers for this, out of curiosity? Binary
> size, performance, build time?
I don't have performance numbers to share. Are there any specific
benchmarks you'd be interested in seeing? Build time typically
in
On Mon, 20 Nov 2017, Guenter Roeck wrote:
> On Mon, Nov 20, 2017 at 01:18:38PM -0500, Nicolas Pitre wrote:
> > On Sun, 19 Nov 2017, Guenter Roeck wrote:
> >
> > > On 11/19/2017 08:08 PM, Nicolas Pitre wrote:
> > > > On Sun, 19 Nov 2017, Guenter Roeck wrote:
> > > > > On 11/19/2017 12:36 PM, Nicol
On Fri, 10 Nov 2017, Dave Hansen wrote:
> __set_fixmap(get_cpu_gdt_ro_index(cpu), get_cpu_gdt_paddr(cpu), prot);
> +
> + /* CPU 0's mapping is done in kaiser_init() */
> + if (cpu) {
> + int ret;
> +
> + ret = kaiser_add_mapping((unsigned long) get_cpu_gdt_ro(c
On Tue, Nov 14, 2017 at 5:10 AM, Martin Kepplinger wrote:
> A few years ago the FSF moved and "59 Temple Place" is wrong. Having this
> still in our source files feels old and unmaintained.
>
> Let's take the license statement serious and not confuse users.
>
> As https://www.gnu.org/licenses/gpl-
On Mon, Nov 20, 2017 at 11:50:00AM -0800, Palmer Dabbelt wrote:
> The RISC-V privileged ISA mandates the presence of an SBI, but there's
> no reason not to put it in the device tree. This would allow us to
> possibly remove the SBI later.
Thanks!
>
> CC: Jonathan Neuschäfer
> Signed-off-by: Pa
PROC_NUMBUF is 13 which is enough for "negative int + \n + \0".
However PIDs and TGIDs are never negative and newline is not a concern,
so use just 10 per integer.
Signed-off-by: Alexey Dobriyan
---
fs/proc/base.c| 16
fs/proc/fd.c |2 +-
fs/proc/self.c
Linus,
The following changes since commit 0b07194bb55ed836c2cc7c22e866b87a14681984:
Linux 4.14-rc7 (2017-10-29 13:58:38 -0700)
are available in the git repository at:
git://git.infradead.org/linux-mtd.git tags/for-linus-20171120
for you to fetch changes up to
> - ret = PTR_ERR(priv->clk);
> - dev_err(&pdev->dev, "cannot get clock: %d\n", ret);
> - goto eprobe;
> + dev_err(&pdev->dev, "cannot get clock\n");
> + return PTR_ERR(priv->clk);
Why dropping the 'ret' printout? Will it be printed by t
From: Haiyang Zhang
On Hyper-V the VF NIC has the same MAC as the related synthetic NIC.
VF NIC can work under the synthetic NIC transparently, without its
own IP address. The existing KVP daemon only gets IP from the first
NIC matching a MAC address, and may not be able to find the IP in
this ca
On Mon, Nov 20, 2017 at 08:32:47PM +0100, Romain Perier wrote:
> From: Romain Perier
>
> Now that all the drivers use dma pool API, we can remove the macro
> functions for PCI pool.
>
> Signed-off-by: Romain Perier
> Reviewed-by: Peter Senna Tschudin
I already acked this once on Oct 24. Plea
On Mon, Nov 20, 2017 at 02:47:20PM +, Mark Rutland wrote:
> However, we could instead check ld-version, produce a warning, and
> abort the build in such cases.
I believe the version number of gold didn't change in binutils 2.28.1,
where this was fixed, but we could certainly warn about older v
On 11/20/2017 08:58 PM, Bjorn Andersson wrote:
> On Sun 19 Nov 13:35 PST 2017, Jacek Anaszewski wrote:
>
>> Hi Bjorn,
>>
>> Thanks for the update.
>>
>> On 11/15/2017 08:13 AM, Bjorn Andersson wrote:
>>> This adds the binding document describing the three hardware blocks
>>> related to the Light P
On Mon, Nov 20, 2017 at 04:03:53PM +, mario.limoncie...@dell.com wrote:
> > -Original Message-
> > From: Darren Hart [mailto:dvh...@infradead.org]
> > Sent: Friday, November 17, 2017 2:39 PM
> > To: Limonciello, Mario
> > Cc: Andy Shevchenko ; LKML > ker...@vger.kernel.org>; platform-
On Tue, Nov 07, 2017 at 04:57:21PM +0900, Masahiro Yamada wrote:
> The description in the Makefile is odd. Fix the CONFIG selection
> in a cleaner way.
>
> Signed-off-by: Masahiro Yamada
Acked-by: Wolfram Sang
Simon, you did the last refactoring, can you have a look, too?
signature.asc
Des
On Tue, Nov 07, 2017 at 04:57:22PM +0900, Masahiro Yamada wrote:
> ARCH_RENESAS is a stronger condition than (ARM || ARM64).
> If ARCH_RENESAS is enabled, (ARM || ARM64) is met as well.
>
> What is worse, the first depends on line prevents COMPILE_TEST from
> enabling this driver. It should be re
> A typo in the subject.
>
> renesas_shci -> renesas_sdhc
renesas_sdhi ;)
signature.asc
Description: PGP signature
On Fri, 10 Nov 2017, Dave Hansen wrote:
>
> +static int kaiser_user_map_ptr_early(const void *start_addr, unsigned long
> size,
> + unsigned long flags)
> +{
> + int ret = kaiser_add_user_map(start_addr, size, flags);
> + WARN_ON(ret);
> + return ret;
Wh
READ_ONCE and WRITE_ONCE are useless when there is only one read/write
is being made.
Signed-off-by: Alexey Dobriyan
---
fs/proc/base.c |5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
--- a/fs/proc/base.c
+++ b/fs/proc/base.c
@@ -1371,7 +1371,7 @@ static ssize_t proc_fail_nth_wri
On Tue, Nov 07, 2017 at 05:09:28PM +0900, Masahiro Yamada wrote:
> The remove, suspend, resume hooks need tmio_mmc_host. It is tedious
> to get mmc_host from the driver_data and pass it to mmc_priv().
> We can directly set tmio_mmc_host to driver data to clean up the code.
>
> Signed-off-by: Masa
On Mon, Nov 20, 2017 at 09:07:33AM -0800, Andy Lutomirski wrote:
> +bool in_SYSENTER_stack(unsigned long *stack, struct stack_info *info)
Can you make it lowercase for consistency with the other in_*_stack()
functions? For example, in_irq_stack() is all lowercase even though
"IRQ" is normally wri
On Tue, Nov 07, 2017 at 05:09:29PM +0900, Masahiro Yamada wrote:
> The TMIO core misses to request_mem_region(). devm_ioremap_resource()
> takes care of it and makes the code cleaner.
>
> Signed-off-by: Masahiro Yamada
Reviewed-by: Wolfram Sang
Tested-by: Wolfram Sang
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On Mon, Nov 20, 2017 at 09:01:32PM +0100, Luc Van Oostenryck wrote:
> [not knowing much about RCU's needs here but knowing quite a bit
> about sparse]
>
> I think the issue here is mainly about the use of the address space.
> For kernel space vs. __user vs. __iomem, address space works quite
> we
On Fri, Nov 17, 2017 at 03:09:27PM +, Adam Thomson wrote:
> Current DT binding documentation shows an example where the IRQ
> for the device is chosen to be ACTIVE_HIGH. This is incorrect as
> the device only supports ACTIVE_LOW, so this commit fixes that
> discrepancy.
>
> Signed-off-by: Adam
On Fri, Nov 17, 2017 at 03:09:28PM +, Adam Thomson wrote:
> Current DT binding documentation shows an example where the IRQ
> for the device is chosen to be ACTIVE_HIGH. This is incorrect as
> the device only supports ACTIVE_LOW, so this commit fixes that
> discrepancy.
>
> Signed-off-by: Adam
On Fri, Nov 10, 2017 at 11:31 AM, Dave Hansen
wrote:
>
> From: Dave Hansen
>
> The IDT is another structure which the CPU references via a
> virtual address. It also obviously needs these to handle an
> interrupt in userspace, so these need to be mapped into the user
> copy of the page tables.
On Tue, Nov 07, 2017 at 05:09:30PM +0900, Masahiro Yamada wrote:
> Currently, tmio_mmc_ops is static data and tmio_mmc_host_probe()
> updates some hooks in the static data. This is a problem when
> two or more instances call tmio_mmc_host_probe() and each of them
> requests to use its own card_bus
On Fri, Nov 17, 2017 at 08:53:21AM -0800, Stephen Boyd wrote:
> It isn't clear if this function of_node_put()s the 'from'
> argument, or the node it searches. Clearly indicate which
> variable is touched. Fold in some more fixes from Randy too
> because we're in the area.
>
> Cc: Randy Dunlap
> S
On Tue, Nov 07, 2017 at 05:09:31PM +0900, Masahiro Yamada wrote:
> Drivers can set any mmc_host_ops hooks between tmio_mmc_host_alloc()
> and tmio_mmc_host_probe(). Remove duplicated hooks in tmio_mmc_host.
>
> Signed-off-by: Masahiro Yamada
Yes, this is much cleaner. I like it!
Reviewed-by: W
On Mon, Nov 20, 2017 at 12:42 PM, Josh Poimboeuf wrote:
> On Mon, Nov 20, 2017 at 09:07:33AM -0800, Andy Lutomirski wrote:
>> +bool in_SYSENTER_stack(unsigned long *stack, struct stack_info *info)
>
> Can you make it lowercase for consistency with the other in_*_stack()
> functions? For example,
On Fri, 10 Nov 2017, Dave Hansen wrote:
>
> +/* There are 12 bits of space for ASIDS in CR3 */
> +#define CR3_HW_ASID_BITS 12
> +/* When enabled, KAISER consumes a single bit for user/kernel switches */
> +#define KAISER_CONSUMED_ASID_BITS 0
> +
> +#define CR3_AVAIL_ASID_BITS (CR3_HW_ASID_BITS-KA
On Tue, Nov 07, 2017 at 05:09:32PM +0900, Masahiro Yamada wrote:
> mmc_of_parse() parses various DT properties and sets capability flags
> accordingly. However, drivers have no chance to run platform init
> code depending on such flags because mmc_of_parse() is called from
> tmio_mmc_host_probe().
On Mon, Nov 20, 2017 at 12:22 PM, Thomas Gleixner wrote:
> On Fri, 10 Nov 2017, Dave Hansen wrote:
>> __set_fixmap(get_cpu_gdt_ro_index(cpu), get_cpu_gdt_paddr(cpu), prot);
>> +
>> + /* CPU 0's mapping is done in kaiser_init() */
>> + if (cpu) {
>> + int ret;
>> +
>> +
> + struct mmc_host_ops mmc_host_ops;
Just came to think of it: maybe a shorter name?
host->ops
is still nicely readable, I'd think...
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On 11/20/2017 08:42 PM, Jens Axboe wrote:
> On 11/20/2017 12:29 PM, Christian Borntraeger wrote:
>>
>>
>> On 11/20/2017 08:20 PM, Bart Van Assche wrote:
>>> On Fri, 2017-11-17 at 15:42 +0100, Christian Borntraeger wrote:
This is
b7a71e66d (Jens Axboe2017-08-01 09:2
On Mon, Nov 20, 2017 at 03:20:14PM +, Mark Rutland wrote:
> Could you elaborate on what the integrated asembler doesn't like?
Here's the error, looks like in aes_sub:
:1:69: error: invalid operand for instruction
dup v1.4s, w12 ;movi v0.16b, #0 ;aese
On Tue, Nov 07, 2017 at 05:14:12PM +0900, Masahiro Yamada wrote:
> These registers are only used in drivers/mfd/tmio_core.c
>
> Signed-off-by: Masahiro Yamada
Well, yes, why not...
Acked-by: Wolfram Sang
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Hi,
I have been using the perf script -F option on the latest perf and I
find it not very convenient to use. I appreciate the + and - prefix to
field names to add or suppress them. But most of the time, I want to
print only one or two fields and I have to guess which ones are there
by default so I
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