On 10/16/2017 10:32 PM, Mike Kravetz wrote:
> Agree. I only wanted to point out the similarities.
> But, it does make me wonder how much of a benefit hugetlb 1G pages would
> make in the the RDMA performance comparison. The table in the presentation
> show a average speedup of something like 27%
On Mon, 16 Oct 2017, Marek Wilczewski
wrote:
> Hi All,
>
> I can check this patch tomorrow on real HW, but this is rather not
> correct way to go.
>
> CherryView / Braswell (N3xxx family) has got 3 DDI ports - see EDS,
> DDI0,1,2 - linked to PORTs B,C,D. (at least this is the Intel's naming).
On Mon, 2017-10-16 at 15:55 -0700, Kees Cook wrote:
> In preparation for unconditionally passing the struct timer_list pointer to
> all timer callbacks, switch to using the new timer_setup() and from_timer()
> to pass the timer pointer explicitly.
>
> Cc: Daniel Vetter
> Cc: Jani Nikula
> Cc: Da
On 2017/10/17 8:05, Rafael J. Wysocki wrote:
> On Monday, October 16, 2017 5:11:57 AM CEST Li, Aubrey wrote:
>> On 2017/10/14 8:35, Rafael J. Wysocki wrote:
>>> On Saturday, September 30, 2017 9:20:28 AM CEST Aubrey Li wrote:
Record the overhead of idle entry in micro-second
>>>
>>> What
From: Lei Yang
it only prints FAIL status when test fails, but doesn't print PASS
status when test pass,this patch is to add PASS status in the test log.
Signed-off-by: Lei Yang
---
tools/testing/selftests/memory-hotplug/Makefile | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff
At the moment the device table save() returns -EINVAL if
vgic_its_check_id() fails to return the gpa of the entry
associated to the device/collection id. Let vgic_its_check_id()
return an int instead of a bool and return a more precised
error value:
- EINVAL in case the id is out of range
- EFAULT
This series fixes various bugs observed when saving/restoring the
ITS state before the guest writes the ITS registers (on first boot or
after reset/reboot).
This is a follow up of Wanghaibin's series [1] plus additional
patches following additional code review. It also proposes one
ITS reset imple
In case the device table save fails, we currently do not
attempt to save the collection table. However it may
happen that the device table fails because the structures
in memory are inconsistent with device GITS_BASER however
this does not mean collection backup can't and shouldn't
be performed. Sa
At the moment, the in-kernel emulated ITS is not properly reset.
On guest restart/reset some registers keep their old values and
internal structures like device, ITE, and collection lists are not
freed.
This may lead to various bugs. Among them, we can have incorrect state
backup or failure when s
On reset we clear the valid bits of GITS_CBASER and GITS_BASER.
We also clear command queue registers and free the cache (device,
collection, and lpi lists).
Signed-off-by: Eric Auger
Reviewed-by: Christoffer Dall
---
v2 -> v3:
- added Christoffer's R-b
---
arch/arm/include/uapi/asm/kvm.h |
vgic_its_restore_cte returns +1 if the collection table entry
is valid and properly decoded. As a consequence, if the
collection table is fully filled with valid data that are
decoded without error, vgic_its_restore_collection_table()
returns +1. This is wrong.
Let's use the standard C convention
At the moment vgic_its_process_commands() does not
check the CBASER is valid before processing any command.
Let's fix that.
Also rename cbaser local variable into cbaser_pa to avoid
any confusion with the full register.
Signed-off-by: Eric Auger
---
virt/kvm/arm/vgic/vgic-its.c | 13 ---
When the GITS_BASER.Valid gets cleared, the data structures in
guest RAM are not valid anymore. The device, collection
and LPI lists stored in the in-kernel ITS represent the same
information in some form of cache. So let's void the cache.
Signed-off-by: Eric Auger
---
v2 -> v3:
- add a comment
At the moment we don't properly check the GITS_BASER.Valid
bit before saving the collection and device tables.
On vgic_its_save_collection_table() we use the GITS_BASER gpa
field whereas the Valid bit should be used.
On vgic_its_save_device_tables() there is no check. This can
cause various bugs,
* Byungchul Park wrote:
> On Sat, Oct 14, 2017 at 04:36:51AM -0700, tip-bot for Ingo Molnar wrote:
> > Commit-ID: b483cf3bc249d7af706390efa63d6671e80d1c09
> > Gitweb:
> > https://git.kernel.org/tip/b483cf3bc249d7af706390efa63d6671e80d1c09
> > Author: Ingo Molnar
> > AuthorDate: Sat, 1
From: wanghaibin
We create 2 new functions that frees the device and
collection lists. this is currently called by vgic_its_destroy()
and we will add other callers in subsequent patches.
We also remove the check on its->device_list.next as it looks
unnecessary. Indeed, the device list always is
The spec says it is UNPREDICTABLE to enable the ITS
if any of the following conditions are true:
- GITS_CBASER.Valid == 0.
- GITS_BASER.Valid == 0, for any GITS_BASER register
where the Type field indicates Device.
- GITS_BASER.Valid == 0, for any GITS_BASER register
where the Type field indic
AT the moment if ITT only contains invalid entries,
vgic_its_restore_itt returns 1 and this is considered as
an an error in vgic_its_restore_dte.
Also in case the device table only contains invalid entries,
the table restore fails and this is not correct.
This patch fully revisits the errror hand
On Tue, Oct 17, 2017 at 12:05:11AM +0200, Rafael J. Wysocki wrote:
> On Monday, October 16, 2017 8:28:52 AM CEST Greg Kroah-Hartman wrote:
> > On Mon, Oct 16, 2017 at 03:29:02AM +0200, Rafael J. Wysocki wrote:
> > > struct dev_pm_info {
> > > pm_message_tpower_state;
> > > unsigned
On Fri, Oct 13, 2017 at 10:21:50AM -0400, Steven Rostedt wrote:
> From: Steven Rostedt (VMware)
>
> As trace events when defined create data structures and functions to
> process them, defining trace events when not using them is a waste of
> memory.
>
> The trace events thermal_power_devfreq_ge
I think this driver is at entirely the wrong level.
If you want to expose pmem to a guest with flushing assist do it
as pmem, and not a block driver.
On Fri, Oct 13, 2017 at 10:23:09AM -0400, Steven Rostedt wrote:
> From: Steven Rostedt (VMware)
>
> As trace events when defined create data structures and functions to
> process them, defining trace events when not using them is a waste of
> memory.
>
> The trace events thermal_power_cpu_get_po
On 16/10/17 22:28, Ben Hutchings wrote:
On Fri, 2017-10-06 at 10:53 +0200, Greg Kroah-Hartman wrote:
4.4-stable review patch. If anyone has any objections, please let me know.
--
From: Matt Redfearn
[ Upstream commit db8466c581cca1a08b505f1319c3ecd246f16fa8 ]
[...]
Ther
>> A minor complaint: all commits are missing "Fixes:" tag.
>
> None of these patches fix anything.
It depends on the view which you prefer.
> All are trivial changes without much of any impact.
I find that they improve the affected software another bit.
Other adjustments can be more noticeabl
Hi Ard,
On Thu, 12 Oct 2017 20:59:37 +0100, Ard Biesheuvel wrote:
> Currently, when booting a kernel with DMI support on a platform that has
> no DMI tables, the following output is emitted into the kernel log:
>
> [0.128818] DMI not present or invalid.
> ...
> [1.306659] dmi: Firmw
On Wed, Oct 11, 2017 at 12:01:20PM -0500, Josh Poimboeuf wrote:
> I failed to add the slab maintainers to CC on the last attempt. Trying
> again.
>
> On Tue, Oct 10, 2017 at 09:31:06PM -0500, Josh Poimboeuf wrote:
> > On Tue, Oct 10, 2017 at 08:15:13PM +0800, kernel test robot wrote:
> > >
> > >
From: Netanel Belgazal
ENA driver was developed by developers from Annapurna Labs.
Annapurna Labs was acquired by Amazon and the company's domain
(@annapurnalabs.com) will become deprecated soon.
Update the email addresses of the maintainers to the alternative amazon
emails (@amazon.com)
Signed
On 2017/10/17 8:07, Rafael J. Wysocki wrote:
> On Monday, October 16, 2017 9:44:41 AM CEST Li, Aubrey wrote:
>>
>> Or you concern why the threshold can't simply be tick interval?
>
> That I guess.
>
>> For the latter, if the threshold is close/equal to the tick, it's quite
>> possible
>> the nex
For the SEA notification, the two functions ghes_sea_add() and
ghes_sea_remove() are only called when CONFIG_ACPI_APEI_SEA
is defined. If not, it will return errors in the ghes_probe()
and not continue. If the probe is failed, the ghes_sea_remove()
also has no chance to be called. Hence, remove the
On the Amlogic Gx SoCs (GXBB, GXL & GXM), the VPU power domain is initialized
by the vendor U-Boot code, but running mainline U-boot has been possible
on these SoCs. But lacking such init made the system lock at kernel boot.
This patchset adds the Video Processing Unit power domain driver to enabl
The Video Processing Unit needs a specific Power Domain powering scheme
this driver handles this as a PM Power Domain driver.
Signed-off-by: Neil Armstrong
---
drivers/soc/amlogic/Kconfig | 10 ++
drivers/soc/amlogic/Makefile| 1 +
drivers/soc/amlogic/meson-gx-pwrc-vpu
On Mon 16-10-17 21:02:09, James Hogan wrote:
> On Mon, Oct 16, 2017 at 09:00:47PM +0200, Michal Hocko wrote:
> > [CCing metag people for the metag elf_map implementation specific. The
> > thread
> > starts here
> > http://lkml.kernel.org/r/20171016134446.19910-1-mho...@kernel.org]
> >
> > On Mon
ARMv8.2 requires implementation of the RAS extension, in
this extension it adds SEI(SError Interrupt) notification
type, this patch adds new GHES error source SEI handling
functions. Because this error source parsing and handling
methods are similar with the SEA. So share some SEA handling
function
Signed-off-by: Neil Armstrong
---
.../bindings/power/amlogic,meson-gx-pwrc.txt | 65 ++
1 file changed, 65 insertions(+)
create mode 100644
Documentation/devicetree/bindings/power/amlogic,meson-gx-pwrc.txt
diff --git a/Documentation/devicetree/bindings/power/amlogic,m
On 17.10.2017 00:05, Nagarathnam Muthusamy wrote:
On 10/16/2017 09:24 AM, Oleg Nesterov wrote:
On 10/13, Konstantin Khlebnikov wrote:
On 13.10.2017 19:05, Oleg Nesterov wrote:
I won't insist, but this suggests we should add a new helper,
get_ns_by_fd_type(fd, type), and convert get_net_ns_b
>
> I think this driver is at entirely the wrong level.
>
> If you want to expose pmem to a guest with flushing assist do it
> as pmem, and not a block driver.
Are you saying do it as existing i.e ACPI pmem like interface?
The reason we have created this new driver is exiting pmem driver
does n
On Tue, 17 Oct 2017, Ingo Molnar wrote:
> * Byungchul Park wrote:
> > > diff --git a/lib/Kconfig.debug b/lib/Kconfig.debug
> > > index 2689b7c..e270584 100644
> > > --- a/lib/Kconfig.debug
> > > +++ b/lib/Kconfig.debug
> > > @@ -1092,8 +1092,8 @@ config PROVE_LOCKING
> > > select DEBUG_MUTEXES
>
On Mon 16-10-17 17:15:31, David Rientjes wrote:
> Please simply dump statistics for all slab caches where the memory
> footprint is greater than 5% of system memory.
Unconditionally? User controlable?
--
Michal Hocko
SUSE Labs
Dear all,
I'm working on an iMX6 based board with a PCA9555 which is used both to
drive LEDs and manage some GPIOs.
My current kernel is quite old (4.1.15) but I've found Cédric patches on
mainline and backported to this old revision.
I'm facing an issue with it, because it seems that it fa
Looks good,
Acked-by: Johannes Thumshirn
--
Johannes Thumshirn Storage
jthumsh...@suse.de+49 911 74053 689
SUSE LINUX GmbH, Maxfeldstr. 5, 90409 Nürnberg
GF: Felix Imendörffer, Jane Smithard, Graham Norton
HRB 21284 (AG Nürn
On (10/16/17 10:15), Steven Rostedt wrote:
[..]
> > just "brainstorming" it... with some silly ideas.
> >
> > pushing the data from NMI panic might look like we are replacing one
> > deadlock scenario with another deadlock scenario. some of the console
> > drivers are s complex internally. so
On Tue, 17 Oct 2017, Joonsoo Kim wrote:
> On Wed, Oct 11, 2017 at 12:01:20PM -0500, Josh Poimboeuf wrote:
> > > Looking at the panic, the code in slob_free() was:
> > >
> > >0: e8 8d f7 ff ff callq 0xf792
> > >5: 48 ff 05 c9 8c 91 02incq 0x2918cc9(%rip)
On Tue 17-10-17 09:20:58, Kemi Wang wrote:
[...]
Other than two remarks below, it looks good to me and it also looks
simpler.
> diff --git a/mm/vmstat.c b/mm/vmstat.c
> index 4bb13e7..e746ed1 100644
> --- a/mm/vmstat.c
> +++ b/mm/vmstat.c
> @@ -32,6 +32,76 @@
>
> #define NUMA_STATS_THRESHOLD (
Dexuan reported that the recent rework of the vector allocation mode in x86
broke HyperV PCI passtrough because the rework missed to add the
MSI_FLAG_MUST_REACTIVATE flag to the HyperV/PCI interrupt domain info.
The simple solution would be to set the flag in the HyperV/PCI driver but
it's better
If interrupt reservation mode is enabled then the PCI/MSI interrupts must
be reactivated after early activation.
Make sure that all callers of pci_msi_create_irq_domain() have the
MSI_FLAG_MUST_REACTIVATE set when reservation mode is enabled.
Signed-off-by: Thomas Gleixner
---
drivers/pci/msi.c
The interrupt reservation mode requires reactivation of PCI/MSI
interrupts. Create a config option, so the PCI code can set the
corresponding flag when required.
Signed-off-by: Thomas Gleixner
---
kernel/irq/Kconfig |3 +++
1 file changed, 3 insertions(+)
--- a/kernel/irq/Kconfig
+++ b/kern
Select CONFIG_GENERIC_IRQ_RESERVATION_MODE so PCI/MSI domains get the
MSI_FLAG_MUST_REACTIVATE flag set in pci_msi_create_irq_domain().
Remove the explicit setters of this flag in the apic/msi code as they are
not longer required.
Fixes: 4900be83602b ("x86/vector/msi: Switch to global reservation
Hi Peter,
On Fri, Oct 13, 2017 at 05:01:04PM +0200, Peter Rosin wrote:
> On 2017-10-13 15:29, Alan Cox wrote:
> > On Thu, 12 Oct 2017 13:35:17 +0200
> > Peter Rosin wrote:
> >
> >> Hi!
> >>
> >> I have encountered an "interesting" bug. It silently corrupts data
> >> and is generally nasty...
> >
On Tue, Oct 17, 2017 at 06:57:43AM +0200, Markus Trippelsdorf wrote:
> On 2017.10.16 at 18:06 -0700, Andy Lutomirski wrote:
> > On Mon, Oct 16, 2017 at 3:15 AM, Borislav Petkov wrote:
> > > On Mon, Oct 16, 2017 at 10:39:17AM +0800, kernel test robot wrote:
> > >>
> > >> Greeting,
> > >>
> > >> FYI
On Mon, Oct 16, 2017 at 1:49 PM, Jarkko Sakkinen
wrote:
> On Mon, Oct 16, 2017 at 02:28:33PM +0300, Jarkko Sakkinen wrote:
>> On Wed, Oct 11, 2017 at 02:52:54PM +0300, Jarkko Sakkinen wrote:
>> > On Wed, Oct 11, 2017 at 12:54:26PM +1100, James Morris wrote:
>> > > On Tue, 10 Oct 2017, Jarkko Sakki
On Tue, Oct 17, 2017 at 03:40:56AM -0400, Pankaj Gupta wrote:
> Are you saying do it as existing i.e ACPI pmem like interface?
> The reason we have created this new driver is exiting pmem driver
> does not define proper semantics for guest flushing requests.
At this point I'm caring about the Linu
Make dma_get_cache_alignment() to accept a 'dev' argument. As a result,
it can return different alignments due to different devices' I/O cache
coherency.
Currently, ARM/ARM64 and MIPS support coherent & noncoherent devices
co-exist. This may be extended in the future, so add a new function
pointer
On 2017年10月17日 15:54, Michal Hocko wrote:
> On Tue 17-10-17 09:20:58, Kemi Wang wrote:
> [...]
>
> Other than two remarks below, it looks good to me and it also looks
> simpler.
>
>> diff --git a/mm/vmstat.c b/mm/vmstat.c
>> index 4bb13e7..e746ed1 100644
>> --- a/mm/vmstat.c
>> +++ b/mm/vmstat.
In non-coherent DMA mode, kernel uses cache flushing operations to
maintain I/O coherency, so scsi's block queue should be aligned to
ARCH_DMA_MINALIGN. Otherwise, If a DMA buffer and a kernel structure
share a same cache line, and if the kernel structure has dirty data,
cache_invalidate (no writeb
On 2017/10/12 05:04AM, Masami Hiramatsu wrote:
> On Tue, 10 Oct 2017 22:32:31 +0530
> "Naveen N. Rao" wrote:
>
> > On 2017/09/19 10:00AM, Masami Hiramatsu wrote:
> > So, we don't seem to _require_ users to return !0 if the handler
> > changes [n]ip? Or to always change [n]ip if returning !0.
> >
In non-coherent DMA mode, kernel uses cache flushing operations to
maintain I/O coherency, so in ata_do_dev_read_id() the DMA buffer
should be aligned to ARCH_DMA_MINALIGN. Otherwise, If a DMA buffer
and a kernel structure share a same cache line, and if the kernel
structure has dirty data, cache_i
In non-coherent DMA mode, kernel uses cache flushing operations to
maintain I/O coherency, so libsas's SMP request/response should be
aligned to ARCH_DMA_MINALIGN. Otherwise, If a DMA buffer and a kernel
structure share a same cache line, and if the kernel structure has
dirty data, cache_invalidate
On Mon, Oct 16, 2017 at 03:46:32PM +0200, Greg KH wrote:
> On Mon, Oct 16, 2017 at 02:11:01PM +0100, David Woodhouse wrote:
> > On Mon, 2017-10-16 at 11:25 +0200, Greg KH wrote:
> > > Documentation: Add a file explaining the requested Linux kernel
> > > license enforcement policy
> > >
> > > Here'
Currently, MIPS is an architecture which support coherent & noncoherent
devices co-exist. So implement get_cache_alignment() function pointer
in 'struct dma_map_ops' to return different dma alignments.
Cc: sta...@vger.kernel.org
Signed-off-by: Huacai Chen
---
arch/mips/cavium-octeon/dma-octeon.c
On reference boards and derivatives, the HDMI Logic is powered by an external
5V regulator.
This regulator was set by the Vendor U-Boot, add optional support for it.
Signed-off-by: Neil Armstrong
---
Documentation/devicetree/bindings/display/amlogic,meson-dw-hdmi.txt | 4
1 file changed, 4
On the Amlogic Gx SoCs (GXBB, GXL & GXM), the VPU power domain is initialized
by the vendor U-Boot code, but running mainline U-boot has been possible
on these SoCs. But lacking such init made the system lock at kernel boot.
A PM Power Domain driver has been pushed at [1] to solve the main issue.
On 10/16/2017 02:49 PM, changbin...@intel.com wrote:
> From: Changbin Du
>
> This patch introduced 4 new interfaces to allocate a prepared
> transparent huge page.
> - alloc_transhuge_page_vma
> - alloc_transhuge_page_nodemask
> - alloc_transhuge_page_node
> - alloc_transhuge_page
>
If
The Video Processing Unit power domain was setup by the Vendor U-Boot,
add support for an optional Power Domain phandle to setup it from the kernel.
Signed-off-by: Neil Armstrong
---
Documentation/devicetree/bindings/display/amlogic,meson-vpu.txt | 4
1 file changed, 4 insertions(+)
diff -
The VPU init misses these configurations values.
Signed-off-by: Neil Armstrong
---
drivers/gpu/drm/meson/meson_drv.c | 9 +
drivers/gpu/drm/meson/meson_registers.h | 4
2 files changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/meson/meson_drv.c
b/drivers/gpu/drm/meson/m
On reference boards and derivatives, the HDMI Logic is powered by an external
5V regulator.
This regulator was set by the Vendor U-Boot, add optional support for it.
Signed-off-by: Neil Armstrong
---
drivers/gpu/drm/meson/meson_dw_hdmi.c | 13 +
1 file changed, 13 insertions(+)
diff
Add edp panel and enable related nodes on kevin.
Signed-off-by: Jeffy Chen
Reviewed-by: Mark Yao
---
Changes in v3: None
Changes in v2: None
arch/arm64/boot/dts/rockchip/rk3399-gru-kevin.dts | 29 +++
arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi | 16 +
2
From: Tomasz Figa
The driver that instantiates the bridge should own the drvdata, as all
driver model callbacks (probe, remove, shutdown, PM ops, etc.) are also
owned by its driver struct. Moreover, storing two different pointer
types in driver data depending on driver initialization status is ba
Since we are trying to access components' resources in the master's
suspend/resume PM callbacks(e.g. panel), add device links to correct
the suspend/resume and shutdown ordering.
Signed-off-by: Jeffy Chen
---
Changes in v3: None
Changes in v2:
Use device link to correct the suspend/resume and sh
Hi,
Kees Cook writes:
> In preparation for unconditionally passing the struct timer_list pointer to
> all timer callbacks, switch to using the new timer_setup() and from_timer()
> to pass the timer pointer explicitly.
>
> Cc: Felipe Balbi
> Cc: Greg Kroah-Hartman
> Cc: linux-...@vger.kernel.or
When the pwm driver is unbound while the pwm is still requested, the
pwm core would not actually remove the pwmchip(return -EBUSY instead).
So it would hold some references to the invalid resources(e.g. pwmchip).
And the customer who requested the pwm would have those references too,
and may cras
Add missing error handling in rockchip_dp_bind().
Fixes: 9e32e16e9e98 ("drm: rockchip: dp: add rockchip platform dp driver")
Signed-off-by: Jeffy Chen
---
Changes in v3: None
Changes in v2: None
drivers/gpu/drm/rockchip/analogix_dp-rockchip.c | 14 --
1 file changed, 12 insertions(
On 17/10/2017 09:38, Neil Armstrong wrote:
> Signed-off-by: Neil Armstrong
> ---
> .../bindings/power/amlogic,meson-gx-pwrc.txt | 65
> ++
> 1 file changed, 65 insertions(+)
> create mode 100644
> Documentation/devicetree/bindings/power/amlogic,meson-gx-pwrc.txt
>
>
On Mon, Oct 16, 2017 at 1:35 PM, Mark Brown wrote:
> Hi all,
>
> Today's linux-next merge of the drm-intel tree got a conflict in:
>
> drivers/gpu/drm/i915/i915_gem.c
>
> between commit:
>
> b85577b72837e ("drm/i915: Order two completing nop_submit_request")
>
> from the drm-intel-fixes tree a
Make edp display works on chromebook kevin(at least for boot animation).
Also solve some issues i meet during the bringup.
Changes in v3:
Assign orphan pwms to dummy pwmchip instead of adding device link in the
customer driver.
Changes in v2:
Use device link to correct the suspend/resume and sh
From: Huang Ying
One page may store a set of entries of the
sis->swap_map (swap_info_struct->swap_map) in multiple swap clusters.
If some of the entries has sis->swap_map[offset] > SWAP_MAP_MAX,
multiple pages will be used to store the set of entries of the
sis->swap_map. And the pages are linke
Just took a quick look over this and I basically agree with the comments
from Robin.
What I don't understand is why you're even trying to do all these
hacky things.
It seems like the controller should simply set dma_pfn_offset for
each device hanging off it, and all the supported architectures
sh
On Tue 17-10-17 16:03:44, kemi wrote:
> On 2017年10月17日 15:54, Michal Hocko wrote:
[...]
> > So basically any value will enable numa stats. This means that we would
> > never be able to extend this interface to e.g. auto mode (say value 2).
> > I guess you meant to check sysctl_vm_numa_stat == ENABL
Hi Brian,
On 10/17/2017 07:57 AM, Brian Norris wrote:
This is going to be a*lot* of churn throughout the tree, if we expect
all resource consumers to do this. I think we'd want some kind of
agreement from the PM maintainers and (larger) subsystem owners before
going down this route...
And in t
The Video Processing Unit needs a specific Power Domain powering scheme
this driver handles this as a PM Power Domain driver.
Signed-off-by: Neil Armstrong
---
drivers/soc/amlogic/Kconfig | 10 ++
drivers/soc/amlogic/Makefile| 1 +
drivers/soc/amlogic/meson-gx-pwrc-vpu
On the Amlogic Gx SoCs (GXBB, GXL & GXM), the VPU power domain is initialized
by the vendor U-Boot code, but running mainline U-boot has been possible
on these SoCs. But lacking such init made the system lock at kernel boot.
This patchset adds the Video Processing Unit power domain driver to enabl
Looks fine:
Reviewed-by: Christoph Hellwig
Greg, do you want to take this or should I queue it up in the
dma-mapping tree?
Signed-off-by: Neil Armstrong
---
.../bindings/power/amlogic,meson-gx-pwrc.txt | 61 ++
1 file changed, 61 insertions(+)
create mode 100644
Documentation/devicetree/bindings/power/amlogic,meson-gx-pwrc.txt
diff --git a/Documentation/devicetree/bindings/power/amlogic,m
This reverts commit e863d539614641 ("kprobes: Warn if optprobe handler
tries to change execution path").
On powerpc, we place a probe at kretprobe_trampoline to catch function
returns and with CONFIG_OPTPROBES, this probe gets optimized. This
works for us due to the way we handle the optprobe as d
On 17 October 2017 at 08:27, Jean Delvare wrote:
> Hi Ard,
>
> On Thu, 12 Oct 2017 20:59:37 +0100, Ard Biesheuvel wrote:
>> Currently, when booting a kernel with DMI support on a platform that has
>> no DMI tables, the following output is emitted into the kernel log:
>>
>> [0.128818] DMI not
From: Huang Ying
Now, when the page table is walked in the implementation of
/proc//pagemap, pmd_soft_dirty() is used for both the PMD huge
page map and the PMD migration entries. That is wrong,
pmd_swp_soft_dirty() should be used for the PMD migration entries
instead because the different page
A mismerge in linux-next caused a build failure:
drivers/gpu/drm/i915/i915_gem.c: In function 'nop_submit_request':
drivers/gpu/drm/i915/i915_gem.c:3092:54: error: 'flags' undeclared (first use
in this function); did you mean 'class'?
This is the fixup I used to get a clean build on top of today
Il 17/10/2017 10:18, Cédric Le Goater ha scritto:
On 10/17/2017 09:36 AM, Andrea Scian - DAVE Embedded Systems wrote:
Dear all,
I'm working on an iMX6 based board with a PCA9555 which is used both to drive
LEDs and manage some GPIOs.
The PCA9555 chip and the PCA955[0-3] chips have different
On Mon, Oct 16, 2017 at 08:43:15PM -0500, Brijesh Singh wrote:
> Actually, I worked to enable the kvmclock support before the
> kvm-stealtime, eoi and apf_reason. The kvmclock uses memblock_alloc() to
> allocate the shared memory and since the memblock_alloc() returns the
> physical address hence I
On Monday 16 October 2017 12:04 PM, Greg KH wrote:
> On Mon, Oct 16, 2017 at 11:35:53AM +0530, Kishon Vijay Abraham I wrote:
>> Hi Greg,
>>
>> On Wednesday 04 October 2017 06:09 PM, Kishon Vijay Abraham I wrote:
>>> Hi Greg,
>>>
>>> Please find below the phy pull request for 4.14 -rc cycle below.
On Mon, Oct 16, 2017 at 04:24:56PM -0700, Kees Cook wrote:
> In preparation for unconditionally passing the struct timer_list pointer to
> all timer callbacks, switch to using the new timer_setup() and from_timer()
> to pass the timer pointer explicitly.
>
> Cc: Mauro Carvalho Chehab
> Cc: Greg K
> +/* Macros to help extract property data */
> +#define U8TOU32(b, offs) \
> + u32)b[0 + offs] << 0) & 0x00ff) | \
> + (((u32)b[1 + offs] << 8) & 0xff00) | \
> + (((u32)b[2 + offs] << 16) & 0x00ff) | \
> + (((u32)b[3 + offs] << 24) & 0xff00))
Please us hel
On Tue, Oct 17, 2017 at 10:17:01AM +0200, Christoph Hellwig wrote:
> Looks fine:
>
> Reviewed-by: Christoph Hellwig
>
> Greg, do you want to take this or should I queue it up in the
> dma-mapping tree?
You can take it, thanks!
Acked-by: Greg Kroah-Hartman
Now the VPU Power Domain has been fixed while boothing from Mainline U-Boot,
VPU and HDMI nodes can finally be added to the Odroid-C2 DTS.
Signed-off-by: Neil Armstrong
---
.../arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts | 30 ++
1 file changed, 30 insertions(+)
diff --gi
This patch adds support for the VPU Power Domain nodes, and attaches the
VPU power domain to the VPU node.
Signed-off-by: Neil Armstrong
---
arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 11
arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 43 +
arch/arm64/boot/
On the Amlogic Gx SoCs (GXBB, GXL & GXM), the VPU power domain is initialized
by the vendor U-Boot code, but running mainline U-boot has been possible
on these SoCs. But lacking such init made the system lock at kernel boot.
A PM Power Domain driver has been pushed at [1] to solve the main issue.
Now the Amlogic Meson GX SoCs datasheet documents all the Reset registers,
grow the memory in the node to allow usage of the level registers.
Signed-off-by: Neil Armstrong
---
arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64
> > Are you saying do it as existing i.e ACPI pmem like interface?
> > The reason we have created this new driver is exiting pmem driver
> > does not define proper semantics for guest flushing requests.
>
> At this point I'm caring about the Linux-internal interface, and
> for that it should be i
On Tue, Oct 17, 2017 at 10:11:53AM +0200, Arnd Bergmann wrote:
> This merge seems fine, but it seems there was another merge
> against the akpm tree that introduced a build error by reintroducing
> the spin_lock_irqsave() without restoring the local variable:
> drivers/gpu/drm/i915/i915_gem.c: In
On reference boards and derivatives, the HDMI Logic is powered by an external
5V regulator.
This regulator was set by the Vendor U-Boot, add the regulator and phandle
property to the HDMI node.
Signed-off-by: Neil Armstrong
---
arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi | 12 ++
Hi,
Bhumika Goyal writes:
> Make these structures const as they are only passed to the const
> argument of the functions config_{group/item}_init_type_name.
>
> Signed-off-by: Bhumika Goyal
> ---
> * Changes in v2- Combine all the followup patches and the constification
> patches into a series.
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