On Fri, Oct 06, 2017 at 08:06:07PM -0500, Brijesh Singh wrote:
> The SEV_PDH_CERT_EXPORT command can be used to export the PDH and its
> certificate chain. The command is defined in SEV spec section 5.10.
>
> Cc: Paolo Bonzini
> Cc: "Radim Krčmář"
> Cc: Borislav Petkov
> Cc: Herbert Xu
> Cc: G
> Do you know what your physical memory layout looks like?
[0.00] Memory: 34960K/131072K available (16316K kernel code,
6716K rwdata, 7996K rodata, 1472K init, 8837K bss, 79728K reserved,
16384K cma-reserved)
[0.00] Virtual kernel memory layout:
[0.00] kasan : 0x0
> -Original Message-
> From: Greg KH [mailto:g...@kroah.com]
> Sent: Friday, October 13, 2017 4:43 AM
> To: Darren Hart
> Cc: Alan Cox ; Limonciello, Mario
> ; Andy Shevchenko
> ; LKML ;
> platform-driver-...@vger.kernel.org; Andy Lutomirski ;
> quasi...@google.com; pali.ro...@gmail.com; r
On 13/10/2017 23:48, Peng Hao wrote:
> When poweroff L1 Guest with L2 guset on L1, it exists a path to
> trigger a bad_page bug_on.
How easy it is to reproduce? CCing Junaid and Guangrong too.
> !page_count(pfn_to_page(pfn)) Warning in mmu_spte_clear_track_bits will
> appear before,then it may s
Hi,
On Fri, Oct 13, 2017 at 4:25 AM, Masahiro Yamada
wrote:
> The cache files are only cleaned away by "make clean". If you continue
> incremental builds, the cache files will grow up little by little.
> It is not a big deal in general use cases because compiler flags do not
> change quite often
perf-record had a '-l' option that mean "scale counter values"
very long time ago, but it currently belong to perf-stat as '-c'.
So remove it. I found this problem in the below case.
$ perf record -e cycles -l sleep 3
Error: unknown switch `l
Cc: Jiri Olsa
Cc: Namhyung Kim
Signed-off-
From: Joel Fernandes
In preparation of adding irqsoff and preemptsoff enable and disable trace
events, move required functions and code to make it easier to add these events
in a later patch. This patch is just code movement and no functional change.
Link: http://lkml.kernel.org/r/20171006005432.
> It shouldn't be difficult to use section mappings with my patch, I just
> don't really see the need to try to optimise TLB pressure when you're
> running with KASAN enabled which already has something like a 3x slowdown
> afaik. If it ends up being a big deal, we can always do that later, but
> m
git://git.kernel.org/pub/scm/linux/kernel/git/rostedt/linux-trace.git
for-next
Head SHA1: 8715b108cd75523c9b2e833cdcd7aeb363767f95
Joel Fernandes (3):
tracing: Prepare to add preempt and irq trace events
tracing: Add support for preempt and irq enable/disable events
ftrace: C
Em Fri, Oct 13, 2017 at 02:58:40PM +, Liang, Kan escreveu:
> > Em Fri, Oct 13, 2017 at 07:09:26AM -0700, kan.li...@intel.com escreveu:
> > > From: Kan Liang
> > >
> > > The process function process_synthesized_event writes the process
> > > result to perf.data, which is not multithreading frie
From: Joel Fernandes
Filters should be cleared of init functions during freeing of init
memory when the ftrace dyn records are released. However in current
code, the filters are left as is. This patch clears the hashes of the
saved init functions when the init memory is freed. This fixes the
foll
From: Joel Fernandes
Preempt and irq trace events can be used for tracing the start and
end of an atomic section which can be used by a trace viewer like
systrace to graphically view the start and end of an atomic section and
correlate them with latencies and scheduling issues.
This also serves
perf-record had a '-l' option that mean "scale counter values"
very long time ago, but it currently belong to perf-stat as '-c'.
So remove it. I found this problem in the below case.
$ perf record -e cycles -l sleep 3
Error: unknown switch `l
Cc: Jiri Olsa
Cc: Namhyung Kim
Signed-off-
On 09/24/2017 05:47 PM, Jonathan Cameron wrote:
On Thu, 21 Sep 2017 09:26:52 +0800
Zhiyong Tao wrote:
Add auxadc device node for MT2712.
Signed-off-by: Zhiyong Tao
I've applied the IIO patches to make this work, so assume this will get
picked up in due course.
pushed now to v4.14-next
On 13.10.2017 13:56, Markus Trippelsdorf wrote:
> On 2017.10.13 at 13:39 +0200, Prakash Punnoor wrote:
>> after some use (eg. compiling packages) the machine locks up hard. Magic
>> SysRq doesn't work.
>>
>> I had trouble bisecting the offending commit. This is my third try. And
>> it points to 94b
On 13/10/17 15:29, gengdongjiu wrote:
> Hi Marc,
> Thank you very much for your time to review it.
>
>> On 12/10/17 17:44, Dongjiu Geng wrote:
>>> When a exception is trapped to EL2, hardware uses ELR_ELx to hold the
>>> current fault instruction address. If KVM wants to inject a abort to
>>>
On 10/13/2017 08:05 AM, Shuah Khan wrote:
> On 10/12/2017 06:09 PM, John Stultz wrote:
>> On Thu, Oct 12, 2017 at 4:45 PM, Shuah Khan wrote:
>>> On 10/12/2017 03:26 PM, Greg Kroah-Hartman wrote:
This is the start of the stable review cycle for the 4.13.7 release.
There are 2 patches in t
On Thu, 12 Oct 2017, Anshuman Khandual wrote:
> > +static long __alloc_vma_contig_range(struct vm_area_struct *vma)
> > +{
> > + gfp_t gfp = GFP_HIGHUSER | __GFP_ZERO;
>
> Would it be GFP_HIGHUSER_MOVABLE instead ? Why __GFP_ZERO ? If its
> coming from Buddy, every thing should have already been
On 13 October 2017 at 15:42, Emil Renner Berthing
wrote:
> On 13 October 2017 at 15:25, Heiko Stuebner wrote:
>> Am Freitag, 13. Oktober 2017, 18:41:38 CEST schrieb Jeffy Chen:
>>> Add edp panel and enable related nodes on kevin.
>>>
>>> Signed-off-by: Jeffy Chen
>>
>> does this actually work wi
On 10/11/2017 03:43 PM, Maninder Singh wrote:
> Issue observed on ARM.
>
> Whenever there is switch from user mode, we end up with invalid last entry
> with some user space address as below:-
>
> save_stack+0x40/0xec
> __set_page_owner+0x2c/0x64
>
>
> __handle_domain_irq+0x9c/0x130
>
The driver probe path hits 'BUG_ON(entries != vpe_proxy.dev->nr_ites)'
on systems where it has VLPI capability, doesn't support direct LPI
feature and boot with a single CPU.
Relax the BUG_ON() condition to fix the issue.
Crash log messages on QDF2400 when booting with a single core.
---
On Fri, Oct 13, 2017 at 8:17 PM, Sudeep Holla wrote:
> On 13/10/17 15:12, Jassi Brar wrote:
>
>> In MHU the 32bits are tied together and all go to one target
>> processor. Whereas on QCom, each bit corresponds to independent signal
>> going to a different target processor.
>>
>
> I was not aware o
On Wed, Sep 27, 2017 at 03:28:38PM +0200, Eric Auger wrote:
> When the GITS_BASER.Valid gets cleared, the data structures in
> guest RAM are not provisionned anymore. The device, collection
provisioned
(but did you really mean valid?)
> and LPI lists store
On Fri, 13 Oct 2017, Michal Hocko wrote:
> I would, quite contrary, suggest a device specific mmap implementation
> which would guarantee both the best memory wrt. physical contiguous
> aspect as well as the placement - what if the device have a restriction
> on that as well?
Contemporary high en
On Fri, 13 Oct 2017 15:03:10 +
> Take off your "kernel" hat and put on a "customer" hat for a few moments
> while I try to put this in practical terms why the whitelist approach doesn't
> scale for what I'm trying to do.
As a customer I'm more worried about someone trashing my system or
breaki
Hi Peter,
Le Tuesday 10 Oct 2017 à 09:44:53 (+0200), Vincent Guittot a écrit :
> On 10 October 2017 at 09:29, Peter Zijlstra wrote:
> > On Mon, Oct 09, 2017 at 05:29:04PM +0200, Vincent Guittot wrote:
> >> On 9 October 2017 at 17:03, Vincent Guittot
> >> wrote:
> >> > On 1 September 2017 at 15:
On Thu, 12 Oct 2017, Josh Poimboeuf wrote:
> > Can you run SLUB with full debug? specify slub_debug on the commandline or
> > set CONFIG_SLUB_DEBUG_ON
>
> Oddly enough, with CONFIG_SLUB+slub_debug, I get the same crypto panic I
> got with CONFIG_SLOB. The trapping instruction is:
>
> vmovdqa 0x
Well, it actually occured to me that this would trigger the global oom
killer in case no memcg specific victim can be found which is definitely
not something we would like to do. This should work better. I am not
sure we can trigger this corner case but we should cover it and it
actually doesn't ma
On Fri, Oct 13, 2017 at 2:44 AM, Stefan Hajnoczi wrote:
> On Thu, Oct 12, 2017 at 09:20:26PM +0530, Pankaj Gupta wrote:
[..]
>> +#ifndef REQ_FLUSH
>> +#define REQ_FLUSH REQ_PREFLUSH
>> +#endif
>
> Is this out-of-tree kernel module compatibility stuff that can be
> removed?
Yes, this was copied fr
Hi Eric,
On Wed, Sep 27, 2017 at 03:28:39PM +0200, Eric Auger wrote:
> At the moment, the in-kernel emulated ITS is not properly reset.
> On guest restart/reset some registers keep their old values and
> internal structures like device, ITE, collection lists are not freed.
Am 13.10.2017 um 16:06 schrieb Steven Rostedt:
From: Steven Rostedt (VMware)
Commit e941759c74 ("fence: dma-buf cross-device synchronization") added
trace event fence_annotate_wait_on, but never used it. It was renamed
to dma_fence_annotate_wait_on by commit f54d186700 ("dma-buf: Rename
struct
On Fri 13-10-17 10:20:06, Cristopher Lameter wrote:
> On Fri, 13 Oct 2017, Michal Hocko wrote:
[...]
> > I am not really convinced this is a good interface. You are basically
> > trying to bypass virtual memory abstraction and that is quite
> > contradicting the mmap API to me.
>
> This is a stand
Hi again,
Vivien Didelot writes:
>>> How about using:
>>>
>>> union {
>>> struct net_device *master;
>>> struct net_device *slave;
>>> } netdev;
>> ...
>>
>> You can remove the 'netdev' all the compilers support unnamed unions.
>
> There are issues with older GCC
Commit-ID: 127a1bea40f7f2a36bc7207ea4d51bb6b4e936fa
Gitweb: https://git.kernel.org/tip/127a1bea40f7f2a36bc7207ea4d51bb6b4e936fa
Author: Steven Rostedt (VMware)
AuthorDate: Thu, 12 Oct 2017 18:06:19 -0400
Committer: Ingo Molnar
CommitDate: Fri, 13 Oct 2017 07:32:18 +0200
x86/fpu/debug:
From: Vivien Didelot
> Sent: 13 October 2017 02:41
> As for mv88e6xxx, setup the switch from within the mv88e6060 driver with
> a random MAC address, and remove the .set_addr implementation.
>
> Signed-off-by: Vivien Didelot
> ---
> drivers/net/dsa/mv88e6060.c | 30 +++---
Hi,
On Fri, Oct 13, 2017 at 3:41 AM, Jeffy Chen wrote:
> Currently we are suspending the spi master in it's ->suspend callback,
> which is racy as some other drivers may still want to transmit messages
> on the bus(e.g. spi based pwm backlight).
>
> Convert to late and early system PM callbacks t
Hello,
Can i trust an investment project in your country? accepted please send email
for more details.
Best Regards
Daria Yoong Shang
Hi,
On Fri, Oct 13, 2017 at 3:41 AM, Jeffy Chen wrote:
>
> Make edp display works on chromebook kevin.
>
>
> Jeffy Chen (2):
> spi: rockchip: Convert to late and early system PM callbacks
> arm64: dts: rockchip: Enable edp disaplay on kevin
>
> arch/arm64/boot/dts/rockchip/rk3399-gru-kevin.d
Hi Christoffer,
On 13/10/2017 17:19, Christoffer Dall wrote:
> On Wed, Sep 27, 2017 at 03:28:38PM +0200, Eric Auger wrote:
>> When the GITS_BASER.Valid gets cleared, the data structures in
>> guest RAM are not provisionned anymore. The device, collection
>
> provisioned
>
>
Here is simplified qemu command:
qemu-system-aarch64 \
-display none \
-kernel ./arch/arm64/boot/Image \
-M virt -cpu cortex-a57 -s -S
In a separate terminal start arm64 cross debugger:
$ aarch64-unknown-linux-gnu-gdb ./vmlinux
...
Reading symbols from ./vmlinux...done.
(gdb)
On Fri, Oct 13, 2017 at 07:58:09AM -0700, Christoph Hellwig wrote:
> On Fri, Oct 13, 2017 at 02:45:51PM +0200, Matias Bjørling wrote:
> > From: Rakesh Pandit
> >
> > When a virtual block device is formatted and mounted after creating
> > with "nvme lnvm create... -t pblk", a removal from "nvm lnv
On Fri, Oct 13, 2017 at 10:22:54AM -0500, Christopher Lameter wrote:
> On Thu, 12 Oct 2017, Josh Poimboeuf wrote:
>
> > > Can you run SLUB with full debug? specify slub_debug on the commandline or
> > > set CONFIG_SLUB_DEBUG_ON
> >
> > Oddly enough, with CONFIG_SLUB+slub_debug, I get the same cryp
Eric Biggers wrote:
> > static inline bool key_is_instantiated(const struct key *key)
> ...
> This should use 'smp_load_acquire(&key->state) == KEY_IS_INSTANTIATED',
I made a key_read_state() wrapper function that does this and then used it in
a bunch of places that read it, including this one.
From: Wei Yang [mailto:richard.weiy...@gmail.com]
> On Wed, Oct 11, 2017 at 04:39:40PM -0700, Andrew Morton wrote:
> >On Wed, 11 Oct 2017 10:33:39 +0800 Wei Yang
> >> BTW, I have another question on the implementation of radix tree.
> >>
> >> #Question: why 6 is one of the choice of RADIX_TREE_MAP_
On Wed, Sep 27, 2017 at 03:28:40PM +0200, Eric Auger wrote:
> On reset we clear the valid bits of GITS_CBASER and GITS_BASER.
> We also clear command queue registers and free the device,
> collection and lpi lists.
, and lpi lists.
(https://imgur.com/gallery/fycHx for your amusemnt)
Hi Christoffer,
On 13/10/2017 17:26, Christoffer Dall wrote:
> Hi Eric,
>
> On Wed, Sep 27, 2017 at 03:28:39PM +0200, Eric Auger wrote:
>> At the moment, the in-kernel emulated ITS is not properly reset.
>> On guest restart/reset some registers keep their old values and
>> internal structures lik
On Fri, 13 Oct 2017, Michal Hocko wrote:
> On Fri 13-10-17 10:20:06, Cristopher Lameter wrote:
> > On Fri, 13 Oct 2017, Michal Hocko wrote:
> [...]
> > > I am not really convinced this is a good interface. You are basically
> > > trying to bypass virtual memory abstraction and that is quite
> > >
From: Tvrtko Ursulin
It looks like all completions as created by flush_workqueue map
into a single lock class which creates lockdep false positives.
Example of a false positive:
[ 20.805315] ==
[ 20.805316] WARNING: possible circular loc
From: Kalle Valo
Date: Fri, 13 Oct 2017 10:25:14 +0300
> here's a pull request to net tree, more info in the signed tag below.
> Please let me know if there are any problems.
Pulled, thanks Kalle.
Den 07.10.2017 00.17, skrev Harsha Sharma:
Convert instances of dev_error to DRM_DEV_ERROR as we have
DRM_DEV_ERROR variants of drm print macros.
Signed-off-by: Harsha Sharma
---
Thanks, applied to drm-misc.
Noralf.
Changes in v3:
-Solve merge conflicts
Changes in v2:
-Fix alignment i
> -Original Message-
> From: Alan Cox [mailto:gno...@lxorguk.ukuu.org.uk]
> Sent: Friday, October 13, 2017 10:20 AM
> To: Limonciello, Mario
> Cc: g...@kroah.com; dvh...@infradead.org; andy.shevche...@gmail.com;
> linux-kernel@vger.kernel.org; platform-driver-...@vger.kernel.org;
> l...@ke
Hi Pavel,
On Fri, Oct 13, 2017 at 11:09:41AM -0400, Pavel Tatashin wrote:
> > It shouldn't be difficult to use section mappings with my patch, I just
> > don't really see the need to try to optimise TLB pressure when you're
> > running with KASAN enabled which already has something like a 3x slowd
A customer reported massive contention on the ncalls->lock in which
the workload is designed around nested epolls (where the fd is already
an epoll).
83.49% [kernel] [k] __pv_queued_spin_lock_slowpath
2.70% [kernel] [k] ep_call_nested.constprop.13
1.94% [kernel]
On Fri 13-10-17 10:42:37, Cristopher Lameter wrote:
> On Fri, 13 Oct 2017, Michal Hocko wrote:
>
> > On Fri 13-10-17 10:20:06, Cristopher Lameter wrote:
> > > On Fri, 13 Oct 2017, Michal Hocko wrote:
> > [...]
> > > > I am not really convinced this is a good interface. You are basically
> > > > tr
Hi Joerg,
On 20/09/17 15:13, Liviu Dudau wrote:
> If the IPMMU driver is compiled in the kernel it will replace the
> platform bus IOMMU ops on running the ipmmu_init() function, regardless
> if there is any IPMMU hardware present or not. This screws up systems
> that just want to build a generic
From: Thierry Reding
Hi Linus,
here's the latest series of patches that implement the tighter IRQ chip
integration. I've dropped the banked infrastructure for now as per the
discussion with Grygorii.
The first couple of patches are mostly preparatory work in order to
consolidate all IRQ chip re
From: Thierry Reding
In order to consolidate the multiple ways to associate an IRQ chip with
a GPIO chip, move more fields into the new struct gpio_irq_chip.
Signed-off-by: Thierry Reding
---
drivers/gpio/gpiolib.c | 14 +++---
include/linux/gpio/driver.h | 14 --
2 fi
From: Thierry Reding
Tegra186 has two GPIO controllers that are largely register compatible
between one another but are completely different from the controller
found on earlier generations.
Signed-off-by: Thierry Reding
---
drivers/gpio/Kconfig | 9 +
drivers/gpio/Makefile|
From: Thierry Reding
In order to consolidate the multiple ways to associate an IRQ chip with
a GPIO chip, move more fields into the new struct gpio_irq_chip.
Signed-off-by: Thierry Reding
---
Documentation/gpio/driver.txt | 4 ++--
drivers/gpio/gpio-aspeed.c | 4
From: Thierry Reding
Export these functions so that drivers can explicitly use these when
setting up their IRQ domain.
Signed-off-by: Thierry Reding
---
drivers/gpio/gpiolib.c | 8 +---
include/linux/gpio/driver.h | 4
2 files changed, 9 insertions(+), 3 deletions(-)
diff --git
From: Thierry Reding
Currently GPIO drivers are required to add the GPIO chip and its
corresponding IRQ chip separately, which can result in a lot of
boilerplate. Use the newly introduced struct gpio_irq_chip, embedded in
struct gpio_chip, that drivers can fill in if they want the GPIO core
to au
From: Thierry Reding
In order to consolidate the multiple ways to associate an IRQ chip with
a GPIO chip, move more fields into the new struct gpio_irq_chip.
Signed-off-by: Thierry Reding
---
drivers/gpio/gpiolib.c | 4 ++--
include/linux/gpio/driver.h | 9 +++--
2 files changed, 9 in
From: Thierry Reding
In order to consolidate the multiple ways to associate an IRQ chip with
a GPIO chip, move more fields into the new struct gpio_irq_chip.
Signed-off-by: Thierry Reding
---
drivers/gpio/gpiolib.c | 18 +-
include/linux/gpio/driver.h | 19 +++-
From: Thierry Reding
In order to consolidate the multiple ways to associate an IRQ chip with
a GPIO chip, move more fields into the new struct gpio_irq_chip.
Signed-off-by: Thierry Reding
---
drivers/gpio/gpiolib.c | 8
include/linux/gpio/driver.h | 9 +++--
2 files changed,
Hi,
On Fri, Oct 13, 2017 at 08:32:12AM -0700, Doug Anderson wrote:
> Hi,
>
> On Fri, Oct 13, 2017 at 3:41 AM, Jeffy Chen wrote:
> > Currently we are suspending the spi master in it's ->suspend callback,
> > which is racy as some other drivers may still want to transmit messages
> > on the bus(e.
Hi Linus,
The following changes since commit 8a5776a5f49812d29fe4b2d0a2d71675c3facf3f:
Linux 4.14-rc4 (2017-10-08 20:53:29 -0700)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu.git
tags/iommu-fixes-v4.14-rc4
for you to fetch changes up to
From: Thierry Reding
In order to consolidate the multiple ways to associate an IRQ chip with
a GPIO chip, move more fields into the new struct gpio_irq_chip.
Signed-off-by: Thierry Reding
---
Documentation/gpio/driver.txt | 2 +-
drivers/bcma/driver_gpio.c | 2
From: Thierry Reding
In order to consolidate the multiple ways to associate an IRQ chip with
a GPIO chip, move more fields into the new struct gpio_irq_chip.
Signed-off-by: Thierry Reding
---
drivers/gpio/gpiolib.c | 6 +++---
include/linux/gpio/driver.h | 11 ---
2 files changed
From: Thierry Reding
In order to consolidate the multiple ways to associate an IRQ chip with
a GPIO chip, move more fields into the new struct gpio_irq_chip.
Signed-off-by: Thierry Reding
---
drivers/pinctrl/mvebu/pinctrl-armada-37xx.c | 2 +-
include/linux/gpio/driver.h | 10
From: Thierry Reding
In order to consolidate the multiple ways to associate an IRQ chip with
a GPIO chip, move more fields into the new struct gpio_irq_chip.
Signed-off-by: Thierry Reding
---
drivers/gpio/gpiolib.c | 4 ++--
include/linux/gpio/driver.h | 11 ---
2 files changed,
From: Thierry Reding
This new structure will be used to group all fields related to interrupt
handling in a GPIO chip. Doing so will properly namespace these fields
and make it easier to distinguish which fields are used for IRQ support.
Signed-off-by: Thierry Reding
---
include/linux/gpio/dri
> Thanks for sharing the .config and tree. It looks like the problem is that
> kimg_shadow_start and kimg_shadow_end are not page-aligned. Whilst I fix
> them up in kasan_map_populate, they remain unaligned when passed to
> kasan_populate_zero_shadow, which confuses the loop termination conditions
Hi Tglx, Andy,
Sorry for old-posting,
2017-09-15 8:09 GMT+01:00 Thomas Gleixner :
> On Thu, 14 Sep 2017, Andy Lutomirski wrote:
>> On Thu, Sep 14, 2017 at 9:00 AM, Thomas Gleixner wrote:
>> > On Thu, 14 Sep 2017, Andy Lutomirski wrote:
>> >> On Thu, Sep 14, 2017 at 12:38 AM, Thomas Gleixner
>>
Just want to respond to this part first:
On Fri, Oct 13, 2017 at 03:03:10PM +, mario.limoncie...@dell.com wrote:
> Take off your "kernel" hat and put on a "customer" hat for a few moments
> while I try to put this in practical terms why the whitelist approach doesn't
> scale for what I'm tryin
On Fri, Oct 13, 2017 at 12:27 AM, Johan Hovold wrote:
> On Thu, Oct 12, 2017 at 11:13:21PM -0700, Andrey Smirnov wrote:
>> Add a driver for RAVE Supervisory Processor, an MCU implementing
>> varoius bits of housekeeping functionality (watchdoging, backlight
>> control, LED control, etc) on RAVE fa
On Fri, 13 Oct 2017, Harsha Sharma wrote:
> Done with following coccinelle patch
>
> @r@
> expression x;
> void* e;
> type T;
> identifier f;
> @@
> (
> *((T *)e)
> |
> ((T *)x)[...]
> |
> ((T*)x)->f
> |
>
> - (T*)
> e
> )
>
> Signed-off-by: Harsha Sharma
> ---
> drivers/gpu/drm/amd/po
On Fri, 13 Oct 2017, Michal Hocko wrote:
> > There is a generic posix interface that could we used for a variety of
> > specific hardware dependent use cases.
>
> Yes you wrote that already and my counter argument was that this generic
> posix interface shouldn't bypass virtual memory abstraction.
> On 13 Oct 2017, at 17.35, Rakesh Pandit wrote:
>
>> On Fri, Oct 13, 2017 at 07:58:09AM -0700, Christoph Hellwig wrote:
>>> On Fri, Oct 13, 2017 at 02:45:51PM +0200, Matias Bjørling wrote:
>>> From: Rakesh Pandit
>>>
>>> When a virtual block device is formatted and mounted after creating
>>>
BTW, don't we need the same aligments inside for_each_memblock() loop?
How about change kasan_map_populate() to accept regular VA start, end
address, and convert them internally after aligning to PAGE_SIZE?
Thank you,
Pavel
On Fri, Oct 13, 2017 at 11:54 AM, Pavel Tatashin
wrote:
>> Thanks for
> From: Vivien Didelot
> > Sent: 13 October 2017 02:41
> > As for mv88e6xxx, setup the switch from within the mv88e6060 driver with
> > a random MAC address, and remove the .set_addr implementation.
> >
> > Signed-off-by: Vivien Didelot
> > ---
> > drivers/net/dsa/mv88e6060.c | 30 +++
While implementing MAP_DIRECT, an mmap flag that arranges for an
FL_LAYOUT lease to be established, Al noted:
You are not even guaranteed that descriptor will remain be still
open by the time you pass it down to your helper, nevermind the
moment when event actually happens...
The firs
On 10/13, Konstantin Khlebnikov wrote:
>
> pid_t translate_pid(pid_t pid, int source, int target);
>
> This syscall converts pid from source pid-ns into pid in target pid-ns.
> If pid is unreachable from target pid-ns it returns zero.
>
> Pid-namespaces are referred file descriptors opened to proc
Hi Rob,
2017-10-13 22:49 GMT+09:00 Rob Herring :
> On Fri, Oct 06, 2017 at 02:02:58PM +0900, Keiji Hayashibara wrote:
>> Add uniphier-efuse dt-bindings documentation.
>>
>> Signed-off-by: Keiji Hayashibara
>> ---
>> .../devicetree/bindings/nvmem/uniphier-efuse.txt | 49
>> +++
On Fri, Oct 13, 2017 at 08:44:23AM -0600, Jens Axboe wrote:
> On 10/12/2017 06:19 PM, Ming Lei wrote:
> > On Thu, Oct 12, 2017 at 12:46:24PM -0600, Jens Axboe wrote:
> >> On 10/12/2017 12:37 PM, Ming Lei wrote:
> >>> For SCSI devices, there is often per-request-queue depth, which need
> >>> to be r
On Fri, 13 Oct 2017, Bhumika Goyal wrote:
> These structures are passed to the eeh_ops_register function during the
> initialization phase. There they get stored in a structure variable
> which only makes function calls through function pointers. There is no
> other usage of these eeh_ops struct
Certain SoCs need to map the MSI address in raise_irq.
To map an address, you first need to call pci_epc_mem_alloc_addr,
however, pci_epc_mem_alloc_addr calls ioremap (which can sleep).
Since raise_irq is only called from atomic context, we can't call
pci_epc_mem_alloc_addr from raise_irq, instead
Signed-off-by: Niklas Cassel
---
.../devicetree/bindings/pci/axis,artpec6-pcie.txt | 3 +-
drivers/pci/dwc/Kconfig| 41 +++--
drivers/pci/dwc/Makefile | 4 +-
drivers/pci/dwc/pcie-artpec6.c | 202 -
The ARTPEC-6 SoC and the ARTPEC-7 SoC are very similar.
Unfortunately, some fields in the PCIECFG and PCIESTAT
register have changed.
Signed-off-by: Niklas Cassel
---
.../devicetree/bindings/pci/axis,artpec6-pcie.txt | 2 +
drivers/pci/dwc/pcie-artpec6.c | 162
This is done to better match other drivers such as dra7xx and imx6,
but also to prepare for endpoint mode support.
Signed-off-by: Niklas Cassel
---
drivers/pci/dwc/pcie-artpec6.c | 59 +++---
1 file changed, 32 insertions(+), 27 deletions(-)
diff --git a/driv
There is no need to hard code the cpu to bus fixup address.
By calculating the sum of sizes of config, io and mem,
from device tree, we know how big the PCIe window is.
The bus address has to be inside of this range, so all bits in
the cpu address that are higher than this range, are the ones
that
Commit b015b37e6693 ("PCI: artpec6: Stop enabling writes to
DBI read-only registers") removed the only write using these
defines, but it did not remove the defines.
Remove the defines since they are now unused.
Signed-off-by: Niklas Cassel
---
drivers/pci/dwc/pcie-artpec6.c | 3 ---
1 file chang
This greatly improves readability.
Signed-off-by: Niklas Cassel
---
drivers/pci/dwc/pcie-artpec6.c | 34 +-
1 file changed, 17 insertions(+), 17 deletions(-)
diff --git a/drivers/pci/dwc/pcie-artpec6.c b/drivers/pci/dwc/pcie-artpec6.c
index 4b8ef266dc2f..18075e0f
On 10/13/2017 09:53 AM, Borislav Petkov wrote:
...
- if (copy_from_user(data, (void __user *)(uintptr_t)uaddr, len))
+ if (copy_from_user(data, (void __user *)uaddr, len))
goto e_free;
IIRC, typecast was needed for i386 build, but now we have depends on
X86_64 henc
From: Vivien Didelot
> Sent: 13 October 2017 16:29
> Vivien Didelot writes:
>
> >>> How about using:
> >>>
> >>> union {
> >>> struct net_device *master;
> >>> struct net_device *slave;
> >>> } netdev;
> >> ...
> >>
> >> You can remove the 'netdev' all the compilers suppor
On Fri, Oct 13, 2017 at 6:08 PM, Julia Lawall wrote:
>
>
> On Fri, 13 Oct 2017, Bhumika Goyal wrote:
>
>> These structures are passed to the eeh_ops_register function during the
>> initialization phase. There they get stored in a structure variable
>> which only makes function calls through functi
Previously, set_msi wrote all bits in the Message Control
register, thus overwriting the 64 bit address capable bit.
By clearing the 64 bit address capable bit, we break MSI
on systems where the RC has set a 64 bit MSI address.
Signed-off-by: Niklas Cassel
---
drivers/pci/dwc/pcie-designware-ep.
This is a series that adds:
- PCI endpoint mode support in the ARTPEC-6 driver.
- ARTPEC-7 SoC support in the ARTPEC-6 driver (the SoCs are very similar).
- Small fixes for MSI in designware-ep and designware-host,
needed to get endpoint mode support working for ARTPEC-6.
Niklas Cassel (10):
P
From: Mathieu Desnoyers
Test the new MEMBARRIER_CMD_PRIVATE_EXPEDITED and
MEMBARRIER_CMD_REGISTER_PRIVATE_EXPEDITED commands.
Add checks expecting specific error values on system calls expected to
fail.
Signed-off-by: Mathieu Desnoyers
Acked-by: Shuah Khan
Acked-by: Greg Kroah-Hartman
CC: Pe
Certain registers that pcie-designware-ep tries to write are read-only
registers. However, these registers can become read/write if we first
enable the DBI_RO_WR_EN bit.
Signed-off-by: Niklas Cassel
---
drivers/pci/dwc/pcie-designware-ep.c | 8
1 file changed, 8 insertions(+)
diff --gi
From: Mathieu Desnoyers
Architectures without membarrier hooks don't need to emit the
empty membarrier_arch_switch_mm() static inline when
CONFIG_MEMBARRIER=y.
Adapt the CONFIG_MEMBARRIER=n counterpart to only emit the empty
membarrier_arch_switch_mm() for architectures with membarrier hooks.
R
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