atomic_t variables are currently used to implement reference
counters with the following properties:
- counter is initialized to 1 using atomic_set()
- a resource is freed upon counter reaching zero
- once counter reaches zero, its further
increments aren't allowed
- counter schema uses basi
atomic_t variables are currently used to implement reference
counters with the following properties:
- counter is initialized to 1 using atomic_set()
- a resource is freed upon counter reaching zero
- once counter reaches zero, its further
increments aren't allowed
- counter schema uses basi
atomic_t variables are currently used to implement reference
counters with the following properties:
- counter is initialized to 1 using atomic_set()
- a resource is freed upon counter reaching zero
- once counter reaches zero, its further
increments aren't allowed
- counter schema uses basi
atomic_t variables are currently used to implement reference
counters with the following properties:
- counter is initialized to 1 using atomic_set()
- a resource is freed upon counter reaching zero
- once counter reaches zero, its further
increments aren't allowed
- counter schema uses basi
atomic_t variables are currently used to implement reference
counters with the following properties:
- counter is initialized to 1 using atomic_set()
- a resource is freed upon counter reaching zero
- once counter reaches zero, its further
increments aren't allowed
- counter schema uses basi
atomic_t variables are currently used to implement reference
counters with the following properties:
- counter is initialized to 1 using atomic_set()
- a resource is freed upon counter reaching zero
- once counter reaches zero, its further
increments aren't allowed
- counter schema uses basi
atomic_t variables are currently used to implement reference
counters with the following properties:
- counter is initialized to 1 using atomic_set()
- a resource is freed upon counter reaching zero
- once counter reaches zero, its further
increments aren't allowed
- counter schema uses basi
atomic_t variables are currently used to implement reference
counters with the following properties:
- counter is initialized to 1 using atomic_set()
- a resource is freed upon counter reaching zero
- once counter reaches zero, its further
increments aren't allowed
- counter schema uses basi
On Sun, Aug 13, 2017 at 08:34:56AM -0700, Andy Lutomirski wrote:
> > This specification defines a Uniform Resource Name namespace for
> > UUIDs (Universally Unique IDentifier), also known as GUIDs (Globally
> > Unique IDentifier).
>
> No, that still matches what I thought I knew: "UUID" and "GUID"
atomic_t variables are currently used to implement reference
counters with the following properties:
- counter is initialized to 1 using atomic_set()
- a resource is freed upon counter reaching zero
- once counter reaches zero, its further
increments aren't allowed
- counter schema uses basi
atomic_t variables are currently used to implement reference
counters with the following properties:
- counter is initialized to 1 using atomic_set()
- a resource is freed upon counter reaching zero
- once counter reaches zero, its further
increments aren't allowed
- counter schema uses basi
atomic_t variables are currently used to implement reference
counters with the following properties:
- counter is initialized to 1 using atomic_set()
- a resource is freed upon counter reaching zero
- once counter reaches zero, its further
increments aren't allowed
- counter schema uses basi
On Wed, 30 Aug 2017, Elena Reshetova wrote:
> atomic_as_refcounter.cocci script allows detecting
> cases when refcount_t type and API should be used
> instead of atomic_t.
>
> Signed-off-by: Elena Reshetova
Acked-by: Julia Lawall
> ---
> scripts/coccinelle/api/atomic_as_refcounter.cocci | 1
Hello Peter,
On (08/30/17 10:47), Peter Zijlstra wrote:
[..]
> On Wed, Aug 30, 2017 at 10:42:07AM +0200, Peter Zijlstra wrote:
> >
> > So the overhead looks to be spread out over all sorts, which makes it
> > harder to find and fix.
> >
> > stack unwinding is done lots and is fairly expensive, I
On Wed, Aug 30, 2017 at 01:55:10PM +0200, Christoffer Dall wrote:
> On Wed, Aug 30, 2017 at 12:31:41PM +0200, Andrew Jones wrote:
> > On Mon, Aug 28, 2017 at 08:18:50PM +0200, Christoffer Dall wrote:
> > > On Fri, Aug 04, 2017 at 08:44:04AM +0100, Marc Zyngier wrote:
> > > > On 31/07/17 18:26, Marc
On Tue, 29 Aug 2017 20:57:23 +0800
Li Bin wrote:
> The commit 9aaf5a5("perf probe: Check kprobes blacklist
> when adding new events"), perf probe supports checking
> the blacklist of the fuctions which can not be probed.
> But the checking condition is wrong, that the end_addr
> of the symbol whi
Hi Martin,
Replied in line.
- I don't understand why you go through all these hoops to decide
whether to use PRPs or IEEE scatterlists. If the firmware translation
is slow, why even bother with the SG format in the first place? Set
the max I/O size to match MDTS and you're done.
=> We wil
Hi Sakari,
Thanks for your time.
My comments below.
---
^Divagar
>-Original Message-
>From: Sakari Ailus [mailto:sakari.ai...@iki.fi]
>Sent: Wednesday, August 30, 2017 1:24 PM
>To: Mohandass, Divagar
>Cc: robh...@kernel.org; mark.rutl...@arm.com; w...@the-dreams.de;
>devicet...@vger.ker
On Tue 29-08-17 11:01:50, Roman Gushchin wrote:
[...]
> diff --git a/mm/memcontrol.c b/mm/memcontrol.c
> index b9cf3cf4a3d0..a69d23082abf 100644
> --- a/mm/memcontrol.c
> +++ b/mm/memcontrol.c
> @@ -1792,6 +1792,9 @@ static void refill_stock(struct mem_cgroup *memcg,
> unsigned int nr_pages)
>
Make this const as it is never modified.
Signed-off-by: Bhumika Goyal
---
fs/notify/dnotify/dnotify.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/fs/notify/dnotify/dnotify.c b/fs/notify/dnotify/dnotify.c
index 2430a04..cba3283 100644
--- a/fs/notify/dnotify/dnotify.c
+++
On Mon, Jul 31, 2017 at 08:20:25PM +0300, Andy Shevchenko wrote:
> Yep! There are so many conflicts that would be better just to push
> through your tree.
>
> I have just sent a v2 of this patch separately.
Greg, did you pick that patch up?
On Wed, Aug 30, 2017 at 12:32:07PM +, Mohandass, Divagar wrote:
> >> @@ -743,6 +770,15 @@ static int at24_probe(struct i2c_client *client,
> >> const struct i2c_device_id *id)
> >>
> >>i2c_set_clientdata(client, at24);
> >>
> >> + /* enable runtime pm */
> >> + pm_runtime_get_noresume(&cl
On Wed, Jul 26, 2017 at 02:27:44AM +0200, Rafael J. Wysocki wrote:
> > >> > Cc: "Rafael J. Wysocki"
> > >> > Cc: Mika Westerberg
> > >>
> > >> Acked-by: Mika Westerberg
> > >
> > > OK
> > >
> > > Andy, do you want me to apply this?
> >
> > If you would like to.
> >
> > The patch is now pretty
Thanks,
applied to the uuid for-next tree.
On Tue 29-08-17 22:33:03, Eric Biggers wrote:
> From: Eric Biggers
>
> Commit 7c051267931a ("mm, fork: make dup_mmap wait for mmap_sem for
> write killable") made it possible to kill a forking task while it is
> waiting to acquire its ->mmap_sem for write, in dup_mmap().
>
> However, it was over
On Wed, Aug 30, 2017 at 02:36:55PM +0200, Michal Hocko wrote:
> On Tue 29-08-17 11:01:50, Roman Gushchin wrote:
> [...]
> > diff --git a/mm/memcontrol.c b/mm/memcontrol.c
> > index b9cf3cf4a3d0..a69d23082abf 100644
> > --- a/mm/memcontrol.c
> > +++ b/mm/memcontrol.c
> > @@ -1792,6 +1792,9 @@ static
On Wed, 30 Aug 2017, Pavel Machek wrote:
> On Thu 2017-08-10 12:48:15, Miroslav Benes wrote:
> > If a task sleeps in a set of patched functions uninterruptibly, it could
> > block the whole transition process indefinitely. Thus it may be useful
> > to clear its TIF_PATCH_PENDING to allow the proc
>
> On Wed, 30 Aug 2017, Elena Reshetova wrote:
>
> > atomic_as_refcounter.cocci script allows detecting
> > cases when refcount_t type and API should be used
> > instead of atomic_t.
> >
> > Signed-off-by: Elena Reshetova
>
> Acked-by: Julia Lawall
Thank you very much Julia! What is the cor
Hi,
On 21-07-17 16:35, Quentin Schulz wrote:
From: Hans de Goede
Some sdio devices have a multiple stage bring-up process. Specifically
the esp8089 (for which an out of tree driver is available) loads firmware
on the first call to its sdio-drivers' probe function and then resets
the device cau
Add initial DT support for NanoPi NEO Plus2 by FriendlyARM
Allwinner quad core H5 Cortex A53 with an ARM Mali-450MP GPU
1 GB DDR3 RAM
8GB eMMC flash (Samsung KLM8G1WEPD-B031)
micro SD card slot
Gigabit Ethernet
From: Sahitya Tummala
There is a rare scenario in HW, where the first clear pulse could
be lost when the actual reset and clear/read of status register
are happening at the same time. Fix this by retrying upto 10 times
to ensure the status register gets cleared. Otherwise, this will
lead to a spu
Enable CONFIG_MMC_SDHCI_IO_ACCESSORS so that SDHC controller specific
register read and write APIs, if registered, can be used.
---
drivers/mmc/host/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index 2db84dd..64a9298 100644
--- a/d
Make this const as it is not modified anywhere.
Signed-off-by: Bhumika Goyal
---
drivers/usb/usbip/vhci_hcd.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/usb/usbip/vhci_hcd.c b/drivers/usb/usbip/vhci_hcd.c
index c747623..11b9a22 100644
--- a/drivers/usb/usbip/vhci
Register writes which change voltage of IO lines or turn the IO bus
on/off require controller to be ready before progressing further. When
the controller is ready, it will generate a power irq which needs to be
handled. The thread which initiated the register write should wait for
power irq to comp
On 30/08/17 12:46, Christoffer Dall wrote:
> On Wed, Aug 30, 2017 at 11:28:08AM +0100, Marc Zyngier wrote:
>> On 26/08/17 20:48, Christoffer Dall wrote:
>>> On Mon, Jul 31, 2017 at 06:26:19PM +0100, Marc Zyngier wrote:
Let's use the irq bypass mechanism introduced for platform device
inte
From: Sahitya Tummala
Add support API which will check if power irq is expected to be
generated and wait for the power irq to come and complete if the irq is
expected.
Signed-off-by: Sahitya Tummala
Signed-off-by: Vijay Viswanath
---
drivers/mmc/host/sdhci-msm.c | 124
There is a potential race between cgroup_exit() and the taskset
migration path. This race happens when all tasks associated
with the cg_list entries in mg_tasks, detach themselves
before the tasks can be attached to the destination cpuset in
cpuset_attach(). Below is the sequence where race is obse
There is a potential race between cgroup_exit() and the
migration path. This race happens because cgroup_exit path
reads the css_set and does cg_list empty check outside of
css_set lock. This can potentially race with the migrate path
trying to move the tasks to a different css_set. For instance,
b
On 20 August 2017 at 15:51, Steven Rostedt wrote:
> On Sat, 19 Aug 2017 19:10:35 +0100
> Ard Biesheuvel wrote:
>
>> To avoid the need for relocating absolute references to tracepoint
>> structures at boot time when running relocatable kernels (which may
>> take a disproportionate amount of space)
Hi Marc,
On 30/08/2017 12:42, Marc Zyngier wrote:
> Hi Eric,
>
> On 30/08/17 11:20, Auger Eric wrote:
>> Hi Marc,
>>
>> On 30/08/2017 11:42, Marc Zyngier wrote:
>>> On 26/08/17 20:48, Christoffer Dall wrote:
On Mon, Jul 31, 2017 at 06:26:19PM +0100, Marc Zyngier wrote:
> Let's use the ir
"Rafael J. Wysocki" writes:
> On Wednesday, August 30, 2017 12:34:55 PM CEST Punit Agrawal wrote:
>> Borislav Petkov writes:
>>
>> > On Tue, Aug 29, 2017 at 02:20:20PM +0100, Punit Agrawal wrote:
>> >> According to the ACPI specification, firmware is not required to provide
>> >> the Hardware E
On Wed, 16 Aug 2017, Josh Poimboeuf wrote:
> On Wed, Aug 16, 2017 at 04:50:07PM +0200, Petr Mladek wrote:
> > On Fri 2017-08-11 16:11:31, Josh Poimboeuf wrote:
> > > On Thu, Aug 10, 2017 at 12:48:12PM +0200, Miroslav Benes wrote:
> > > > Now there is a sysfs attribute called "force", which provide
Register writes which change voltage of IO lines or turn the IO bus on/off
require sdhc controller to be ready before progressing further. Once a
register write which affects IO lines is done, the driver should wait for
power irq from controller. Once the irq comes, the driver should acknowledge
th
From: Subhash Jadavani
SDCC controller reset (SW_RST) during probe may trigger power irq if
previous status of PWRCTL was either BUS_ON or IO_HIGH_V. So before we
enable the power irq interrupt in GIC (by registering the interrupt
handler), we need to ensure that any pending power irq interrupt s
On Wed 30-08-17 13:44:59, Roman Gushchin wrote:
> On Wed, Aug 30, 2017 at 02:36:55PM +0200, Michal Hocko wrote:
> > On Tue 29-08-17 11:01:50, Roman Gushchin wrote:
> > [...]
> > > diff --git a/mm/memcontrol.c b/mm/memcontrol.c
> > > index b9cf3cf4a3d0..a69d23082abf 100644
> > > --- a/mm/memcontrol.
On Wed, 16 Aug 2017, Petr Mladek wrote:
> On Thu 2017-08-10 12:48:12, Miroslav Benes wrote:
> > Currently, livepatch gradually migrate the system from an unpatched to a
> > patched state (or vice versa). Each task drops its TIF_PATCH_PENDING
> > itself when crossing the kernel/user space boundary
On Wed, Aug 30, 2017 at 8:25 PM, Byungchul Park wrote:
> On Wed, Aug 30, 2017 at 06:24:39PM +0900, Byungchul Park wrote:
>> > -Original Message-
>> > From: Peter Zijlstra [mailto:pet...@infradead.org]
>> > Sent: Wednesday, August 30, 2017 6:12 PM
>> > To: Byungchul Park
>> > Cc: mi...@kern
Make this const as it is not modified anywhere.
Signed-off-by: Bhumika Goyal
---
drivers/usb/host/imx21-hcd.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/usb/host/imx21-hcd.c b/drivers/usb/host/imx21-hcd.c
index e25d72e..39ae7fb 100644
--- a/drivers/usb/host/imx21
From: Ritesh Harjani
This adds CQHCI support for sdhci-msm platforms.
Signed-off-by: Ritesh Harjani
---
.../devicetree/bindings/mmc/sdhci-msm.txt | 1 +
drivers/mmc/host/Kconfig | 1 +
drivers/mmc/host/sdhci-msm.c | 90
From: Ritesh Harjani
Without this patch the CQHCI registers are getting reset
again.
Signed-off-by: Ritesh Harjani
---
drivers/mmc/host/cqhci.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/mmc/host/cqhci.c b/drivers/mmc/host/cqhci.c
index 8650a13..2a7351c
From: Ritesh Harjani
When CMDQ is halted the HW expects descriptor size to
be same which is using in CMDQ mode.
Thus adjust the desc_sz of sdhci accordingly.
Without this patch below command gives ADMA error
when CQE is enabled.
cat /sys/kernel/debug/mmc0/mmc0:0001/ext_csd
Signed-off-by: Ritesh
From: Ritesh Harjani
There is a case when enabling the legacy IRQs and halting CQE is
resuling into a command response interrupt without any command in
progress. This patch handles such case here.
Error signature without this patch:-
mmc0: Got command interrupt 0x0001 even though no command
From: Ritesh Harjani
Hi All,
This is RFC patch series based on top of ulfh_mmc/cmdq branch
which is based upon Adrian's CMDQ patch series.
Below patch series enables CQE for sdhci-msm platform.
This has been tested on internal 8996 MTP which has CMDQ support.
Fixes w.r.t. CMDQ:-
There are some
On Wed, Aug 30, 2017 at 02:55:43PM +0200, Michal Hocko wrote:
> On Wed 30-08-17 13:44:59, Roman Gushchin wrote:
> > On Wed, Aug 30, 2017 at 02:36:55PM +0200, Michal Hocko wrote:
> > > On Tue 29-08-17 11:01:50, Roman Gushchin wrote:
> > > [...]
> > > > diff --git a/mm/memcontrol.c b/mm/memcontrol.c
On Tuesday 29 August 2017 10:33 PM, James Morse wrote:
Hi Pratyush,
(Nit: get_maintainer.pl will give you the list of people to CC, you're reliant
on the maintainers being eagle-eyed to spot this!)
I noticed it after sending. I do use it, but there was a bug in my cccmd
script. I have fixed
Hi Vineet,
On Mon, 28 Aug 2017 15:28:32 -0700 Vineet Gupta
wrote:
>
> On 08/28/2017 03:23 PM, Stephen Rothwell wrote:
> >
> > Commit
> >
> >279921e080b9 ("ARCv2: SLC: provide a line based flush routine for
> > debugging")
> >
> > is missing a Signed-off-by from its author and committer.
> >
Hi All,
Please ignore the previous patch series from a wrong email
address. Stupid gitconfig issue. Apologies for the spam.
This is RFC patch series based on top of ulfh_mmc/cmdq branch
which is based upon Adrian's CMDQ patch series.
Below patch series enables CQE for sdhci-msm platform.
This ha
Without this patch the CQHCI registers are getting reset
again.
Signed-off-by: Ritesh Harjani
---
drivers/mmc/host/cqhci.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/mmc/host/cqhci.c b/drivers/mmc/host/cqhci.c
index 8650a13..2a7351c 100644
--- a/drivers/mm
This adds CQHCI support for sdhci-msm platforms.
Signed-off-by: Ritesh Harjani
---
.../devicetree/bindings/mmc/sdhci-msm.txt | 1 +
drivers/mmc/host/Kconfig | 1 +
drivers/mmc/host/sdhci-msm.c | 90 +-
3 files changed
There is a case when enabling the legacy IRQs and halting CQE is
resuling into a command response interrupt without any command in
progress. This patch handles such case here.
Error signature without this patch:-
mmc0: Got command interrupt 0x0001 even though no command operation
was in progre
When CMDQ is halted the HW expects descriptor size to
be same which is using in CMDQ mode.
Thus adjust the desc_sz of sdhci accordingly.
Without this patch below command gives ADMA error
when CQE is enabled.
cat /sys/kernel/debug/mmc0/mmc0:0001/ext_csd
Signed-off-by: Ritesh Harjani
---
drivers/
Em Wed, Aug 30, 2017 at 04:41:13PM +0800, Jin, Yao escreveu:
> Hi Arnaldo,
>
> Andi has reviewed this patch yet.
>
> https://patchwork.kernel.org/patch/9884399/
>
> Is this patch OK for merging or any other comments?
Thanks, applied together with Andi's reviewed-by tag,
- Arnaldo
> Thanks
>
On Wed, 30 Aug 2017, Reshetova, Elena wrote:
>
> >
> > On Wed, 30 Aug 2017, Elena Reshetova wrote:
> >
> > > atomic_as_refcounter.cocci script allows detecting
> > > cases when refcount_t type and API should be used
> > > instead of atomic_t.
> > >
> > > Signed-off-by: Elena Reshetova
> >
> > A
Hi all,
Commit
1a9f9af07e80 ("ARM: dts: at91: at91sam9g45: add AC97")
is missing a Signed-off-by from its author.
--
Cheers,
Stephen Rothwell
On Wed, 2017-08-30 at 14:38 +0200, Christoph Hellwig wrote:
> On Mon, Jul 31, 2017 at 08:20:25PM +0300, Andy Shevchenko wrote:
> > Yep! There are so many conflicts that would be better just to push
> > through your tree.
> >
> > I have just sent a v2 of this patch separately.
>
> Greg, did you pi
On Wed, Aug 30, 2017 at 02:38:45PM +0200, Christoph Hellwig wrote:
> On Mon, Jul 31, 2017 at 08:20:25PM +0300, Andy Shevchenko wrote:
> > Yep! There are so many conflicts that would be better just to push
> > through your tree.
> >
> > I have just sent a v2 of this patch separately.
>
> Greg, did
On Mon, Aug 28, 2017 at 11:47:27PM +0530, Bhumika Goyal wrote:
> Make these const as they are not modified anywhere.
>
> Signed-off-by: Bhumika Goyal
> ---
> drivers/iommu/ipmmu-vmsa.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Applied, thanks.
Since commit 7401bc18d1ee ("scsi: qla2xxx: Add FC-NVMe command handling")
we make use of 'struct nvmefc_fcp_req' in qla24xx_nvme_iocb_entry() without
including linux/nvme-fc-driver.h where it is defined.
Add linux/nvme-fc-driver.h (and scsi/fc/fc_fs.h as nvme-fc-driver.h needs
the definition of 's
On 21 August 2017 at 09:41, Kishon Vijay Abraham I wrote:
> From: Adrian Hunter
>
> Read each register only once and move the code to a separate function so
> that it is not jammed against the 80 column margin.
>
> Signed-off-by: Adrian Hunter
> Signed-off-by: Kishon Vijay Abraham I
Thanks, ap
On 21 August 2017 at 09:41, Kishon Vijay Abraham I wrote:
> TI's implementation of sdhci controller used in DRA7 SoC's has
> CRC in responses with length 136 bits. Add quirk to indicate
> the controller has CRC in MMC_RSP_136. If this quirk is
> set sdhci library shouldn't shift the response prese
On 23 August 2017 at 06:14, Masahiro Yamada
wrote:
>
> [1] implements suspend / resume for sdhci-cadence.c
>
> [2] refactor sdhci-pxav2
>
> [3] add clk handling for suspend/resume hooks of sdhci-pltfm.
> This also cleans up sdhci-brcmstb.c and sdhci-sirf.c
>
> [4] export sdhci_pltfm_suspend/re
On 23 August 2017 at 18:30, Arvind Yadav wrote:
> amba_id are not supposed to change at runtime. All functions
> working with const amba_id. So mark the non-const structs as const.
>
> Signed-off-by: Arvind Yadav
Thanks, applied for next!
Kind regards
Uffe
> ---
> drivers/mmc/host/mmci.c | 2
On 28 August 2017 at 16:29, Jerome Brunet wrote:
> The patchset features several bugfixes, rework and upgrade for the
> meson-gx MMC driver.
>
> The main goal is to improve readability and enable new high speed
> modes, such as eMMC DDR52 and sdcard UHS modes up to SDR50 (100Mhz)
>
> SDR104 is not
On 30 August 2017 at 14:22, wrote:
> From: Srinivas Kandagatla
>
> It does not make sense for qcom dml code to be a seperate module, as
> this has just 2 helper functions specific to qcom, and used directly by
> mmci driver, so just compile this along with main mmci driver.
>
> This would also f
On Mon, Aug 28, 2017 at 05:42:05PM +0530, Arvind Yadav wrote:
> iommu_ops are not supposed to change at runtime.
> Functions 'iommu_device_set_ops' and 'bus_set_iommu' working with
> const iommu_ops provided by . So mark the non-const
> structs as const.
>
> Signed-off-by: Arvind Yadav
> ---
> d
On Wed, 30 Aug 2017 13:52:26 +0100
Ard Biesheuvel wrote:
> On 20 August 2017 at 15:51, Steven Rostedt wrote:
> > On Sat, 19 Aug 2017 19:10:35 +0100
> > Ard Biesheuvel wrote:
> >
> >> To avoid the need for relocating absolute references to tracepoint
> >> structures at boot time when running r
On Mon, Aug 28, 2017 at 05:42:26PM +0530, Arvind Yadav wrote:
> iommu_ops are not supposed to change at runtime.
> Functions 'iommu_device_set_ops' and 'bus_set_iommu' working with
> const iommu_ops provided by . So mark the non-const
> structs as const.
>
> Signed-off-by: Arvind Yadav
> ---
> d
- Original Message -
| rhashtable_params are not supposed to change at runtime. All
| Functions rhashtable_* working with const rhashtable_params
| provided by . So mark the non-const structs
| as const.
|
| Signed-off-by: Arvind Yadav
| ---
Hi,
Thanks. This is now pushed to the for-next
On 30 August 2017 at 14:17, Steven Rostedt wrote:
> On Wed, 30 Aug 2017 13:52:26 +0100
> Ard Biesheuvel wrote:
>
>> On 20 August 2017 at 15:51, Steven Rostedt wrote:
>> > On Sat, 19 Aug 2017 19:10:35 +0100
>> > Ard Biesheuvel wrote:
>> >
>> >> To avoid the need for relocating absolute reference
On 30/08/2017 at 23:07:12 +1000, Stephen Rothwell wrote:
> Hi all,
>
> Commit
>
> 1a9f9af07e80 ("ARM: dts: at91: at91sam9g45: add AC97")
>
> is missing a Signed-off-by from its author.
>
Oh crap, it was the only one not in linux-next... iThe original
submission had the SoB:
https://patchwork
Refactor code in order to avoid identical code for different branches.
This issue was detected with the help of Coccinelle.
Addresses-Coverity-ID: 1226761
Signed-off-by: Gustavo A. R. Silva
---
This issue was reported by Coverity and it was tested by compilation only.
Please, verify if any of th
Hi Dave,
Thank you for acking.
The reason I am not doing initializing stores is because they require a
membar, even if only regular stores are following (I hoped to do a
membar before first load). This is something I was thinking was not
true, but after consulting with colleagues and checking
On Mon, Aug 28, 2017 at 05:42:50PM +0530, Arvind Yadav wrote:
> iommu_ops are not supposed to change at runtime.
> Functions 'bus_set_iommu' working with const iommu_ops provided
> by . So mark the non-const structs as const.
>
> Signed-off-by: Arvind Yadav
> ---
> drivers/iommu/s390-iommu.c | 2
Hi Huacai,
On 29/08/17 02:43, Huacai Chen wrote:
I suggest to drop sync_r4k completely, because it is inaccurate. You
can use IPI to synchronize count/compare instead, as Loongson-3 does.
I am all for a better fix, such as this - but that would be a much more
invasive change than what I propo
On Wed, Aug 30, 2017 at 09:19:14AM +0800, honghui.zh...@mediatek.com wrote:
> From: Honghui Zhang
>
> Switch from using a custom NUM_INTX macro to the generic PCI_NUM_INTX
> definition for the number of INTx interrupts.
>
> Signed-off-by: Honghui Zhang
I rebased pci/host-mediatek on top of pci
kfree on NULL pointer is a no-op and therefore checking is redundant.
Signed-off-by: Himanshu Jha
---
drivers/gpu/drm/gma500/cdv_intel_dp.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/gma500/cdv_intel_dp.c
b/drivers/gpu/drm/gma500/cdv_intel_dp.c
ind
On Tue, Aug 29, 2017 at 02:59:12PM -0500, Josh Poimboeuf wrote:
> On Tue, Aug 29, 2017 at 03:22:06PM -0400, Joe Lawrence wrote:
> > On 08/29/2017 11:49 AM, Josh Poimboeuf wrote:
> > > On Fri, Aug 25, 2017 at 03:10:00PM -0400, Joe Lawrence wrote:
> > >> +Test 6
> > >> +--
> > >> +
> > >> +Test a
On Wed, Aug 30, 2017 at 2:57 AM, Pavel Machek wrote:
> The command line is visible to unpriviledged userspace (/proc/cmdline,
> dmesg). Is that a problem?
These files are not exposed to untrusted processes on Android.
--
Nick Kralevich | Android Security | n...@google.com | 650.214.4037
Hi,
The following patch was sent a while back by Wolfgang Bumiller to remap cpusets
for a whole subtree in a cgroup v1 cpuset hierarchy. The fact that currently
this is not possible in a non-racy why is a pretty big limitation. This is
especially true for nested containers. Where the nested contai
Three minor fixes: a NULL deref in qedf, an off by one in sg and a fix
to IPR to prevent an error on initialisation.
The patch is available here:
git://git.kernel.org/pub/scm/linux/kernel/git/jejb/scsi.git scsi-fixes
The short changelog is:
Brian King (1):
scsi: ipr: Set no_report_opcodes
Hi Jeffy,
Am Donnerstag, 24. August 2017, 12:52:23 CEST schrieb Jeffy Chen:
> Currently the rt5514 i2c driver and rt5514 spi driver are using the same
> compatible string.
>
> Add additional unused compatible strings to identify them for Gru
> boards.
>
> Signed-off-by: Jeffy Chen
> ---
>
> Ch
Hi Filippo,
please change the subject to:
iommu/vt-d: Don't be too aggressive when clearing one context entry
to follow the convention used in the iommu-tree. Another comment below.
On Mon, Aug 28, 2017 at 04:16:29PM +0200, Filippo Sironi wrote:
> static void domain_context_clear_one(s
kfree on NULL pointer is a no-op and therefore checking is redundant.
Signed-off-by: Himanshu Jha
---
drivers/gpu/drm/i915/intel_opregion.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_opregion.c
b/drivers/gpu/drm/i915/intel_opregion.c
ind
On 08/30/2017 01:32 AM, Colin King wrote:
From: Colin Ian King
Don't populate the arrays on the stack, instead make them static.
Makes the object code smaller by over 950 bytes:
Before:
text data bss dec hex filename
26144 18768 352 45264b0d0 dri
On 30 August 2017 at 03:34, Shawn Lin wrote:
> The intention of this patch is to move dev_pm_domain_detach after
> devres_release_all to avoid possible accessing device's registers
> with genpd been powered off.
>
> Many common IP drivers use devm_request_irq to request irq for either
> shared irq
On 08/30/2017 02:48 AM, Hans de Goede wrote:
Anything higher then 5V may damage hardware not capable of it, so
the only sane default here is 5V. If a board is able to handle a
higher voltage that should come from board specific data such as
device-tree and not be hard coded into the fusb302 code.
On 08/30/2017 01:47 PM, Colin King wrote:
From: Colin Ian King
Trivial fix to typo in printf error message
Signed-off-by: Colin Ian King
For net-next; looks like there is also one in "failed to listeen\n".
Want to fix this one as well ? ;)
Acked-by: Daniel Borkmann
On 30 August 2017 at 14:44, Hans de Goede wrote:
> Hi,
>
>
> On 21-07-17 16:35, Quentin Schulz wrote:
>>
>> From: Hans de Goede
>>
>> Some sdio devices have a multiple stage bring-up process. Specifically
>> the esp8089 (for which an out of tree driver is available) loads firmware
>> on the first
On 08/30/2017 02:48 AM, Hans de Goede wrote:
This is board specific info so it should come from board config, such
as devicetree.
I've chosen to prefix these with "fcs," treating them as fusb302 driver
specific for now. We may want to revisit this and replace these with
properties which are part
On Wednesday, August 30, 2017 2:41:41 PM CEST Christoph Hellwig wrote:
> On Wed, Jul 26, 2017 at 02:27:44AM +0200, Rafael J. Wysocki wrote:
> > > >> > Cc: "Rafael J. Wysocki"
> > > >> > Cc: Mika Westerberg
> > > >>
> > > >> Acked-by: Mika Westerberg
> > > >
> > > > OK
> > > >
> > > > Andy, do yo
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