From: Arvind Yadav
Date: Wed, 23 Aug 2017 16:22:20 +0530
> genl_ops are not supposed to change at runtime. All functions
> working with genl_ops provided by work with
> const genl_ops. So mark the non-const structs as const.
>
> Signed-off-by: Arvind Yadav
Applied.
From: Stefano Brivio
Date: Wed, 23 Aug 2017 13:27:13 +0200
> inet_diag_msg_sctp{,l}addr_fill() and sctp_get_sctp_info() copy
> sizeof(sockaddr_storage) bytes to fill in sockaddr structs used
> to export diagnostic information to userspace.
>
> However, the memory allocated to store sockaddr info
From: Colin King
Date: Wed, 23 Aug 2017 12:59:48 +0100
> From: Colin Ian King
>
> iph is being assigned the same value twice; remove the redundant
> first assignment. (Thanks to Nikolay Aleksandrov for pointing out
> that the first asssignment should be removed and not the second)
>
> Fixes wa
From: Joonsoo Kim
Freepage on ZONE_HIGHMEM doesn't work for kernel memory so it's not that
important to reserve. When ZONE_MOVABLE is used, this problem would
theorectically cause to decrease usable memory for GFP_HIGHUSER_MOVABLE
allocation request which is mainly used for page cache and anon pa
'ldrd/strd' (load/store doublewords) instructions are 64bit atomic as
long as the address is 64-bit aligned on LPAE (Large Physical Address
Extension) enabled architectures. This feature is to guarantee atomic
accesses on newly introduced 64bit wide descriptors in the translation
tables.
Making
On some 32-bit architectures, 64bit accesses are atomic when certain
conditions are satisfied.
For example, on LPAE (Large Physical Address Extension) enabled ARM
architecture, 'ldrd/strd' (load/store doublewords) instructions are 64bit
atomic as long as the address is 64-bit aligned. This featu
On some 32-bit architectures, 64bit accesses are atomic when certain
conditions are satisfied.
For example, on LPAE (Large Physical Address Extension) enabled ARM
architecture, 'ldrd/strd' (load/store doublewords) instructions are 64bit
atomic as long as the address is 64-bit aligned. This featur
'min_vruntime_copy' is copied when 'min_vruntime' is updated for cfq_rq
and used to check if updating 'min_vruntime' is completed on reader side.
Because 'min_vruntime' variable is 64bit, we need a mimic of seqlock to
check if the variable is not being updated on 32bit machines.
On 64BIT_ATOMIC
On 2017-08-21 12:34, Pierre Yves MORDRET wrote:
> OK. I will redesign my driver to take into account this idea.
>
> I believe I should get rid of my custom API in DMA for channelID as well.
> Please
> confirm. Not very clear for me whether I can keep it or not.
Yes, you should be able to get r
On 23.8.2017 12:55, Shubhrajyoti Datta wrote:
> Signed-off-by: Shubhrajyoti Datta
Empty commit message?
What's the reason for this change?
M
> ---
> drivers/tty/serial/xilinx_uartps.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/tty/serial/xilinx_uartps.c
Hi Martin,
After merging the scsi-mkp tree, today's linux-next build (powerpc
ppc64_defconfig) produced this warning:
drivers/scsi/lpfc/lpfc_nvmet.c:1457:1: warning: 'lpfc_nvmet_replenish_context'
defined but not used [-Wunused-function]
lpfc_nvmet_replenish_context(struct lpfc_hba *phba,
^
I
Hi all,
[Just adding Dick and James to the cc list]
On Thu, 24 Aug 2017 15:57:56 +1000 Stephen Rothwell
wrote:
>
> After merging the scsi-mkp tree, today's linux-next build (powerpc
> ppc64_defconfig) produced this warning:
>
> drivers/scsi/lpfc/lpfc_nvmet.c:1457:1: warning:
> 'lpfc_nvmet_rep
Check memory allocation failure and return -ENOMEM in such a case.
Signed-off-by: Christophe JAILLET
---
drivers/media/i2c/smiapp/smiapp-core.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/media/i2c/smiapp/smiapp-core.c
b/drivers/media/i2c/smiapp/smiapp-core.c
index aff55e1dffe
On Tue, 2017-08-22 at 10:37 +0300, Luca Coelho wrote:
> From: Luca Coelho
>
> Work queues cannot be allocated when a mutex is held because the mutex
> may be in use and that would make it sleep. Doing so generates the
> following splat with 4.13+:
>
> [ 19.513298]
On 08/20, icen...@aosc.io wrote:
>在 2017-08-20 08:59，kbuild test robot 写道：
>>Hi Chen-Yu,
>>
>>[auto build test ERROR on robh/for-next]
>>[also build test ERROR on v4.13-rc5 next-20170817]
>>[if your patch is applied to the wrong git tree, please drop us a note
>>to help improve the system]
>
>In fa
On Wed, Aug 23, 2017 at 11:13:04PM +0800, icen...@aosc.io wrote:
> 在 2017-08-23 22:35，Maxime Ripard 写道：
> > On Wed, Aug 23, 2017 at 07:56:29PM +0800, icen...@aosc.io wrote:
> > > > > + reg = <0x01c0f000 0x1000>;
> > > > > + clocks = <&ccu CLK_BUS_MMC0>, <&ccu
On 24/08/17 00:27, Boris Ostrovsky wrote:
> Commit aba831a69632 ("xen: remove tests for pvh mode in pure pv paths")
> removed XENFEAT_auto_translated_physmap test in xen_alloc_p2m_entry()
> since it is assumed that the routine is never called by non-PV guests.
>
> However, alloc_xenballooned_pages
On Wed, Aug 23, 2017 at 07:47:14PM +0200, Peter Zijlstra wrote:
> Those are fine and are indeed the flush_work() vs work inversion.
>
> The two straight forward annotations are:
>
> flush_work(work) process_one_work(wq, work)
> A(work) A(work)
> R(work) work->
Hello,
after reading the NFS(5) manpage and doing some searching through the
mailing list archive (of course, due to it being ubiquitous in posted
logs, searching for "addr" and "clientaddr" was a bit hopeless) I have
come to conclude that NFS does not have an option for explicitly
specifying
Hi Yong,
[auto build test WARNING on iommu/next]
[also build test WARNING on next-20170823]
[cannot apply to v4.13-rc6]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day-ci/linux/commits/Yong-Wu/MT2712-IOMMU
在 2017-08-24 14:07，Maxime Ripard 写道：
On Wed, Aug 23, 2017 at 11:13:04PM +0800, icen...@aosc.io wrote:
在 2017-08-23 22:35，Maxime Ripard 写道：
> On Wed, Aug 23, 2017 at 07:56:29PM +0800, icen...@aosc.io wrote:
> > > > + reg = <0x01c0f000 0x1000>;
> > > > + clocks
snd_ac97_res_table are not supposed to change at runtime. All functions
working with snd_ac97_res_table provided by work with
const snd_ac97_res_table. So mark the non-const structs as const.
Signed-off-by: Arvind Yadav
---
sound/pci/nm256/nm256.c | 2 +-
1 file changed, 1 insertion(+), 1 delet
On 2017/8/23 18:37, Hans Verkuil wrote:
On 08/22/17 09:30, wenyou.y...@microchip.com wrote:
Hi Hans,
-Original Message-
From: Hans Verkuil [mailto:hverk...@xs4all.nl]
Sent: 2017年8月22日 15:00
To: Wenyou Yang - A41535 ; Mauro Carvalho
Chehab
Cc: Nicolas Ferre - M43238 ; linux-
ker...@v
This adds support for reading and writing date/time from/to ds1341 chip.
ds1341 chip has other features - alarms, input clock (can be used instead
of intercal oscillator for better accuracy), output clock ("square wave
generation"). However, not all of that is available at the same time.
Same chip
On Mon, Aug 14 2017, NeilBrown wrote:
> On Fri, Aug 11 2017, Trond Myklebust wrote:
>
>> On Fri, 2017-08-11 at 14:31 +1000, NeilBrown wrote:
>>> Funny story. 4.5 years ago we discarded the FS_REVAL_DOT superblock
>>> flag and introduced the d_weak_revalidate dentry operation instead.
>>> We duly
From: Joonsoo Kim
This patchset is the follow-up of the discussion about the
"Introduce ZONE_CMA (v7)" [1]. Please reference it if more information
is needed.
In this patchset, the memory of the CMA area is managed by using
the ZONE_MOVABLE. Since there is another type of the memory in this zone
From: Joonsoo Kim
Now, all reserved pages for CMA region are belong to the ZONE_MOVABLE
and it only serves for a request with GFP_HIGHMEM && GFP_MOVABLE.
Therefore, we don't need to maintain ALLOC_CMA at all.
Reviewed-by: Aneesh Kumar K.V
Acked-by: Vlastimil Babka
Signed-off-by: Joonsoo Kim
-
From: Joonsoo Kim
CMA area is now managed by the separate zone, ZONE_MOVABLE,
to fix many MM related problems. In this implementation, if
CONFIG_HIGHMEM = y, then ZONE_MOVABLE is considered as HIGHMEM and
the memory of the CMA area is also considered as HIGHMEM.
That means that they are considere
From: Joonsoo Kim
0. History
This patchset is the follow-up of the discussion about the
"Introduce ZONE_CMA (v7)" [1]. Please reference it if more information
is needed.
1. What does this patch do?
This patch changes the management way for the memory of the CMA area
in the MM subsystem. Curren
Power9 introduces a hardware subsystem referred to as the Virtual
Accelerator Switchboard (VAS). VAS allows kernel subsystems and user
space processes to directly access the Nest Accelerator (NX) engines
which implement compression and encryption algorithms in the hardware.
NX has been in Power pr
Define some helper functions to access the MMIO regions. We use these
in follow-on patches to read/write VAS hardware registers. They are
also used to later issue 'paste' instructions to submit requests to
the NX hardware engines.
Signed-off-by: Sukadev Bhattiprolu
---
Changelog [v6]:
- M
Define macros for the VAS hardware registers and bit-fields as well
as couple of data structures needed by the VAS driver.
Signed-off-by: Sukadev Bhattiprolu
---
Changelog[v7]
- Move the threshold control macros from uapi/asm/vas.h to
asm/vas.h for now. When we actually have an
Define helpers to allocate/free VAS window objects. These will
be used in follow-on patches when opening/closing windows.
Signed-off-by: Sukadev Bhattiprolu
---
arch/powerpc/platforms/powernv/vas-window.c | 70 +
1 file changed, 70 insertions(+)
diff --git a/arch/pow
Define the vas_win_close() interface which should be used to close a
send or receive windows.
While the hardware configurations required to open send and receive windows
differ, the configuration to close a window is the same for both. So we use
a single interface to close the window.
Signed-off-
Define an interface that the NX drivers can use to find the physical
paste address of a send window. This interface is expected to be used
with the mmap() operation of the NX driver's device. i.e the user space
process can use driver's mmap() operation to map the send window's paste
address into th
Define an interface to open a VAS send window. This interface is
intended to be used the Nest Accelerator (NX) driver(s) to open
a send window and use it to submit compression/encryption requests
to a VAS receive window.
The receive window, identified by the [vasid, cop] parameters, must
already b
Define an interface to return a system-wide unique id for a given VAS
window.
The vas_win_id() will be used in a follow-on patch to generate an unique
handle for a user space receive window. Applications can use this handle
to pair send and receive windows for fast thread-wakeup.
The hardware ref
Define the vas_rx_win_open() interface. This interface is intended to be
used by the Nest Accelerator (NX) driver(s) to setup receive windows for
one or more NX engines (which implement compression/encryption algorithms
in the hardware).
Follow-on patches will provide an interface to close the win
Define interfaces (wrappers) to the 'copy' and 'paste' instructions
(which are new in PowerISA 3.0). These are intended to be used to
by NX driver(s) to submit Coprocessor Request Blocks (CRBs) to the
NX hardware engines.
Signed-off-by: Sukadev Bhattiprolu
---
Changelog[v4]
- Export symb
Define helpers to initialize window context registers of the VAS
hardware. These will be used in follow-on patches when opening/closing
VAS windows.
Signed-off-by: Sukadev Bhattiprolu
---
Changelog[v6]
- Add support for FTW windows and drop the fault window id
code since it is n
Move the GET_FIELD and SET_FIELD macros to vas.h as VAS and other
users of VAS, including NX-842 can use those macros.
There is a lot of related code between the VAS/NX kernel drivers
and skiboot. For consistency, switch the order of parameters in
SET_FIELD to match the order in skiboot.
Signed-o
Implement vas_init() and vas_exit() functions for a new VAS module.
This VAS module is essentially a library for other device drivers
and kernel users of the NX coprocessors like NX-842 and NX-GZIP.
In the future this will be extended to add support for user space
to access the NX coprocessors.
VA
On 08/24/2017 08:25 AM, Yang, Wenyou wrote:
>
>
> On 2017/8/23 18:37, Hans Verkuil wrote:
>> On 08/22/17 09:30, wenyou.y...@microchip.com wrote:
>>> Hi Hans,
>>>
-Original Message-
From: Hans Verkuil [mailto:hverk...@xs4all.nl]
Sent: 2017年8月22日 15:00
To: Wenyou Yang -
Some manufacturers may use different bit to set QE on
different memories.
The GD25Q256 from GigaDevice is a example, which uses S6(bit 6
of the Status Register-1) to set QE, which is different with
other supported memories from GigaDevice that use S9(bit 1 of
the Status Register-2). This makes it
Add support for GD25Q256, a 32MiB SPI Nor flash
from GigaDevice.
Signed-off-by: Andy Yan
---
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
drivers/mtd/spi-nor/spi-nor.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/mtd
Hello,
Le 23/08/2017 à 18:46, Florian Fainelli a écrit :
> On 08/23/2017 01:50 AM, Romain Perier wrote:
>> This code is no longer used, the logging function was changed by commit
>> fbca164776e4 ("net: stmmac: Use the right logging functi"). It was
>> previously showing information about the type
2017-08-24 12:21 GMT+08:00 Wanpeng Li :
> From: Wanpeng Li
>
> vmx_complete_interrupts() assumes that the exception is always injected,
> so it would be dropped by kvm_clear_exception_queue(). This patch separates
> exception.pending from exception.injected, exception.inject represents the
> excep
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