There are new types and helpers that are supposed to be used in new code.
As a preparation to get rid of legacy types and API functions do
the conversion here.
While here, re-indent couple of lines to increase readability.
Cc: David Kershner
Cc: Greg Kroah-Hartman
Cc: sparmaintai...@unisys.com
On Fri, Jul 28, 2017 at 01:10:03PM +0200, Michal Hocko wrote:
> I haven't seen a newer version posted but the same comment applies on
> your hmm-v25-4.9 git version from
> git://people.freedesktop.org/~glisse/linux
>
> On Wed 28-06-17 14:00:41, Jérôme Glisse wrote:
> > This introduce a simple stru
On Sun, 2017-07-30 at 10:37 -0700, Greg Kroah-Hartman wrote:
> On Sun, Jul 30, 2017 at 08:26:48PM +0300, Andy Shevchenko wrote:
> > On Sun, Jul 30, 2017 at 6:32 PM, Greg Kroah-Hartman
> > wrote:
> > > Doesn't apply to the staging tree at all :(
> >
> > No surprises, it was cooked against uuid tr
On Mon, 2017-07-31 at 14:48 +, Josef Bacik wrote:
> On Mon, Jul 31, 2017 at 03:42:25PM +0200, Mike Galbraith wrote:
> > On Mon, 2017-07-31 at 12:21 +, Josef Bacik wrote:
> > >
> > > I've been working in this area recently because of a cpu imbalance
> > > problem.
> > > Wake_wide() definit
Fix ordering of link creation between node->prev and prev->next in
osq_lock(). A case in which the status of optimistic spin queue is
CPU6->CPU2 in which CPU6 has acquired the lock.
tail
v
,-. <- ,-.
|6||2|
`-' -> `-'
At this point if CPU0 comes in to acquire osq_lock,
On 07/30/2017 04:51 PM, Pavel Machek wrote:
Hi!
Screens that don't have a black border around the active area will have
ugly black bars for the margin when the text background color is not black.
This is especially noticeable on an LCD screen (not the backlit kind) when
the terminal colors are
The various LPI definitions are in the middle of the code, and
would be better placed at the beginning, given that we're going
to use some of them much earlier.
Reviewed-by: Thomas Gleixner
Reviewed-by: Eric Auger
Signed-off-by: Marc Zyngier
---
drivers/irqchip/irq-gic-v3-its.c | 25 ++
Add the probing code for the ITS VLPI support. This includes
configuring the ITS number if not supporting the single VMOVP
command feature.
Reviewed-by: Eric Auger
Signed-off-by: Marc Zyngier
---
drivers/irqchip/irq-gic-v3-its.c | 71 +++---
include/linux/irqch
Just as for the property table, let's move the pending table
allocation to a separate function.
Reviewed-by: Thomas Gleixner
Reviewed-by: Eric Auger
Signed-off-by: Marc Zyngier
---
drivers/irqchip/irq-gic-v3-its.c | 29 -
1 file changed, 20 insertions(+), 9 deletion
As we want to use 2-level tables for VCPUs, let's hack the device
table allocator in order to make it slightly more generic. It
will get reused in subsequent patches.
Reviewed-by: Thomas Gleixner
Reviewed-by: Eric Auger
Signed-off-by: Marc Zyngier
---
drivers/irqchip/irq-gic-v3-its.c | 26
When a guest issues a INVALL command targetting a collection, it must
be translated into a VINVALL for the VPE that has this collection.
This patch implements a hook that offers this functionallity to the
hypervisor.
Reviewed-by: Thomas Gleixner
Signed-off-by: Marc Zyngier
---
drivers/irqchip/
A long time ago, GITS_CTLR[1] used to be called GITC_CTLR.EnableVLPI.
It has been subsequently deprecated and is now an "Implementation
Defined" bit that may ot may not be set for GICv4. Brilliant.
And the current crop of the FastModel requires that bit for VLPIs
to be enabled. Oh well... Let's se
On activation, a VPE is mapped using the VMAPP command, followed
by a VINVALL for a good measure. On deactivation, the VPE is
simply unmapped.
Reviewed-by: Thomas Gleixner
Signed-off-by: Marc Zyngier
---
drivers/irqchip/irq-gic-v3-its.c | 102 +++
1 file chan
Add a bunch of GICv4-specific data structures that will get used in
subsequent patches.
Reviewed-by: Thomas Gleixner
Signed-off-by: Marc Zyngier
---
include/linux/irqchip/arm-gic-v4.h | 92 ++
1 file changed, 92 insertions(+)
create mode 100644 include/linux
As KVM needs to know about the availability of GICv4 to enable
direct injection of interrupts, let's advertise the feature in
the gic_kvm_info structure.
Signed-off-by: Marc Zyngier
---
drivers/irqchip/irq-gic-v3.c | 2 ++
include/linux/irqchip/arm-gic-common.h | 2 ++
2 files changed,
Upon updating a property, we propagate it all the way to the physical
ITS, and ask for an INV command to be executed there.
Signed-off-by: Marc Zyngier
---
virt/kvm/arm/vgic/vgic-its.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/virt/kvm/arm/vgic/vgic-its.c b/virt/kvm/arm/vgic/vgic-it
In order to control the GICv4 view of virtual CPUs, we rely
on an irqdomain allocated for that purpose. Let's add a couple
of helpers to that effect.
At the same time, the vgic data structures gain new fields to
track all this... erm... wonderful stuff.
They way we hook into the vgic init is slig
In order for VLPIs to be delivered to the guest, we must make
sure that the cpuif is always enabled, irrespective of the
presence of virtual interrupt in the LRs.
Signed-off-by: Marc Zyngier
---
virt/kvm/arm/hyp/vgic-v3-sr.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --
When freeing an LPI (on a DISCARD command, for example), we need
to unmap the VLPI down to the physical ITS level.
Signed-off-by: Marc Zyngier
---
virt/kvm/arm/vgic/vgic-its.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/virt/kvm/arm/vgic/vgic-its.c b/virt/kvm/arm/vgi
Handling CLEAR is pretty easy. Just ask the ITS driver to clear
the corresponding pending bit (which will turn into a CLEAR
command on the physical side).
Signed-off-by: Marc Zyngier
---
virt/kvm/arm/vgic/vgic-its.c | 4
1 file changed, 4 insertions(+)
diff --git a/virt/kvm/arm/vgic/vgic-i
When the VLPI gets mapped, it must inherit the configuration of
LPI configured at the vITS level. FOr that purpose, let's make
update_lpi_config globally available and call it just after
having performed the VLPI map operation.
Signed-off-by: Marc Zyngier
---
virt/kvm/arm/vgic/vgic-its.c | 6 ++-
In order to be able to issue command variants depending on
how broken an ITS is, let's pass the its pointer to all
command building primitives.
Signed-off-by: Marc Zyngier
---
drivers/irqchip/irq-gic-v3-its.c | 58 ++--
1 file changed, 38 insertions(+), 20 del
The ITSes on the Huawei D05 are broken when it comes to addressing
the redistributors, and need to be explicitely told to address
the VLPI page instead of the redistributor base address.
So let's add yet another quirk, fixing up the target address
in the command stream.
Signed-off-by: Marc Zyngie
All it takes is the has_v4 flag to be set in gic_kvm_info
as well as "kvm-arm.vgic_v4_enable=1" being passed on the
command line for GICv4 to be enabled in KVM.
Signed-off-by: Marc Zyngier
---
Documentation/admin-guide/kernel-parameters.txt | 4
virt/kvm/arm/vgic/vgic-v3.c
The GICv4 architecture doesn't prevent CPUs implementing GICv4 to
cohabit with CPUs limited to GICv3 in the same system.
This is mad (the sheduler would have to be made aware of the v4
capability), and we're certainly not going to support this any
time soon. So let's check that all online CPUs are
Yet another braindump so I can free some cells...
Signed-off-by: Marc Zyngier
---
virt/kvm/arm/vgic/vgic-v4.c | 68 +
1 file changed, 68 insertions(+)
diff --git a/virt/kvm/arm/vgic/vgic-v4.c b/virt/kvm/arm/vgic/vgic-v4.c
index 0a8deefbcf1c..0c002d2be
The redistributor needs to be told which vPE is about to be run,
and tells us whether there is any pending VLPI on exit.
Let's add the scheduling calls to the vgic flush/sync functions,
allowing the VLPIs to be delivered to the guest.
Signed-off-by: Marc Zyngier
---
virt/kvm/arm/vgic/vgic-v4.c
The doorbell interrupt is only useful if the vcpu is blocked on WFI.
In all other cases, recieving a doorbell interrupt is just a waste
of cycles.
So let's only enable the doorbell if a vcpu is getting blocked,
and disable it when it is unblocked. This is very similar to
what we're doing for the b
When a vPE is not running, a VLPI being made pending results in a
doorbell interrupt being delivered. Let's handle this interrupt
and update the pending_last flag that indicates that VLPIs are
pending. The corresponding vcpu is also kicked into action.
Signed-off-by: Marc Zyngier
---
virt/kvm/ar
Repeated dereference of nvmsg.msg.v1_msg.send_rndis_pkt can be
shortened by using a temporary. Do so.
No change in object code.
Miscellanea:
o Use * const for rpkt and nvchan
Signed-off-by: Joe Perches
---
v2: Use * const for rpkt and nvchan
This is a fairly unusual style, but is techn
When a vPE exits, the pending_last flag is set when there are
pending VLPIs stored in the pending table. Similarily, we set
this flag when a doorbell interrupt fires, as it indicates the
same condition.
Let's update kvm_vgic_vcpu_pending_irq() to account for that
flag as well, making a vcpu runnab
Since when updating the properties one LPI at a time, there is no
need to perform an INV each time we read one. Instead, we rely
on the final VINVALL that gets sent to the ITS to do the work.
Signed-off-by: Marc Zyngier
---
virt/kvm/arm/vgic/vgic-its.c | 15 +--
1 file changed, 9 ins
On Mon, Jul 31, 2017 at 9:46 AM, Darrick J. Wong
wrote:
> On Sat, Jul 29, 2017 at 12:43:35PM -0700, Dan Williams wrote:
>> An inode with this flag set indicates that the file's block map cannot
>> be changed, no size change, deletion, hole-punch, range collapse, or
>> reflink.
>>
>> The implementa
On 31.07.2017 15:22, Christoffer Dall wrote:
> On Sat, Jul 29, 2017 at 02:22:57PM +0800, Longpeng(Mike) wrote:
>> We had disscuss the idea here:
>> https://www.spinics.net/lists/kvm/msg140593.html
>
> This is not a very nice way to start a commit description.
>
> Please provide the necessary back
The current implementation of MOVALL doesn't allow us to call
into the core ITS code as we hold a number of spinlocks.
Let's try a method used in other parts of the code, were we copy
the intids of the candicate interrupts, and then do whatever
we need to do with them outside of the critical secti
On Mon, 2017-07-31 at 10:05 -0700, Stephen Hemminger wrote:
> On Sun, 30 Jul 2017 14:19:30 -0700 Joe Perches wrote:
> > Repeated dereference of nvmsg.msg.v1_msg.send_rndis_pkt can be
> > shortened by using a temporary. Do so.
[]
> Looks good, several other places also suffer from to
> long.varia
When the guest issues a MOVI, we need to tell the physical ITS
that we're now targetting a new vcpu. This is done by extracting
the current mapping, updating the target, and reapplying the
mapping. The core ITS code should do the right thing.
Signed-off-by: Marc Zyngier
---
virt/kvm/arm/vgic/vgi
If the guest issues an INT command targetting a VLPI, let's
call into the irq_set_irqchip_state() helper to make it pending
on the physical side.
This works just as well if userspace decides to inject an interrupt
using the normal userspace API...
Signed-off-by: Marc Zyngier
---
virt/kvm/arm/vg
Let's use the irq bypass mechanism introduced for platform device
interrupts to intercept the virtual PCIe endpoint configuration
and establish our LPI->VLPI mapping.
Signed-off-by: Marc Zyngier
---
include/kvm/arm_vgic.h | 8
virt/kvm/arm/arm.c | 27
virt/kvm/
Hi Andre,
On Mon, Jul 24, 2017 at 12:23 AM, Andre Przywara wrote:
>
> This mailbox driver implements a mailbox which signals transmitted data
> via an ARM smc (secure monitor call) instruction. The mailbox receiver
As far as I can see, this driver also supports transmission via hvc.
However, al
On 7/31/2017 11:00 AM, Luck, Tony wrote:
On Mon, Jul 31, 2017 at 10:15:27AM -0600, Baicar, Tyler wrote:
I think the better thing to do in this case is still send the ack. If
ghes_read_estatus() fails, then
either we are unable to read the estatus or the estatus is empty/invalid.
Right now we si
On Mon, Jul 31, 2017 at 07:04:03PM +0800, Boqun Feng wrote:
> On Mon, Jul 31, 2017 at 11:05:35AM +0200, Peter Zijlstra wrote:
> > On Wed, Jul 26, 2017 at 08:47:50PM +0800, Boqun Feng wrote:
> >
> > > > +
> > > > +Further, while something like:
> > > > +
> > > > + smp_mb__before_atomic();
> > > >
On 07/28/2017 09:23 AM, Jeff Layton wrote:
> From: Jeff Layton
>
> This patch converts most of the in-kernel filesystems that do writeback
> out of the pagecache to report errors using the errseq_t-based
> infrastructure that was recently added. This allows them to report
> errors once for each o
On Mon, Jul 31, 2017, at 12:32 PM, Colin Walters wrote:
> On Mon, Jul 31, 2017, at 12:29 PM, Dan Williams wrote:
> >
> > How is S_CONTENTS_IMMUTABLE different than S_IMMUTABLE?
>
> We still want the ability to make hardlinks.
Also of course, symmetrically, to unlink. If we used S_IMMUTABLE f
(keeping Rafael in c/c per Jassi suggestion)
On Thu, Jul 20, 2017 at 12:04 PM, Punit Agrawal wrote:
> When booting on an ACPI enabled system that does not provide the
> Platform Communications Channel Table (PCCT), the pcc mailbox driver
> prints -
>
> [0.484261] PCCT header not found.
Ah.
zs_stat_inc/dec/get() uses enum zs_stat_type for the stat type, however
some callers pass an enum fullness_group value. Change the type to int
to reflect the actual use of the functions and get rid of
'enum-conversion' warnings
Signed-off-by: Matthias Kaehlcke
---
mm/zsmalloc.c | 9 ++---
1
The whole MSI injection process is fairly monolithic. An MSI write
gets turned into an injected LPI in one swift go. But this is actually
a more fine-grained process:
- First, a virtual ITS gets selected using the doorbell address
- Then the DevID/EventID pair gets translated into an LPI
- Finally
The way we call kvm_vgic_destroy is a bit bizarre. We call it
*after* having freed the vcpus, which sort of defeats the point
of cleaning up things before that point.
Let's move kvm_vgic_destroy towards the beginning of kvm_arch_destroy_vm,
which seems more sensible.
Signed-off-by: Marc Zyngier
Add a new has_gicv4 field in the global VGIC state that indicates
whether the HW is GICv4 capable, as a per-VM predicate indicating
if there is a possibility for a VM to support direct injection
(the above being true and the VM having an ITS).
Signed-off-by: Marc Zyngier
---
include/kvm/arm_vgic
The GICv4 support introduces a hard dependency between the KVM
core and the ITS infrastructure. arm64 already selects it at
the architecture level, but 32bit doesn't. In order to avoid
littering the kernel with #ifdefs, let's just select the whole
of the GICv3 suport code.
You know you want it.
S
Do a braindump of the way things are supposed to work.
Reviewed-by: Thomas Gleixner
Reviewed-by: Eric Auger
Signed-off-by: Marc Zyngier
---
drivers/irqchip/irq-gic-v4.c | 71
1 file changed, 71 insertions(+)
diff --git a/drivers/irqchip/irq-gic-v4.
Get the show on the road...
Reviewed-by: Thomas Gleixner
Signed-off-by: Marc Zyngier
---
drivers/irqchip/Makefile | 2 +-
drivers/irqchip/irq-gic-v3-its.c | 3 ++-
drivers/irqchip/irq-gic-v4.c | 13 +
include/linux/irqchip/arm-gic-v4.h | 2 ++
4 files changed, 1
Add the required interfaces to schedule a VPE and perform a
VINVALL command.
Reviewed-by: Thomas Gleixner
Reviewed-by: Eric Auger
Signed-off-by: Marc Zyngier
---
drivers/irqchip/irq-gic-v4.c | 25 +
include/linux/irqchip/arm-gic-v4.h | 2 ++
2 files changed, 27 i
Add the required interfaces to map, unmap and update a VLPI.
Reviewed-by: Eric Auger
Reviewed-by: Thomas Gleixner
Signed-off-by: Marc Zyngier
---
drivers/irqchip/irq-gic-v4.c | 42 ++
include/linux/irqchip/arm-gic-v4.h | 4
2 files changed, 46 in
When creating a VM, it is very convenient to have an irq domain
containing all the doorbell interrupts associated with that VM
(each interrupt representing a VPE).
Reviewed-by: Thomas Gleixner
Signed-off-by: Marc Zyngier
---
drivers/irqchip/irq-gic-v4.c | 73 ++
When we're about to run a vcpu, it is crucial that the redistributor
associated with the physical CPU is being told about the new residency.
This is abstracted by hijacking the irq_set_affinity method for the
doorbell interrupt associated with the VPE. It is expected that the
hypervisor will call
While the doorbell interrupts are usually driven by the HW itself,
having a way to trigger them independently has proved to be a
really useful debug feature. As it is actually very little code,
let's add it to the VPE irqchip operations.
Signed-off-by: Marc Zyngier
---
drivers/irqchip/irq-gic-v3
When we don't have the DirectLPI feature, we must work around the
architecture shortcomings to be able to perform the required
invalidation.
For this, we create a fake device whose sole purpose is to
provide a way to issue a map/inv/unmap sequence (and the corresponding
sync operations). That's 6
When masking/unmasking a doorbell interrupt, it is necessary
to issue an invalidation to the corresponding redistributor.
We use the DirectLPI feature by writting directly to the corresponding
redistributor.
Reviewed-by: Thomas Gleixner
Signed-off-by: Marc Zyngier
---
arch/arm/include/asm/arch_
When a VPE is scheduled to run, the corresponding redistributor must
be told so, by setting VPROPBASER to the VM's property table, and
VPENDBASER to the vcpu's pending table.
When scheduled out, we preserve the IDAI and PendingLast bits. The
latter is specially important, as it tells the hyperviso
V{PEND,PROP}BASER being 64bit registers, they need some ad-hoc
accessors on 32bit, specially given that VPENDBASER contains
a Valid bit, making the access a bit convoluted.
Reviewed-by: Thomas Gleixner
Reviewed-by: Eric Auger
Signed-off-by: Marc Zyngier
---
arch/arm/include/asm/arch_gicv3.h
Add the basic GICv4 VPE (vcpu in GICv4 parlance) infrastructure
(irqchip, irq domain) that is going to be populated in the following
patches.
Reviewed-by: Eric Auger
Signed-off-by: Marc Zyngier
---
drivers/irqchip/irq-gic-v3-its.c | 33 -
1 file changed, 32 inser
When creating a VM, the low level GICv4 code is responsible for:
- allocating each VPE a unique VPEID
- allocating a doorbell interrupt for each VPE
- allocating the pending tables for each VPE
- allocating the property table for the VM
This of course has to be reversed when the VM is brought down
On Mon, Jul 31, 2017 at 9:42 AM, Josef Bacik wrote:
>>
>> >
>> > So why do you care about wake_wide() anyway? Are you observing some
>> > problem
>> > that you suspect is affected by the affine wakeup stuff? Or are you just
>> > trying
>>
>> I am dealing with an affine wake up issue, yes.
>>
When a VLPI is reconfigured (enabled, disabled, change in priority),
the full configuration byte must be written, and the caches invalidated.
Also, when using the irq_mask/irq_unmask methods, it is necessary
to disable the doorbell for that particular interrupt (by mapping it
to 1023) on top of cl
Add the new GICv4 ITS command definitions, most of them, being
defined in terms of their physical counterparts.
Reviewed-by: Eric Auger
Reviewed-by: Thomas Gleixner
Signed-off-by: Marc Zyngier
---
drivers/irqchip/irq-gic-v3-its.c | 2 +-
include/linux/irqchip/arm-gic-v3.h | 12
Add the skeleton irq_set_vcpu_affinity method that will be used
to configure VLPIs.
Reviewed-by: Eric Auger
Signed-off-by: Marc Zyngier
---
drivers/irqchip/irq-gic-v3-its.c | 24
1 file changed, 24 insertions(+)
diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/i
In order to let a VLPI being injected into a guest, the VLPI must
be mapped using the VMAPTI command. When moved to a different vcpu,
it must be moved with the VMOVI command.
These commands are issued via the irq_set_vcpu_affinity method,
making sure we unmap the corresponding host LPI first.
The
On Fri, Jul 28, 2017 at 4:00 PM, Alex Williamson
wrote:
> On Fri, 28 Jul 2017 11:50:43 -0700
> Feng Kan wrote:
>
>> The APM X-Gene PCIe root port does not support ACS at this point.
>> However, the hw provides isolation and source validation through
>> the SMMU. The stream ID generated by the PCI
On 7/31/2017 11:11 AM, James Morse wrote:
Hi Tyler,
On 31/07/17 17:15, Baicar, Tyler wrote:
On 7/29/2017 12:53 AM, Borislav Petkov wrote:
On Fri, Jul 28, 2017 at 04:25:03PM -0600, Tyler Baicar wrote:
Currently we acknowledge errors before clearing the error status.
This could cause a new erro
We're are going to need to change a bit more than just the enable
bit in the LPI property table in the future. So let's change the
LPI configuration funtion to take a set of bits to be cleared,
and a set of bits to be set.
This way, we'll be able to use it when a guest updates an LPI
property (pri
Rework LPI deallocation so that it can be reused by the v4 support
code.
Reviewed-by: Eric Auger
Reviewed-by: Thomas Gleixner
Signed-off-by: Marc Zyngier
---
drivers/irqchip/irq-gic-v3-its.c | 13 +++--
1 file changed, 7 insertions(+), 6 deletions(-)
diff --git a/drivers/irqchip/irq-g
On Mon, Jul 31, 2017 at 7:31 PM, Logan Gunthorpe wrote:
> On 31/07/17 10:10 AM, Andy Shevchenko wrote:
>> Some drivers (hardware) would like to have non-atomic MMIO accesses
>> when readq() defined
>
> Huh? But that's the whole point of the io64-nonatomic header. If a
> driver wants a specific non
On Mon, 31 Jul 2017 17:53:50 +0200
Michal Hocko wrote:
> On Mon 31-07-17 17:04:59, Gerald Schaefer wrote:
> > On Mon, 31 Jul 2017 14:53:19 +0200
> > Michal Hocko wrote:
> >
> > > On Mon 31-07-17 14:35:21, Gerald Schaefer wrote:
> > > > On Fri, 28 Jul 2017 14:19:41 +0200
> > > > Michal Hocko wr
The VCPU tables can be quite sparse as well, and it makes sense
to use indirect tables as well if possible.
Reviewed-by: Thomas Gleixner
Reviewed-by: Eric Auger
Signed-off-by: Marc Zyngier
---
drivers/irqchip/irq-gic-v3-its.c | 25 +
1 file changed, 17 insertions(+), 8
Move the LPI property table allocation into its own function, as
this is going to be required for those associated with VMs in
the future.
Reviewed-by: Eric Auger
Reviewed-by: Thomas Gleixner
Signed-off-by: Marc Zyngier
---
drivers/irqchip/irq-gic-v3-its.c | 31 +--
Most ITS commands do operate on a collection object, and require
a SYNC command to be performed on that collection in order to
guarantee the execution of the first command.
With GICv4 ITS, another set of commands perform similar operations
on a VPE object, and a VSYNC operations must be executed t
Allow the pending state of an LPI to be set or cleared via
irq_set_irqchip_state.
Reviewed-by: Thomas Gleixner
Reviewed-by: Eric Auger
Signed-off-by: Marc Zyngier
---
drivers/irqchip/irq-gic-v3-its.c | 78
1 file changed, 78 insertions(+)
diff --git a/
In order to discover the VLPI properties, we need to iterate over
the redistributor regions. As we already have code that does this,
let's factor it out and make it slightly more generic.
Reviewed-by: Thomas Gleixner
Signed-off-by: Marc Zyngier
---
drivers/irqchip/irq-gic-v3.c | 69
On 31/07/17 11:58 AM, Andy Shevchenko wrote:
> On Mon, Jul 31, 2017 at 7:31 PM, Logan Gunthorpe wrote:
>> On 31/07/17 10:10 AM, Andy Shevchenko wrote:
>>> Some drivers (hardware) would like to have non-atomic MMIO accesses
>>> when readq() defined
>>
>> Huh? But that's the whole point of the io6
Add helper functions that probe for VLPI and DirectLPI properties.
Reviewed-by: Eric Auger
Reviewed-by: Thomas Gleixner
Signed-off-by: Marc Zyngier
---
drivers/irqchip/irq-gic-v3.c | 24 +++-
include/linux/irqchip/arm-gic-v3.h | 3 +++
2 files changed, 26 insertions(
Hi Paul,
Thanks for looking at this again!
On 07/27/17 11:12 AM, Paul E. McKenney wrote:
> Hello!
>
> But my main question is whether the throttling shown below is acceptable
> for your use cases, namely only one expedited sys_membarrier() permitted
> per scheduling-clock period (1 millisecond
When assigning an interrupt to a vcpu, it is not unlikely that
the level of the hierarchy implementing irq_set_vcpu_affinity
is not the top level (think a generic MSI domain on top of a
virtualization aware interrupt controller).
In such a case, let's iterate over the hierarchy until we find
an ir
On 07/31/2017 at 02:10 PM Alan Cox wrote:
> On Wed, 26 Jul 2017 06:54:01 +0900
> Satoru Takeuchi wrote:
>
>> # I'm a LKML subscriber, but not a x86 list subscriber
>>
>> I found the following new linux kernel bugzilla about Ryzen related problem.
>> Since many developers don't check this bugzilla
This (monster of a) series implements full support for GICv4, bringing
direct injection of MSIs to KVM on arm and arm64, assuming you have
the right hardware (which is quite unlikely).
To get an idea of the design, I'd recommend you start with patches #33
and #57, which try to shed some light on t
On Mon, Jul 31, 2017 at 9:00 PM, Logan Gunthorpe wrote:
> On 31/07/17 11:58 AM, Andy Shevchenko wrote:
>> On Mon, Jul 31, 2017 at 7:31 PM, Logan Gunthorpe wrote:
>>> On 31/07/17 10:10 AM, Andy Shevchenko wrote:
Some drivers (hardware) would like to have non-atomic MMIO accesses
when rea
On 31/07/17 12:03 PM, Andy Shevchenko wrote:
>
> Per commit 3a044178cccf they are exactly created for this kind of cases.
>
Sure, ok, and my patchset provides the same set of functions to satisfy
such a use.
Logan
On Mon, Jul 31, 2017 at 9:04 PM, Logan Gunthorpe wrote:
>
>
> On 31/07/17 12:03 PM, Andy Shevchenko wrote:
>>
>> Per commit 3a044178cccf they are exactly created for this kind of cases.
>>
>
> Sure, ok, and my patchset provides the same set of functions to satisfy
> such a use.
Okay, please, Cc m
Ram Pai writes:
> static inline int mm_pkey_free(struct mm_struct *mm, int pkey)
> {
> - return -EINVAL;
> + if (!pkey_inited)
> + return -1;
Sorry, I missed this earlier but the pkey_free syscall will pass this
value to userspace so it needs to be an errno as well (-EINVAL
On Mon, Jul 31, 2017 at 2:27 AM, Joel Stanley wrote:
> On Sat, Jul 29, 2017 at 10:30 AM, Brendan Higgins
> wrote:
>> Before I skipped null checks when the master is in the STOP state; this
>> fixes that.
>>
>> Signed-off-by: Brendan Higgins
>
> Acked-by: Joel Stanley
>
> Out of interest, was th
On Mon, Jul 31, 2017 at 01:42:13PM -0400, Colin Walters wrote:
>
>
> On Mon, Jul 31, 2017, at 12:32 PM, Colin Walters wrote:
> > On Mon, Jul 31, 2017, at 12:29 PM, Dan Williams wrote:
> > >
> > > How is S_CONTENTS_IMMUTABLE different than S_IMMUTABLE?
> >
> > We still want the ability to make h
On Mon, Jul 31, 2017 at 10:09 AM, Darrick J. Wong
wrote:
> On Sat, Jul 29, 2017 at 12:43:40PM -0700, Dan Williams wrote:
>> >From falloc.h:
>>
>> FALLOC_FL_SEAL_BLOCK_MAP is used to seal (make immutable) all of the
>> file logical-to-physical extent offset mappings in the file. The
>>
Hello,
This patch (originally agains 3.1x, now I updated include to build
against 4.12.x) fixes winstron_btns module issue with calling BIOS
functions in non-executable memory.
Tested (on Linux 3.10.x and few later versions) on F-S Amilo 8210 laptop.
--
Jakub Boguszhttp://qboosh.pl/
wistro
On Mon, Jul 31, 2017 at 11:00:19AM -0700, Dave Watson wrote:
> Hi Paul,
>
> Thanks for looking at this again!
>
> On 07/27/17 11:12 AM, Paul E. McKenney wrote:
> > Hello!
> >
> > But my main question is whether the throttling shown below is acceptable
> > for your use cases, namely only one exp
New getfb2 functionality uses drm_mode_fb_cmd2 struct to be symmetric
with addfb2. Also modifies *_fb_create_handle() calls to accept a
format_plane_index so that handles for each plane can be generated.
Previously, many *_fb_create_handle() calls simply defaulted to plane 0 only.
Signed-off-by:
On 2017-07-24 19:39, Florian Fainelli wrote:
On 07/18/2017 12:37 PM, Florian Fainelli wrote:
Adds support for the Broadcom reference board BCM947189ACDMBR which
features the following:
* 128MB of DRAM
* External MoCA support through a Broadcom BCM6802 chip
* 1x external Gigabit PHY through the
The loop to find the best memory frame in arch_timer_mem_acpi_init()
initializes the loop counter with itself ('i = i'), which is suspicious
in the first place and pointed out by clang. The loop condition is
'i < timer_count' and a prior for loop exits when 'i' reaches
'timer_count', therefore the
Clang produces the following warning:
net/ipv4/netfilter/nf_nat_h323.c:553:6: error:
logical not is only applied to the left hand side of this comparison
[-Werror,-Wlogical-not-parentheses]
if (!set_h225_addr(skb, protoff, data, dataoff, taddr,
^
add parentheses after the '!' to evaluate the
Andy Shevchenko writes:
> We may use hex2bin() instead of custom approach.
>
> Signed-off-by: Andy Shevchenko
[...]
> + u8 hc[2];
Let's move this to following more local scope.
> if (utf8) {
> *outlen = utf8s_to_utf16s(name, len, UTF16_HOST_ENDIAN,
> @@ -532,31 +532,1
On Mon, Jul 31, 2017 at 10:31:11AM +0200, Peter Zijlstra wrote:
> On Sun, Jul 30, 2017 at 11:28:13AM -0400, Johannes Weiner wrote:
> > On Sat, Jul 29, 2017 at 11:10:55AM +0200, Peter Zijlstra wrote:
> > > On Thu, Jul 27, 2017 at 11:30:10AM -0400, Johannes Weiner wrote:
> > > > +static void domain_c
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