Now that the virtual EL2 can access EL2 register states via EL1
registers, we need to consider it when selecting the register to
emulate.
Signed-off-by: Jintack Lim
---
arch/arm64/kvm/sys_regs.c | 46 --
1 file changed, 44 insertions(+), 2 deletions(-)
From: Zhen Lei
Now that the cached node optimisation can apply to all allocations, the
couple of users which were playing tricks with dma_32bit_pfn in order to
benefit from it can stop doing so. Conversely, there is also no need for
all the other users to explicitly calculate a 'real' 32-bit PFN,
When creating the shadow context for the virtual EL2 execution, we can
directly copy the EL2 register states to the shadow EL1 register states
if the virtual HCR_EL2.E2H bit is set. This is because EL1 and EL2
system register formats compatible with E2H=1.
Now that we allow the virtual EL2 modify
ARMv8.1 added more EL2 registers: TTBR1_EL2, CONTEXTIDR_EL2, and three
EL2 virtual timer registers. Add the first two registers to vcpu context
and set their handlers. The timer registers and their handlers will be
added in a separate patch.
Signed-off-by: Jintack Lim
---
arch/arm64/include/asm/
From: Zhen Lei
The mask for calculating the padding size doesn't change, so there's no
need to recalculate it every loop iteration. Furthermore, Once we've
done that, it becomes clear that we don't actually need to calculate a
padding size at all - by flipping the arithmetic around, we can just
c
These macros will be used to support the virtual EL2 with VHE.
Signed-off-by: Jintack Lim
---
arch/arm64/include/asm/kvm_emulate.h | 24
1 file changed, 24 insertions(+)
diff --git a/arch/arm64/include/asm/kvm_emulate.h
b/arch/arm64/include/asm/kvm_emulate.h
index 3017
The cached node mechanism provides a significant performance benefit for
allocations using a 32-bit DMA mask, but in the case of non-PCI devices
or where the 32-bit space is full, the loss of this benefit can be
significant - on large systems there can be many thousands of entries in
the tree, such
From: Zhen Lei
Checking the IOVA bounds separately before deciding which direction to
continue the search (if necessary) results in redundantly comparing both
pfns twice each. GCC can already determine that the final comparison op
is redundant and optimise it down to 3 in total, but we can go one
pci_device_id are not supposed to change at runtime. All functions
working with pci_device_id provided by work with
const pci_device_id. So mark the non-const structs as const.
File size before:
textdata bss dec hex filename
2610 304 82922 b6a sound/hda/hda
On Tue, Jul 18, 2017 at 09:37:57AM -0700, Arjan van de Ven wrote:
> that's just a matter of fixing the C1 and later thresholds to line up right.
> shrug that's the most trivial thing to do, it's a number in a table.
Well, they represent a physical measure, namely the break-even-time. If
you go mu
Forward exceptions due to WFI or WFE instructions to the virtual EL2 if
they are not coming from the virtual EL2 and virtual HCR_EL2.TWX is set.
Signed-off-by: Jintack Lim
---
arch/arm64/include/asm/kvm_host.h | 1 +
arch/arm64/kvm/handle_exit.c | 13 -
arch/arm64/kvm/nested.c
On Tue, Jul 18, 2017 at 6:29 AM, Peter Chen wrote:
> On Mon, Jul 17, 2017 at 03:39:07PM +0200, Rafael J. Wysocki wrote:
>> > Sorry, I should describe more.
>> >
>> > Let's take USB bus as an example, when the new USB device is at the
>> > host port, the device structure at device model is not crea
On Tue, Jul 18, 2017 at 1:53 AM, Ingo Molnar wrote:
>
> * Peter Zijlstra wrote:
>
>> On Wed, Jul 05, 2017 at 09:04:39AM -0700, Andy Lutomirski wrote:
>> > On Wed, Jul 5, 2017 at 5:18 AM, Peter Zijlstra
>> > wrote:
>> > > On Thu, Jun 29, 2017 at 08:53:22AM -0700, Andy Lutomirski wrote:
>> > >> @
For the same reason we trap virtual memory register accesses in virtual
EL2, we trap CPACR_EL1 access too; We allow the virtual EL2 mode to
access EL1 system register state instead of the virtual EL2 one.
Signed-off-by: Jintack Lim
---
arch/arm64/kvm/hyp/switch.c | 10 +++---
arch/arm64/kvm/
Now that the psci call is done by the smc instruction when nested
virtualization is enabled, it is clear that all hvc instruction from the
VM (including from the virtual EL2) are supposed to handled in the
virtual EL2.
Signed-off-by: Jintack Lim
---
arch/arm64/kvm/handle_exit.c | 6 ++
1 fil
When HCR.NV bit is set, execution of the EL2 translation regime address
aranslation instructions and TLB maintenance instructions are trapped to
EL2. In addition, execution of the EL1 translation regime address
aranslation instructions and TLB maintenance instructions that are only
accessible from
When HCR.NV bit is set, eret instructions trap to EL2 with EC code 0x1A.
Emulate eret instructions by setting pc and pstate.
Note that the current exception level is always the virtual EL2, since
we set HCR_EL2.NV bit only when entering the virtual EL2. So, we take
spsr and elr states from the vir
VMs used to execute hvc #0 for the psci call if EL3 is not implemented.
However, when we come to provide the virtual EL2 mode to the VM, the
host OS inside the VM calls kvm_call_hyp() which is also hvc #0. So,
it's hard to differentiate between them from the host hypervisor's point
of view.
So, le
For the same reason we trap virtual memory register accesses at virtual
EL2, we need to trap SPSR_EL1, ELR_EL1 and VBAR_EL1 accesses. ARM v8.3
introduces the HCR_EL2.NV1 bit to be able to trap on those register
accesses in EL1. Do not set this bit until the whole nesting support is
completed.
Sign
These macros and enums can be reused to inject exceptions
for nested virtualization.
Signed-off-by: Jintack Lim
---
arch/arm64/include/asm/kvm_emulate.h | 12
arch/arm64/kvm/inject_fault.c| 12
2 files changed, 12 insertions(+), 12 deletions(-)
diff --git a/arc
Support inject synchronous exceptions to the virtual EL2 as
described in ARM ARM AArch64.TakeException().
This can be easily extended to support to inject asynchronous exceptions
to the virtual EL2, but it will be added in a later patch when appropriate.
Signed-off-by: Jintack Lim
---
arch/arm/
From: Christoffer Dall
When running in virtual EL2 mode, we actually run the hardware in EL1
and therefore have to use the EL1 registers to ensure correct operation.
By setting the HCR.TVM and HCR.TVRM we ensure that the virtual EL2 mode
doesn't shoot itself in the foot when setting up what it b
Hi all,
In the wake of the ARM SMMU optimisation efforts, it seems that certain
workloads (e.g. storage I/O with large scatterlists) probably remain quite
heavily influenced by IOVA allocation performance. Separately, Ard also
reported massive performance drops for a graphical desktop on AMD Seatt
From: Christoffer Dall
When entering virtual EL2, we need to reflect virtual EL2 register
states to corresponding shadow EL1 registers. We can simply copy them if
their formats are identical. Otherwise, we need to convert EL2 register
state to EL1 register state.
When entering EL1/EL0, we need
Hello, Waiman.
On Tue, Jul 18, 2017 at 10:37:41AM -0400, Waiman Long wrote:
> Thinking about it some more. There is a place for invalid domain. It is
> not the child of a threaded cgroup. It is the siblings of a threaded
> cgroup whose parent is not root.
>
>Root - A (domain) - B (domain)
With the nested virtualization support, a hypervisor running inside a VM
(i.e. a guest hypervisor) is now deprivilaged and runs in EL1 instead of
EL2. So, the host hypervisor manages the shadow context for the virtual
EL2 execution.
Signed-off-by: Jintack Lim
---
arch/arm64/include/asm/kvm_host.
From: Christoffer Dall
Some bits of the TCR weren't defined and since we're about to use these
in KVM, add these defines.
Signed-off-by: Christoffer Dall
---
arch/arm64/include/asm/pgtable-hwdef.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/include/asm/pgtable-hwdef.h
From: Christoffer Dall
Add functions setting up and restoring the guest's context on each entry
and exit. These functions will come in handy when we want to use
different context for normal EL0/EL1 and virtual EL2 execution.
No functional change yet.
Signed-off-by: Christoffer Dall
Signed-off-
If the guest exception level is EL2, then set up the shadow context of
the virtual EL2 to hardware. Otherwise, set the regular EL0/EL1 context.
Note that the shadow context content will be prepared in subsequent
patches.
Signed-off-by: Jintack Lim
---
arch/arm64/kvm/context.c | 74 +
From: Christoffer Dall
When running a nested hypervisor we occasionally have to figure out if
the mode we are switching into is the virtual EL2 mode or a regular
EL0/1 mode.
Signed-off-by: Christoffer Dall
---
arch/arm/include/asm/kvm_emulate.h | 6 ++
arch/arm64/include/asm/kvm_emulate
ARM v8.3 introduces a new bit in the HCR_EL2, which is the NV bit. When
this bit is set, accessing EL2 registers in EL1 traps to EL2. In
addition, executing the following instructions in EL1 will trap to EL2:
tlbi, at, eret, and msr/mrs instructions to access SP_EL1. Most of the
instructions that t
Nested virtualizaion is in use only if all three conditions are met:
- The architecture supports nested virtualization.
- The kernel parameter is set.
- The userspace uses nested virtualiztion feature.
Signed-off-by: Jintack Lim
---
arch/arm/include/asm/kvm_host.h | 11 +++
arch/arm64/
Add a new ARM64_HAS_NESTED_VIRT feature to indicate that the
CPU has the ARMv8.3 nested virtualization capability.
This will be used to support nested virtualization in KVM.
Signed-off-by: Jintack Lim
---
arch/arm64/include/asm/cpucaps.h | 3 ++-
arch/arm64/include/asm/sysreg.h | 1 +
arch/a
strscpy() performs the word-at-a-time optimistic reads. So it may
may access the memory past the end of the object, which is perfectly fine
since strscpy() doesn't use that (past-the-end) data and makes sure the
optimistic read won't cross a page boundary.
But KASAN doesn't know anything about tha
Hi David,
On 17-07-10 06:44 AM, Rob Herring wrote:
> On Thu, Jul 06, 2017 at 10:37:57AM -0700, Arun Parameswaran wrote:
>> Add SoC specific compatibility strings to the Broadcom DTE
>> based PTP clock binding document.
>>
>> Fixed the document heading and node name.
>>
>> Fixes: 80d6076140b2 ("dt-
Add a new kernel parameter(kvm-arm.nested) to enable KVM/ARM nested
virtualization support. This kernel parameter on arm architecture is
ignored since nested virtualization is not supported on arm.
Note that this kernel parameter will not have any impact until nested
virtualization support is comp
Nested virtualization is the ability to run a virtual machine inside another
virtual machine. In other words, it’s about running a hypervisor (the guest
hypervisor) on top of another hypervisor (the host hypervisor).
Supporting nested virtualization on ARM means that the hypervisor provides not
on
On Tue, Jul 18, 2017 at 7:15 PM, Andrey Ryabinin
wrote:
> strscpy() performs the word-at-a-time optimistic reads. So it may
> may access the memory past the end of the object, which is perfectly fine
> since strscpy() doesn't use that (past-the-end) data and makes sure the
> optimistic read won't
On Tue, 2017-07-18 at 09:04 -0700, Thomas Garnier wrote:
> On Tue, Jul 18, 2017 at 7:36 AM, Leonard Crestez
> wrote:
> >
> > On Wed, 2017-06-14 at 18:12 -0700, Thomas Garnier wrote:
> > >
> > > Ensure the address limit is a user-mode segment before returning to
> > > user-mode. Otherwise a proc
On Tue, Jul 18, 2017 at 10:15 AM, Andrey Ryabinin
wrote:
>
> + /*
> +* KASAN won't be happy about word-at-a-time
> +* optimistic reads, so let's avoid them.
> +*/
> + if (IS_ENABLED(CONFIG_KASAN))
> + max = 0;
> +
No, please don't.
Two reasons:
On 07/18/2017 01:10 PM, Tejun Heo wrote:
> Hello, Waiman.
>
> On Tue, Jul 18, 2017 at 10:37:41AM -0400, Waiman Long wrote:
>> Thinking about it some more. There is a place for invalid domain. It is
>> not the child of a threaded cgroup. It is the siblings of a threaded
>> cgroup whose parent is not
are here:
http://kisskb.ellerman.id.au/kisskb/buildresult/12982362/
Signed-off-by: Murilo Opsfelder Araujo
---
Changes from v1:
- Rebased on top of next-20170718.
include/linux/vfio.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/include/linux/vfio.h b/include/linux/vfio.h
in
Helpful for post-mortem analysis to synchronize CLOCK_MONOTONIC
kernel logs with CLOCK_REALTIME user space logs. Post-mortem
analysis for Battery and Power diagnosis. Improved reporting
of suspension times against the rtc wallclock, which is
persistent even at the lowest power management states.
On Tue, 2017-07-18 at 18:43 +0200, Borislav Petkov wrote:
> On Tue, Jul 18, 2017 at 03:48:54PM +, Kani, Toshimitsu wrote:
> > This patch defines 'struct acpi_oemlist' in "include/linux/acpi.h"
> > as a
>
> I see that.
>
> > common structure, and replaces this specific 'struct
> > acpi_blackli
Permits power state and battery life diagnosis.
Feature activated by CONFIG_RTC_SHOW_TIME.
Signed-off-by: Mark Salyzyn
---
drivers/rtc/rtc-lib.c | 58 +++
1 file changed, 58 insertions(+)
diff --git a/drivers/rtc/rtc-lib.c b/drivers/rtc/rtc-lib.c
Permits power state and battery life diagnosis.
Feature activated by CONFIG_RTC_SHOW_TIME.
Signed-off-by: Mark Salyzyn
---
kernel/power/suspend.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/kernel/power/suspend.c b/kernel/power/suspend.c
index 3ecf275d7e44..f44d2152ab3f 100644
--- a/
Go directly to the rtc for persistent wall clock time and print.
Useful if REALTIME is required to be logged in a low level power
management function or when clock activities are suspended. An
aid to permit user space alignment of kernel activities.
Feature activated by CONFIG_RTC_SHOW_TIME.
Sig
Permits power state and battery life diagnosis.
Feature activated by CONFIG_RTC_SHOW_TIME.
Signed-off-by: Mark Salyzyn
---
kernel/power/hibernate.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/kernel/power/hibernate.c b/kernel/power/hibernate.c
index e1914c7b85b1..0b54
On Mon, Jul 17, 2017 at 10:26:09AM -0400, Tejun Heo wrote:
> Hello, Peter.
>
> On Mon, Jul 17, 2017 at 04:14:09PM +0200, Peter Zijlstra wrote:
> > AFAICT this is not in fact what I suggested... :/
>
> Heh, sorry about misattributing that. I was mostly referring to the
> overall idea of marking e
The HSDK v1 periphery IPs can be reset by accessing some registers
from the CGU block.
The list of available reset lines is documented in the DT bindings.
Signed-off-by: Eugeniy Paltsev
---
.../bindings/reset/snps,hsdk-v1-reset.txt | 28
MAINTAINERS
I have verified that building a clean v4.12 with
68c59fcea1f2c6a54c62aa896cc623c1b5bc9b47 cherry picked on top still
shows the problem:
[root@backup2 ~]# mtx -f /dev/sg7 next 0
Unloading drive 0 into Storage Element 45...mtx: Request Sense: Long
Report=yes
mtx: Request Sense: Valid Residual=no
mtx
Linus Torvalds writes:
> On Tue, Jul 18, 2017 at 7:06 AM, Eric W. Biederman
> wrote:
>> struct siginfo is a union and the kernel since 2.4 has been hiding a union
>> tag in the high 16bits of si_code using the values:
>> __SI_KILL
>> __SI_TIMER
>> __SI_POLL
>> __SI_FAULT
>> __SI_CHLD
>> __SI_RT
On 07/18/2017 01:28 PM, Peter Zijlstra wrote:
> On Mon, Jul 17, 2017 at 10:26:09AM -0400, Tejun Heo wrote:
>> Hello, Peter.
>>
>> On Mon, Jul 17, 2017 at 04:14:09PM +0200, Peter Zijlstra wrote:
>>> AFAICT this is not in fact what I suggested... :/
>> Heh, sorry about misattributing that. I was mos
On Tue, 2017-07-18 at 10:25 -0700, Mark Salyzyn wrote:
> Go directly to the rtc for persistent wall clock time and print.
> Useful if REALTIME is required to be logged in a low level power
> management function or when clock activities are suspended. An
> aid to permit user space alignment of kern
On Mon, Jul 17, 2017 at 7:23 PM, Alex Williamson
wrote:
> On Mon, 17 Jul 2017 17:45:52 -0700
> Feng Kan wrote:
>
>> The APM X-Gene PCIe root port does not support ACS at this point.
>> Since the root does not allow peer to peer transactions, mask out
>> ACS capability flag bits.
>>
>> Signed-off-
On Tue, Jul 18, 2017 at 05:24:50PM +, Kani, Toshimitsu wrote:
> Well, a list does not need to be a black-list.
But this one *is* a blacklist.
> So, I tried to avoid putting any usage to the structure name.
So OEM is a usage. The moment you need to use it for something else
besides an OEM, it
Two local variables (shift and reg_con) were initialized to unused
values - they were overwritten just few lines after. Getting rid of
this unused initialization allows dropping other variables and
compacting slightly the code.
Signed-off-by: Krzysztof Kozlowski
---
drivers/pinctrl/samsung/pinc
On Tuesday 18 July 2017 10:20 PM, Suman Anna wrote:
> Hi Keerthy,
>
> On 07/18/2017 05:57 AM, Keerthy wrote:
>> Use the devm version of gpiochip_add_data and pass on the
>> return value. Reset the static variables to 0 before returning.
>>
>> Signed-off-by: Keerthy
>> ---
>> drivers/gpio/gpio-
On Tue, Jul 18, 2017 at 8:25 PM, Mark Salyzyn wrote:
> Go directly to the rtc for persistent wall clock time and print.
> Useful if REALTIME is required to be logged in a low level power
> management function or when clock activities are suspended. An
> aid to permit user space alignment of kerne
On Tuesday 18 July 2017 10:24 PM, Suman Anna wrote:
> Hi Keerthy,
>
> On 07/18/2017 05:57 AM, Keerthy wrote:
>> Currently davinci_gpio_irq_setup return value is ignored. Handle the
>> return value appropriately.
>>
>> Signed-off-by: Keerthy
>> ---
>> drivers/gpio/gpio-davinci.c | 18 ++
From: Florian Fainelli
Date: Tue, 18 Jul 2017 09:01:01 -0700
> On 07/17/2017 02:10 PM, David Miller wrote:
>> From: Andrew Lunn
>> Date: Mon, 17 Jul 2017 23:04:05 +0200
>>
>>> On Mon, Jul 17, 2017 at 01:45:49PM -0700, David Miller wrote:
From: Vivien Didelot
Date: Mon, 17 Jul 2017 15
On Tue, Jul 18, 2017 at 8:46 PM, Andy Shevchenko
wrote:
> On Tue, Jul 18, 2017 at 8:25 PM, Mark Salyzyn wrote:
>> Go directly to the rtc for persistent wall clock time and print.
>> Useful if REALTIME is required to be logged in a low level power
>> management function or when clock activities ar
On Tuesday 18 July 2017 05:01 PM, Sekhar Nori wrote:
> Hi Keerthy,
>
> On Tuesday 18 July 2017 04:27 PM, Keerthy wrote:
>> Add a separate compatible for keystone-k2g soc
>>
>> Signed-off-by: Keerthy
>> ---
>> Documentation/devicetree/bindings/gpio/gpio-davinci.txt | 3 ++-
>> drivers/gpio/gpio
On Thu, 2017-06-08 at 16:47 +0300, Andy Shevchenko wrote:
> Recently I have noticed too many users of struct rtc_time that printing
> its content field by field.
>
> In this series I introduce %pt[dt][rv] specifier to make life a bit
> easier.
Hey Andy.
I just saw a patch with a printk for rtc t
From: Logan Gunthorpe
> Now that ioread64 and iowrite64 are available in io-64-nonatomic,
> we can remove the hack at the top of ntb_hw_intel.c and replace it
> with an include.
>
> Signed-off-by: Logan Gunthorpe
> Cc: Jon Mason
> Cc: Allen Hubbe
> Acked-by: Dave Jiang
Acked-by: Allen Hubbe
Hi Jeffy,
On Tue, Jul 18, 2017 at 02:02:53PM +0800, Jeffy Chen wrote:
> I was testing earlycon with 8250 dw serial console. And it hangs in
> these cases:
> 1/ kernel hang when calling early write function after free_initmem:
> a) the earlycon not disabled after the init code(due to keep_bootcon o
Hi,
On 18/07/2017 at 10:25:23 -0700, Mark Salyzyn wrote:
> Go directly to the rtc for persistent wall clock time and print.
> Useful if REALTIME is required to be logged in a low level power
> management function or when clock activities are suspended. An
> aid to permit user space alignment of k
From: Logan Gunthorpe
> Changes since v1:
>
> - Rebased onto latest ntb-next branch (with v4.13-rc1)
> - Reworked ntb_mw_count() function so that it can be called all the
> time (per discussion with Allen)
> - Various spelling and formatting cleanups from Bjorn
> - Added request_module() call su
Hello, Peter.
On Tue, Jul 18, 2017 at 07:28:01PM +0200, Peter Zijlstra wrote:
> > And now try to create another child C, should that be a domain or
> > threaded?
>
> Domain of course, as R must be a domain, and hence all its children
> start out as such.
I don't think it's a matter of course as
Add a driver for RAVE Supervisory Processor, an MCU implementing
varoius bits of housekeeping functionality (watchdoging, backlight
control, LED control, etc) on RAVE family of products by Zodiac
Inflight Innovations.
This driver implementes core MFD/serdev device as well as
communication subrouti
Cc: cphe...@gmail.com
Cc: Lucas Stach
Cc: Nikita Yushchenko
Cc: Rob Herring
Cc: Mark Rutland
Cc: devicet...@vger.kernel.org
Acked-by: Rob Herring
Signed-off-by: Andrey Smirnov
---
.../devicetree/bindings/mfd/zii,rave-sp.txt| 39 ++
1 file changed, 39 insertions(+)
Hi everyone,
This patch series is v2 of the driver for supervisory processor found
on RAVE series of devices from ZII. Supervisory processor is a PIC
microcontroller connected to various electrical subsystems on RAVE
devices whose firmware implements protocol to command/qery them.
Changes since [
On Tue, 2017-07-18 at 10:50 -0700, Joe Perches wrote:
> On Thu, 2017-06-08 at 16:47 +0300, Andy Shevchenko wrote:
> > Recently I have noticed too many users of struct rtc_time that
> > printing
> > its content field by field.
> >
> > In this series I introduce %pt[dt][rv] specifier to make life a
Currently the hikey dsi logic cannot generate accurate byte
clocks values for all pixel clock values. Thus if a mode clock
is selected that cannot match the calculated byte clock, the
device will boot with a blank screen.
This patch uses the new mode_valid callback (many thanks to
Jose Abreu for u
On Tue, 18 Jul 2017 19:05:06 +0200,
Arvind Yadav wrote:
>
> pci_device_id are not supposed to change at runtime. All functions
> working with pci_device_id provided by work with
> const pci_device_id. So mark the non-const structs as const.
>
> File size before:
>text data bss
On 18/07/17 11:51 AM, Allen Hubbe wrote:
> Acked-by: Allen Hubbe
Thanks.
> Should the order of 6 and 7 be swapped?
Hmm, yes. I'll make the change for a v3 after more feedback comes.
> 6 - I think just the comment is best. Rather than prohibit the use of
> functionality for hardware that do
From: Vivien Didelot
Date: Mon, 17 Jul 2017 13:03:34 -0400
> This patch series removes the remaining capabilities as well as the
> flags bitmap in the info structures. Most of them are turned into ops,
> or new info members.
>
> There is no mv88e6xxx_cap enum or bitmap flags anymore, only
> mv88
NUMA rework of workqueue made the combination of max_active of 1 and
WQ_UNBOUND insufficient to guarantee ST behavior system wide.
alloc_ordered_queue should now be used instead.
Signed-off-by: Alexei Potashnik
---
Documentation/core-api/workqueue.rst | 10 +++---
1 file changed, 7 insertio
On Tue, 18 Jul 2017 10:42:40 -0700
Feng Kan wrote:
> On Mon, Jul 17, 2017 at 7:23 PM, Alex Williamson
> wrote:
> > On Mon, 17 Jul 2017 17:45:52 -0700
> > Feng Kan wrote:
> >
> >> The APM X-Gene PCIe root port does not support ACS at this point.
> >> Since the root does not allow peer to peer
Thank you for taking a look into it. I don't see the garbled output.
Can you please send me the perf.data file or a way to reproduce it?
On Tue, Jul 18, 2017 at 1:35 AM, Jiri Olsa wrote:
> On Mon, Jul 17, 2017 at 03:10:36PM -0700, Arun Kalyanasundaram wrote:
>> The process_event python hook rece
On Thu, Jun 29, 2017 at 12:41:07PM -0700, Nick Terrell wrote:
> +static void zstd_free_workspace(struct list_head *ws)
> +{
> + struct workspace *workspace = list_entry(ws, struct workspace, list);
> +
> + vfree(workspace->mem);
> + kfree(workspace->buf);
> + kfree(workspace);
> +}
On Tue, Jul 18, 2017 at 02:11:35PM +0200, Thomas Gleixner wrote:
> On Tue, 18 Jul 2017, Piotr Gregor wrote:
> >
> > Dmesg reports insecure W+X mapping found at address
> > 8805f000/0x8805f000
> >
> > on 4.4.70 kernel patched with -rt83 patch:
>
> Does the same problem happen with
On 07/18/2017 04:06 AM, Eric W. Biederman wrote:
Setting si_code to __SI_FAULT results in a userspace seeing
an si_code of 0. This is the same si_code as SI_USER. Posix
and common sense requires that SI_USER not be a signal specific
si_code. As such this use of 0 for the si_code is a pretty
ho
From: Alexander Potapenko
Date: Mon, 17 Jul 2017 12:35:58 +0200
> KMSAN reported use of uninitialized memory in skb_set_hash_from_sk(),
> which originated from the TCP request socket created in
> cookie_v6_check():
...
> Similar error is reported for cookie_v4_check().
>
> Signed-off-by: Alexan
From: Jason Wang
Date: Mon, 17 Jul 2017 20:43:56 +0800
> This series brings two optimizations for virtio-net XDP:
>
> - avoid reset during XDP set
> - turn off offloads on demand
>
> Please review.
Michael, please review Jason's changes.
Thanks.
On 06/30/2017 02:37 PM, Rafał Miłecki wrote:
> On 30 June 2017 at 21:02, Florian Fainelli wrote:
>> Broadcom BCM53573 SoCs actually have 32 GPIOs, and not 16.
>>
>> Fixes: 3f37ec79dd21 ("bcma: support BCM53573 series of wireless SoCs")
>> Signed-off-by: Florian Fainelli
>
> Looks good.
Is Kalle
On Tue, 2017-07-18 at 20:55 +0300, Andy Shevchenko wrote:
> On Tue, 2017-07-18 at 10:50 -0700, Joe Perches wrote:
> > On Thu, 2017-06-08 at 16:47 +0300, Andy Shevchenko wrote:
> > > Recently I have noticed too many users of struct rtc_time that
> > > printing
> > > its content field by field.
> > >
Support the National Instruments 169445 board.
Signed-off-by: Nathan Sullivan
---
Changes since v5:
- make device tree addresses on the internal bus relative, and compile with
W=2 to be sure they are in the right format.
Documentation/devicetree/bindings/mips/ni.txt | 7 ++
MAINTAINERS
Commit-ID: 7375ae3a0b79ea072f4c672039f08f5db633b9e1
Gitweb: http://git.kernel.org/tip/7375ae3a0b79ea072f4c672039f08f5db633b9e1
Author: Tom Lendacky
AuthorDate: Mon, 17 Jul 2017 16:10:34 -0500
Committer: Ingo Molnar
CommitDate: Tue, 18 Jul 2017 20:23:20 +0200
compiler-gcc.h: Introduce _
Commit-ID: aca20d5462149333ba8b24a4a352be5b7a00dfd2
Gitweb: http://git.kernel.org/tip/aca20d5462149333ba8b24a4a352be5b7a00dfd2
Author: Tom Lendacky
AuthorDate: Mon, 17 Jul 2017 16:10:35 -0500
Committer: Ingo Molnar
CommitDate: Tue, 18 Jul 2017 20:23:26 +0200
x86/mm: Add support to make
On Tue, Jul 18, 2017 at 11:12:53AM -0700, Alexei Potashnik wrote:
> NUMA rework of workqueue made the combination of max_active of 1 and
> WQ_UNBOUND insufficient to guarantee ST behavior system wide.
>
> alloc_ordered_queue should now be used instead.
>
> Signed-off-by: Alexei Potashnik
Patch
From: Christophe JAILLET
Date: Mon, 17 Jul 2017 19:42:41 +0200
> If 'dma_set_mask_and_coherent()' fails, we must undo the previous
> 'pci_request_regions()' call.
> Adjust corresponding 'goto' to jump at the right place of the error
> handling path.
>
> Signed-off-by: Christophe JAILLET
Applie
These variables were set to u16 and u32 although they always hold a little
endian value.
This patch fixes multiple sparse warnings like:
drivers/staging/wlan-ng/prism2sta.c:375:46: warning: cast to restricted __le16
Signed-off-by: Alfonso Lima Astor
---
v2:
Resubmit patch that wouldn't appl
2017-07-01 7:58 GMT+09:00 Stephen Boyd :
> If we have a structure that's marked const it will be placed
> into the .rodata section but it could reference an init section
> function. Include the read only data section in the check we have
> for read/write data sections referencing init sections so w
On Tue, Jul 18, 2017 at 01:54:56PM -0400, Tejun Heo wrote:
> Okay, we're kinda off the rails now. Just to verify that we're on the
> same page, are you also saying that the following should be a valid
> configuration?
>
> R (D)
> |
> A (D and has processes in it and controlle
On Tue, Jul 18, 2017 at 11:24:42AM -0700, David Miller wrote:
> From: Jason Wang
> Date: Mon, 17 Jul 2017 20:43:56 +0800
>
> > This series brings two optimizations for virtio-net XDP:
> >
> > - avoid reset during XDP set
> > - turn off offloads on demand
> >
> > Please review.
>
> Michael, ple
On Tue, Jul 18, 2017 at 08:41:35PM +0200, Peter Zijlstra wrote:
> On Tue, Jul 18, 2017 at 01:54:56PM -0400, Tejun Heo wrote:
>
> > Okay, we're kinda off the rails now. Just to verify that we're on the
> > same page, are you also saying that the following should be a valid
> > configuration?
> >
Why do we expect the VM_EXIT_INTR_INFO and EXIT_QUALIFICATION fields
of the VMCS to have the correct values for the injected exception?
On Mon, Jun 5, 2017 at 5:19 AM, Wanpeng Li wrote:
> 2017-06-05 20:07 GMT+08:00 Paolo Bonzini :
>>
>>
>> On 03/06/2017 05:21, Wanpeng Li wrote:
>>> Commit 0b6ac34
On Tue, Jul 18, 2017 at 8:56 PM, Andrey Smirnov
wrote:
> Add a driver for RAVE Supervisory Processor, an MCU implementing
> varoius bits of housekeeping functionality (watchdoging, backlight
> control, LED control, etc) on RAVE family of products by Zodiac
> Inflight Innovations.
>
> This driver i
Hi,
Please pull 3 MD fixes:
- raid5-ppl fix by Artur. This one is introduced in this release cycle.
- raid5 reshape fix by Xiao. This is an old bug and will be added to stable.
- Bitmap fix by Guoqing.
Thanks,
Shaohua
The following changes since commit af3c8d98508d37541d4bf57f13a984a7f73a328c:
701 - 800 of 1285 matches
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