On Thu, Jul 13, 2017 at 10:13 PM, Maxime Ripard
wrote:
> Just like we did for the TCON enable and disable, for historical reasons we
> used to rely on the encoders calling the TCON mode_set function, while the
> CRTC has a callback for that.
>
> Let's implement it in order to reduce the boilerplat
On Thu, Jul 13, 2017 at 10:13 PM, Maxime Ripard
wrote:
> The "CPU" (or Intel 8080) interface uses a different interrupt called
> TRI_FINISH (most likely TRI being for trigger) to notify the end of frames,
> and hence the VBLANK period.
>
> And that interrupt to the possible VBLANK interrupts sourc
On 07/13/2017 12:54 PM, Moritz Fischer wrote:
From: Moritz Fischer
Add support for the Maxim/Dallas DS1374 RTC/WDT with trickle charger.
The device can either be configured as simple RTC, as simple RTC with
Alarm (IRQ) as well as simple RTC with watchdog timer.
Break up the old monolithic driv
Hi all,
Please do not add any v4.14 material to you linux-next included branches
until after v4.13-rc1 has been released.
Changes since 20170713:
The rdma tree gained a conflict against Linus' tree.
The random tree gained a conflict against Linus' tree.
Non-merge commits (relativ
On 13-07-17, 18:52, Saravana Kannan wrote:
> On 07/11/2017 10:24 PM, Viresh Kumar wrote:
> >On 11-07-17, 19:24, Saravana Kannan wrote:
> >>Currently, the governor calculates the next frequency, set the current CPU
> >>frequency (policy->cur). It also assumes the current CPU frequency doesn't
> >>ch
On Fri, Jul 14, 2017 at 11:47:32AM +0800, Li, Aubrey wrote:
> On 2017/7/13 23:20, Paul E. McKenney wrote:
> > On Thu, Jul 13, 2017 at 04:53:11PM +0200, Peter Zijlstra wrote:
> >> On Thu, Jul 13, 2017 at 10:48:55PM +0800, Li, Aubrey wrote:
> >>
> >>> - totally from arch_cpu_idle_enter entry to arch_
On Fri, 2017-07-14 at 06:34 +0300, Leon Romanovsky wrote:
> On Thu, Jul 13, 2017 at 09:17:13PM -0400, Doug Ledford wrote:
> > On Fri, 2017-07-14 at 11:14 +1000, Stephen Rothwell wrote:
> > > Hi Doug,
> > >
> > > Today's linux-next merge of the rdma tree got conflicts in:
> > >
> > > drivers/inf
On Thu, Jul 13, 2017 at 10:13 PM, Maxime Ripard
wrote:
> It seems like the dotclock dividers are a bit less strict range, and can
> operate even with a smaller than 6 divider. Loose the boundaries a bit.
>
> Signed-off-by: Maxime Ripard
> ---
> drivers/gpu/drm/sun4i/sun4i_dotclock.c | 20 +++
Instead of manually checking the bounds of VMALLOC_START and VMALLOC_END,
use is_vmalloc_addr. Such function was specifically designed for that
purpose.
Signed-off-by: Gustavo A. R. Silva
---
arch/arm/mm/iomap.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/arch/arm/mm/io
On Thu, Jul 13, 2017 at 10:13 PM, Maxime Ripard
wrote:
> The Bananapi M2-Magic is a board with an A33, a USB host and USB OTG
> connectors, and 8GB eMMC, an AP6212 WiFi/Bluetooth chip and connectors for
> DSI, CSI and GPIOs.
>
> Signed-off-by: Maxime Ripard
Reviewed-by: Chen-Yu Tsai
Has BPI pu
On Thu, Jul 13, 2017 at 04:51:10PM +0200, Stephan Müller wrote:
> Am Donnerstag, 13. Juli 2017, 16:22:32 CEST schrieb Christian Langrock:
>
> Hi Christian,
>
> > With this patch it's possible to use crypto user API form all
> > network namespaces, not only form the initial net ns.
>
> Is this wi
On 07/14/2017 04:03 AM, Mike Kravetz wrote:
> On 07/13/2017 12:11 PM, Vlastimil Babka wrote:
>> [+CC linux-api]
>>
>> On 07/13/2017 05:58 PM, Mike Kravetz wrote:
>>> mremap will create a 'duplicate' mapping if old_size == 0 is
>>> specified. Such duplicate mappings make no sense for private
>>> ma
On Fri, Jul 14, 2017 at 12:12:33AM -0400, Doug Ledford wrote:
> On Fri, 2017-07-14 at 06:34 +0300, Leon Romanovsky wrote:
> > On Thu, Jul 13, 2017 at 09:17:13PM -0400, Doug Ledford wrote:
> > > On Fri, 2017-07-14 at 11:14 +1000, Stephen Rothwell wrote:
> > > > Hi Doug,
> > > >
> > > > Today's linux
On Fri, Jul 14, 2017 at 01:50:26PM +1000, Stephen Rothwell wrote:
> Hi all,
>
> On Fri, 14 Jul 2017 06:34:16 +0300 Leon Romanovsky wrote:
> >
> > Sorry Doug, but it is not expected at all for the code which will go to
> > 4.14.
> >
> > Both patches in question were targeted for 4.13 and you was e
On 13-07-17, 19:02, Saravana Kannan wrote:
> Honestly, this seems like such a chip/platform specific decision. There's no
> reason that one can't have a chip where you can change the frequency of any
> CPU from any other CPU. If there's such a limitation, we should let that be
> handled at the CPU
Palmer Dabbelt writes:
> On Thu, 13 Jul 2017 05:32:26 PDT (-0700), james.ho...@imgtec.com wrote:
>> On Thu, Jul 13, 2017 at 09:59:53PM +1000, Michael Ellerman wrote:
>>>
>>> I think it's fairly uncontroversial to have the early console in arch
>>> code, especially in a case like this where there's
On 2017-07-13 11:46, Wolfram Sang wrote:
> Hi peda,
>
> On Sun, May 21, 2017 at 10:37:41PM +0200, Wolfram Sang wrote:
>> It doesn't make sense to use include/linux/i2c for client drivers which may
>> in
>> fact rather be hwmon or input or whatever devices. As a result, I want to
>> deprecate incl
On Mon, Jun 26, 2017 at 05:49:04PM -0500, Tom Zanussi wrote:
> Define a new function, tracing_set_time_stamp_abs(), which can be used
> to enable or disable the use of absolute timestamps rather than time
> deltas for a trace array.
>
> This resets the buffer to prevent a mix of time deltas and ab
Hi Felipe,
On Friday 09 June 2017 11:43 AM, Felipe Balbi wrote:
+static void notrace ftrace_write(struct trace_export *ftrace, const void *buf,
+unsigned int len)
+{
+ struct usb_ftrace *trace = ftrace_to_trace(ftrace);
+ struct usb_reque
On Fri, Jul 14, 2017 at 1:43 AM, Laurent Pinchart
wrote:
>> Commit 52055bafa1ff ("drm: rcar-du: Move plane commit code from CRTC
>> start to CRTC resume") changed the order of the plane commit and CRTC
>> enable operations to accommodate the runtime PM requirements. However,
>> this introduced cor
Hi Thierry,
> I /think/ Jeremy Kerr (To'ed) would be a good person to contact about
> this.
>
> Jeremy, anything you can do about this?
OK, all sorted. I've updated Jerome's entry in the database to suit.
Cheers,
Jeremy
Hi Felipe,
On Friday 09 June 2017 03:58 PM, Felipe Balbi wrote:
Felipe Balbi writes:
Allow for ftrace data to be exported over a USB Gadget
Controller. With this, we have a potentially very fast pipe for
transmitting ftrace data to a Host PC for further analysis.
Note that in order to decode
[Background]
MP specification defines three different interrupt delivery modes as follows:
1. PIC Mode
2. Virtual Wire Mode
3. Symmetric I/O Mode
They will be setup in the different periods of booting time:
1. *PIC Mode*, the default interrupt delivery modes, will be set first.
2. *Virtual
Now, there are many switches in kernel which are used to determine
the final interrupt delivery mode, as shown below:
1) kconfig:
CONFIG_X86_64; CONFIG_X86_LOCAL_APIC; CONFIG_x86_IO_APIC
2) kernel option: disable_apic; skip_ioapic_setup
3) CPU Capability: boot_cpu_has(X86_FEATURE_APIC)
4) MP ta
There are three positions for initializing the interrupt delivery
modes:
1) In IRQ initial function, may setup the through-local-APIC
virtual wire mode.
2) In an SMP-capable system, will try to switch to symmetric I/O
model when preparing the cpus in native_smp_prepare_cpus().
3) In UP sys
apic_bsp_setup() sets and returns logical APIC ID for initializing
cpu0_logical_apicid in SMP-capable system.
The id has nothing to do with the initialization of local APIC and
I/O APIC. And apic_bsp_setup() should be called for interrupt mode
setup intently.
Move the id setup into a separate hel
In the SMP-capable system, enable and setup the interrupt delivery
mode in native_smp_prepare_cpus().
This design mixs the APIC and SMP together, it has highly coupling.
Make the initialization of interrupt mode independent, Unify and
refine it to apic_intr_mode_init() for SMP-capable system.
Si
In UniProcessor kernel with UP_LATE_INIT=y, it enables and setups
interrupt delivery mode in up_late_init().
Unify it to apic_intr_mode_init(), remove APIC_init_uniprocessor().
Signed-off-by: Dou Liyang
---
arch/x86/include/asm/apic.h | 1 -
arch/x86/kernel/apic/apic.c | 47 ++-
In start_kernel(), firstly, it works on the default interrupy mode, then
switch to the final mode. Normally, Booting with BIOS reset is OK.
But, At dump-capture kernel, it boot up without BIOS reset, default mode
may not be compatible with the actual registers, that causes the delivery
interrupt t
The init_bsp_APIC() which works for the virtual wire mode is used
in ISA irq initialization at the booting time.
Currently, enable and setup the interrupt mode has been unified
and advanced just behind the timer IRQ setup. Kernel switches to
the final interrupt delivery mode directly. So init_bsp_
Linux uses acpi_early_init() to put the ACPI table management into
the late stage from the early stage where the mapped ACPI tables is
temporary and should be unmapped.
But, now initializing interrupt delivery mode should map and parse the
DMAR table earlier in the early stage. This causes an ACPI
XEN PV overrides smp_prepare_cpus(). xen_pv_smp_prepare_cpus()
initializes interrupts in the XEN PV specific way and does not invoke
native_smp_prepare_cpus(). As a consequence, x86_init.intr_mode_init() is
not invoked either.
The invocation of x86_init.intr_mode_init() will be moved from
native_s
Hi Moritz,
[auto build test WARNING on net-next/master]
[also build test WARNING on v4.12 next-20170713]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day-ci/linux/commits/Moritz-Fischer/dt-bindings-net-Add
Kernel use timer_irq_works() to detects the timer IRQs. It calls
mdelay(10) to delay ten ticks and check whether the timer IRQ work
or not. The mdelay() depends on the loops_per_jiffy which is set up
in calibrate_delay(). Current kernel defaults the IRQ 0 is available
when it calibrates delay.
But
Calling native_smp_prepare_cpus() to prepare for SMP bootup, does
some sanity checking, enables APIC mode and disables SMP feature.
Now, APIC mode setup has been unified to apic_intr_mode_init(),
some sanity checks are redundant and need to be cleanup.
Mark the apic_intr_mode extern to refine the
X86 and XEN initialize interrupt delivery mode in different way.
Ordinary conditional function calls will make the code mess.
Add an unconditional x86_init_ops function which defaults to the
standard function and can be overridden by the early platform code.
Signed-off-by: Dou Liyang
---
arch/
apic_bsp_setup() sets up the local APIC, I/O APIC and APIC timer.
The local APIC and I/O APIC setup belongs to interrupt delivery mode
setup. Setting up the local APIC timer for booting CPU is another job
and has nothing to do with interrupt delivery mode setup.
Split local APIC timer setup from
On Fri, Jul 14, 2017 at 12:40 AM, Greg Hackmann wrote:
> Hi,
>
> Thanks for taking a look at this patchstack. I apologize for the delay in
> responding.
>
> On 07/10/2017 01:44 AM, Dmitry Vyukov wrote:
>>>
>>> +
>>> + const void *left_redzone = (const void *)(addr -
>>> +
Hi Jacob,
Am Freitag, 14. Juli 2017, 09:52:30 CEST schrieb Jacob Chen:
> 2017-07-14 7:34 GMT+08:00 Heiko Stuebner :
> > Am Donnerstag, 13. Juli 2017, 00:03:51 CEST schrieb Jacob Chen:
> >> Add devicetree nodes for rk3399 VOP (Video Output Processors), and the
> >> top level display-subsystem root
On 07/10/2017 09:06 AM, Yijing Wang wrote:
> Now libsas hotplug work is static, every sas event type has its own
> static work, LLDD driver queue the hotplug work into shost->work_q.
> If LLDD driver burst post lots hotplug events to libsas, the hotplug
> events may pending in the workqueue like
>
On 07/10/2017 09:06 AM, Yijing Wang wrote:
> No one uses the port_gone_completion in struct asd_sas_port,
> clean it out.
>
> Signed-off-by: Yijing Wang
> ---
> include/scsi/libsas.h | 2 --
> 1 file changed, 2 deletions(-)
>
> diff --git a/include/scsi/libsas.h b/include/scsi/libsas.h
> index
On 07/11/2017 08:23 AM, Colin King wrote:
From: Colin Ian King
Don't populate array chip_name on the stack but instead make it static.
Makes the object code smaller by 40 bytes:
Before:
text data bss dec hex filename
5641 2840 384886522a1 dri
Hi Brian,
On 12/07/17 18:26, Brian Norris wrote:
Hi Guillaume,
I know this has already been merged, but I figured here was an OK place
to note (inline):
On Wed, May 03, 2017 at 10:56:25AM +0100, Guillaume Tucker wrote:
[...]
diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-midga
On Thu, Jul 13, 2017 at 08:23:33PM +0900, Byungchul Park wrote:
> On Thu, Jul 13, 2017 at 8:12 PM, Peter Zijlstra wrote:
> > On Thu, Jul 13, 2017 at 12:29:05PM +0200, Peter Zijlstra wrote:
> >> On Thu, Jul 13, 2017 at 07:09:53PM +0900, Byungchul Park wrote:
> >> > On Thu, Jul 13, 2017 at 11:50:52A
Starting with the A83T SoC, Allwinner introduced a new timing mode for
its MMC clocks. The new mode changes how the MMC controller sample and
output clocks are delayed to match chip and board specifics. There are
two controls for this, one on the CCU side controlling how the clocks
behave, and one
Hi everyone,
This series adds support for the MMC controllers on the A83T. The A83T's
MMC controller adds what they call the "new timing mode". It moves the
MMC clock delay lines into the controller itself. There are some minor
changes to how the clock rate is calculated. The new mode give better
On 07/10/2017 09:06 AM, Yijing Wang wrote:
> Now all libsas works are queued to scsi host workqueue,
> include sas event work post by LLDD and sas discovery
> work, and a sas hotplug flow may be divided into several
> works, e.g libsas receive a PORTE_BYTES_DMAED event,
> now we process it as follo
The H8 homlet has a micro-SD card slot connected to mmc0,
and onboard eMMC from FORESEE, connected to mmc2.
Signed-off-by: Chen-Yu Tsai
---
.../boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts | 21 +
1 file changed, 21 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t-
The A83T has 3 MMC controllers. The third one is a bit special, as it
supports a wider 8-bit bus, and a "new timing mode".
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 57 +++
1 file changed, 57 insertions(+)
diff --git a/arch/arm/boot/
On the SoCs that introduced the new timing mode for MMC controllers,
both the old (where the clock delays are set in the CCU) and new
(where the clock delays are set in the MMC controller) timing modes
are available, and we have to support them both. However there are
two bits that control which mo
mmc2 can support 8-bit eMMC chips, with a dedicated reset line.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 085312d0c521..b1198d80873e 1
The MMC controller can support DDR52 transfers under the new timing
mode. According to the BSP kernel, the module clock has to be double
the card clock, regardless of the bus width. The default timings in
the hardware can be used.
This also reworks the code setting the internal divider, getting ri
Now that the CCU device tree binding headers have been merged, we can
use the properly named macros in the device tree, instead of raw
numbers.
Signed-off-by: Chen-Yu Tsai
---
This patch is included as it is a pre-requisite to the other device
tree changes in this series. It is however independe
The register for the "new timing mode" also has bit fields for setting
output and sample timing phases. According to comments in Allwinner's
BSP kernel, the default values are good enough.
Keep the default values already in the hardware when setting new timing
mode, instead of overwriting the whol
Now that we support the MMC controllers on the A83T SoC, we can enable
them on some boards.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts | 27
1 file changed, 27 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.
The MMC2 clock supports a new timing mode. When the new mode is active,
the output clock rate is halved.
This patch sets the feature flag for the new timing mode, and adds
a pre-divider based on the mode bit.
Signed-off-by: Chen-Yu Tsai
---
drivers/clk/sunxi-ng/ccu-sun8i-a83t.c | 38 +++
The third MMC controller (MMC2) on the Allwinner A83T SoC is slightly
different. It supports a wider 8-bit bus, has a dedicated controllable
reset pin for eMMC, and a "new timing mode" which is supposed to deliver
better signals and thus better performance.
Add a compatible for this one to use the
On Thu, Jul 13, 2017 at 02:37:38PM -0500, Mustafa Ismail wrote:
> Initialize the port_num for iWARP in rdma_init_qp_attr.
>
> Signed-off-by: Mustafa Ismail
> ---
> drivers/infiniband/core/cma.c | 2 ++
> 1 file changed, 2 insertions(+)
This is not the correct way to submit patches for inclusi
On Thu, Jul 13, 2017 at 02:37:37PM -0500, Mustafa Ismail wrote:
> The port number is only valid if IB_QP_PORT is set in the mask.
> So only check port number if it is valid to prevent modify_qp from
> failing due to an invalid port number.
>
> Fixes: 5ecce4c9b17b("Check port number supplied by use
On Thu, Jul 13, 2017 at 06:44:38PM +, Ismail, Mustafa wrote:
> > -Original Message-
> > From: Greg Kroah-Hartman [mailto:gre...@linuxfoundation.org]
> > Sent: Thursday, July 13, 2017 11:26 AM
> > To: Ismail, Mustafa
> > Cc: linux-kernel@vger.kernel.org; linux-r...@vger.kernel.org;
> >
Ping for the merge window. :)
2017-07-09 15:40 GMT+08:00 Wanpeng Li :
> From: Wanpeng Li
>
> BUG: using smp_processor_id() in preemptible [] code: 99-trinity/181
> caller is debug_smp_processor_id+0x17/0x19
> CPU: 0 PID: 181 Comm: 99-trinity Not tainted 4.12.0-01059-g2a42eb9 #1
> Call
On 07/10/2017 09:06 AM, Yijing Wang wrote:
> Introduce wait-complete for libsas sas event processing,
> execute sas port create/destruct in sync.
>
> Signed-off-by: Yijing Wang
> CC: John Garry
> CC: Johannes Thumshirn
> CC: Ewan Milne
> CC: Christoph Hellwig
> CC: Tomas Henzl
> CC: Dan Will
On 07/10/2017 09:06 AM, Yijing Wang wrote:
> Sometimes, we want sync libsas probe or destruct in sas discovery work,
> like when libsas revalidate domain. We need to split probe and destruct
> work from the scsi host workqueue.
>
> Signed-off-by: Yijing Wang
> CC: John Garry
> CC: Johannes Thums
On 07/10/2017 09:06 AM, Yijing Wang wrote:
> Introduce a sync flag to tag discovery event whether need to
> sync execute, per-event wait-complete ensure sync.
>
> Signed-off-by: Yijing Wang
> CC: John Garry
> CC: Johannes Thumshirn
> CC: Ewan Milne
> CC: Christoph Hellwig
> CC: Tomas Henzl
>
Hi,
Pratyush Anand writes:
> On Friday 09 June 2017 03:58 PM, Felipe Balbi wrote:
>> Felipe Balbi writes:
>>
>>> Allow for ftrace data to be exported over a USB Gadget
>>> Controller. With this, we have a potentially very fast pipe for
>>> transmitting ftrace data to a Host PC for further analy
On Thu, Jul 13, 2017 at 03:24:02PM -0400, Ben Guthro wrote:
> On Tue, Jul 11, 2017 at 5:55 AM, Greg KH wrote:
> > On Tue, Jul 11, 2017 at 10:30:14AM +0200, Ingo Molnar wrote:
> >>
> >> * Ben Guthro wrote:
> >>
> >> > > If people have experience with these in the "enterprise" distros, or
> >> > >
On 07/10/2017 09:06 AM, Yijing Wang wrote:
> Disco mutex was introudced to prevent domain rediscovery competing
> with ata error handling(87c8331). If we have already hold the lock
> in sas_revalidate_domain and sync executing probe, deadlock caused,
> because, sas_probe_sata() also need hold disco
Hi,
Pratyush Anand writes:
> Hi Felipe,
>
> On Friday 09 June 2017 11:43 AM, Felipe Balbi wrote:
>> +static void notrace ftrace_write(struct trace_export *ftrace, const void
>> *buf,
>> + unsigned int len)
>> +{
>> +struct usb_ftrace *trace = ftrace
According to a description from TRM, add all the power domains.
Signed-off-by: Elaine Zhang
---
include/dt-bindings/power/rk3366-power.h | 24
1 file changed, 24 insertions(+)
create mode 100644 include/dt-bindings/power/rk3366-power.h
diff --git a/include/dt-bindings/
support rk3366 SoC power domain setting.
Elaine Zhang (3):
dt-bindings: power: add RK3366 SoCs header for power-domain
dt-bindings: add binding for rk3366 power domains
soc: rockchip: power-domain: add power domain support for rk3366
.../bindings/soc/rockchip/power_domain.txt | 3
Add binding documentation for the power domains
found on Rockchip RK3366 SoCs.
Signed-off-by: Elaine Zhang
---
Documentation/devicetree/bindings/soc/rockchip/power_domain.txt | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/soc/rockchip/power_domain.txt
b
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