From: Jarkko Sakkinen
It's a bit hard for eye to track certs/Makefile if you are not
accustomed to it. This commit adds comments to key endif statements in
order to help to keep the context while reading this file.
Signed-off-by: Jarkko Sakkinen
Signed-off-by: David Howells
---
certs/Makefil
Hi James,
Could you pass these on to Linus please?
The patches can be found here also:
http://git.kernel.org/cgit/linux/kernel/git/dhowells/linux-fs.git/log/?h=keys-next
David
---
Eric Biggers (1):
KEYS: DH: validate __spare field
Jarkko Sakkinen (1):
modsign: add markers
From: Jarkko Sakkinen
It's a bit hard for eye to track certs/Makefile if you are not
accustomed to it. This commit adds comments to key endif statements in
order to help to keep the context while reading this file.
Signed-off-by: Jarkko Sakkinen
Signed-off-by: David Howells
---
certs/Makefil
From: Eric Biggers
Syscalls must validate that their reserved arguments are zero and return
EINVAL otherwise. Otherwise, it will be impossible to actually use them
for anything in the future because existing programs may be passing
garbage in. This is standard practice when adding new APIs.
Cc
From: Mat Martineau
Provide more specific examples of keyring restrictions as applied to
X.509 signature chain verification.
Signed-off-by: Mat Martineau
Signed-off-by: David Howells
---
Documentation/crypto/asymmetric-keys.txt | 65 ++
Documentation/security/ke
On Thu, Jul 06, 2017 at 05:07:14PM -0400, Sinan Kaya wrote:
> An endpoint is allowed to issue Configuration Request Retry Status (CRS)
> following a Function Level Reset (FLR) request to indicate that it is not
> ready to accept new requests.
>
> Seen a timeout message with Intel 750 NVMe drive an
On Thu, Jul 13, 2017 at 11:19:11AM +0200, Ingo Molnar wrote:
>
> * Peter Zijlstra wrote:
>
> > > One gloriously ugly hack would be to delay the userspace unwind to
> > > return-to-userspace, at which point we have a schedulable context and can
> > > take
> > > faults.
>
> I don't think it's
On 13/07/17 12:36, Bjorn Helgaas wrote:
> On Thu, Jul 13, 2017 at 08:46:45AM +0100, Marc Zyngier wrote:
>> On 13/07/17 07:48, Ard Biesheuvel wrote:
>>> On 13 July 2017 at 04:12, Bjorn Helgaas wrote:
On Mon, Jul 10, 2017 at 04:52:28PM +0100, Marc Zyngier wrote:
> Ard and myself have just s
Theodore Ts'o writes:
> I'm really confused what problem that is trying to be solved, here,
> but it **feels** really, really wrong.
>
> Why do we need to store all of this state on a per-file basis, instead
> of some kind of per-file system or per-container data structure?
>
> And how many of th
On Thu, Jul 13, 2017 at 07:17:55AM -0500, Josh Poimboeuf wrote:
> BTW, while we're throwing out ideas for this, here's another idea,
> though it's almost certainly not a good one :-)
>
> For user space stack unwinding, the kernel could emulate what the kernel
> 'guess' unwinder does by scanning th
Hi Rob,
On 2017-07-13 14:10, Rob Clark wrote:
On Thu, Jul 13, 2017 at 8:02 AM, Marek Szyprowski
wrote:
On 2017-07-13 13:50, Rob Clark wrote:
On Thu, Jul 13, 2017 at 1:35 AM, Sricharan R
wrote:
On 7/13/2017 10:43 AM, Vivek Gautam wrote:
On 07/13/2017 04:24 AM, Stephen Boyd wrote:
On 07/06,
On Thu, Jul 13, 2017 at 01:13:51PM +0300, Ville Syrjälä wrote:
> On Wed, Jul 12, 2017 at 07:28:14PM -0700, Stéphane Marchesin wrote:
> > On Fri, May 5, 2017 at 10:40 AM, Ville Syrjälä
> > wrote:
> > >
> > > On Fri, May 05, 2017 at 10:26:36AM -0700, Matthias Kaehlcke wrote:
> > > > El Thu, Apr 20,
+static ssize_t nvmet_subsys_attr_serial_show(struct config_item *item,
+char *page)
+{
+ struct nvmet_subsys *subsys = to_subsys(item);
+
+ return snprintf(page, PAGE_SIZE, "%llx\n", subsys->serial);
+}
+
+static ssize_t nvmet_subsys_attr_
On Thu, Jul 13, 2017 at 09:59:53PM +1000, Michael Ellerman wrote:
> Palmer Dabbelt writes:
>
> > On Wed, 12 Jul 2017 04:04:00 PDT (-0700), m...@ellerman.id.au wrote:
> >> Palmer Dabbelt writes:
> >>
> >>> On Mon, 10 Jul 2017 23:21:07 PDT (-0700), m...@ellerman.id.au wrote:
> Palmer Dabbelt
Sure, thanks so much!
On 7/13/2017 8:04 PM, Michael Ellerman wrote:
Jin Yao writes:
It is often useful to know the branch types while analyzing branch
data. For example, a call is very different from a conditional branch.
Currently we have to look it up in binary while the binary may later
On Thu, Jul 13, 2017 at 07:21:15AM -0500, Josh Poimboeuf wrote:
> On Thu, Jul 13, 2017 at 07:17:55AM -0500, Josh Poimboeuf wrote:
> > BTW, while we're throwing out ideas for this, here's another idea,
> > though it's almost certainly not a good one :-)
> >
> > For user space stack unwinding, the k
On Wed, Jul 12, 2017 at 02:18:32PM +0800, Jeffy Chen wrote:
> DRM_IOCTL_VERSION is supposed to update the name_len/date_len/desc_len
> fields to user.
>
> Fixes: 012c6741c6aa("switch compat_drm_version() to drm_ioctl_kernel()")
> Signed-off-by: Jeffy Chen
Reviewed-by: Daniel Vetter
Linus, sinc
On 7/11/17 3:31 PM, Mimi Zohar wrote:
> On Tue, 2017-07-11 at 13:49 -0400, Matt Brown wrote:
>
>> I have merged my TPE LSM with Mimi Zohar's shebang LSM and will be
>> releasing a version 3 soon. I have also added securityfs support to
>> shebang that will allow users to update the interpreter lis
On 11/07/17 16:21, Dietmar Eggemann wrote:
> On 11/07/17 07:39, Viresh Kumar wrote:
>> On 10-07-17, 14:46, Rafael J. Wysocki wrote:
>>> This particular change is about a new feature, so making it in the core is
>>> OK
>>> in two cases IMO: (a) when you actively want everyone to be affected by it
On Fri, Jun 30, 2017 at 9:20 PM,
wrote:
> From: Kuppuswamy Sathyanarayanan
>
> Added maintainer info for Whiskey Cove PMIC GPIO driver.
>
> Signed-off-by: Kuppuswamy Sathyanarayanan
>
Patch applied.
Yours,
Linus Walleij
On Wed, Jul 12, 2017 at 09:47:27AM +0200, Peter Rosin wrote:
> On 2017-07-12 09:03, Daniel Vetter wrote:
> > On Tue, Jul 11, 2017 at 02:12:26PM +0200, Peter Rosin wrote:
> >> On 2017-07-11 10:10, Daniel Vetter wrote:
> >>> Tiny nit you might want to improve (since you need to respin for my naming
>
On Thu, Jul 13, 2017 at 01:50:26PM +0200, Rafael J. Wysocki wrote:
> On Thu, Jul 13, 2017 at 11:43 AM, Alex Shi wrote:
> >
> > On 07/13/2017 03:07 PM, Tony Lindgren wrote:
> >> Hi,
> >>
> >> Looks like next-20170713 gives me a bunch of "suspicious
On Thu, 2017-07-13 at 11:05 +0100, Mark Brown wrote:
> On Thu, Jul 13, 2017 at 09:02:10AM +0100, Lee Jones wrote:
>
> > This patch has been rejected by Linus.
>
> > https://lkml.org/lkml/2017/7/7/579
>
> Hrm, when I used to push the register definition patches I did elide all
> the obviously re
On Thu, Jul 13, 2017 at 09:06:19AM +0200, Michal Hocko wrote:
> On Thu 13-07-17 14:58:06, Joey Lee wrote:
> > Hi Michal,
> >
> > Sorry for my delay.
> >
> > On Tue, Jul 11, 2017 at 10:25:32AM +0200, Michal Hocko wrote:
> > > On Mon 26-06-17 10:59:07, Michal Hocko wrote:
> > > > On Mon 26-06-17 1
Andy Lutomirski writes:
> On Tue, May 23, 2017 at 5:36 AM, Vitaly Kuznetsov wrote:
>> Andy Lutomirski writes:
>>
>>>
>>> Also, can you share the benchmark you used for these patches?
>>
>> I didn't do much while writing the patchset, mostly I was running the
>> attached dumb trasher (32 pthread
On 12/07/17 05:09, Viresh Kumar wrote:
> On 11-07-17, 16:06, Dietmar Eggemann wrote:
>> But in the meantime we're convinced that cpufreq_driver_fast_switch() is
>> not the right place to call arch_set_freq_scale() since for (future)
>> arm/arm64 fast-switch driver, the return value of
>> cpufreq_
On Thu, Jul 13, 2017 at 03:30:39PM +0300, Sagi Grimberg wrote:
> It seems weird that a subsystem has a serial.
The subsystem is more of a hack I admit. But we don't maintain
configurations for controllers in configfs, do we?
> I'm not sure that a dynamic controller should maintain
> a serial. Dyn
On 12/07/17 10:27, Viresh Kumar wrote:
> On 12-07-17, 10:31, Peter Zijlstra wrote:
>> So the problem with the thread is two-fold; one the one hand we like the
>> scheduler to directly set frequency, but then we need to schedule a task
>> to change the frequency, which will change the frequency an
On 07/11/2017 10:05 PM, Kirill A. Shutemov wrote:
>>> Can use your Signed-off-by for a [cleaned up version of your] patch?
>>
>> Sure.
>
> Another KASAN-releated issue: dumping page tables for KASAN shadow memory
> region takes unreasonable time due to kasan_zero_p?? mapped there.
>
> The patch b
On Wed, Jul 05, 2017 at 01:02:36PM -0700, Krister Johansen wrote:
> Hey Greg,
>
> > 4.9-stable review patch. If anyone has any objections, please let me know.
> >
> > --
> >
> > From: Masami Hiramatsu
> >
> >
> > [ Upstream commit 613f050d68a8ed3c0b18b9568698908ef7bbc1f7 ]
>
Hi Linus,
The following changes since commit 2ea659a9ef488125eb46da6eb571de5eae5c43f6:
Linux 4.12-rc1 (2017-05-13 13:19:49 -0700)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/thierry.reding/linux-pwm.git
tags/pwm/for-4.13-rc1
for you to fetch chang
Fix multiline comments style not to be reported by checkpatch.
Signed-off-by: Michal Simek
---
drivers/input/serio/xilinx_ps2.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/input/serio/xilinx_ps2.c b/drivers/input/serio/xilinx_ps2.c
index 14c40892ed82..47472
On Thu, Jul 13, 2017 at 01:44:10PM +0100, Richard Fitzgerald wrote:
> On Thu, 2017-07-13 at 11:05 +0100, Mark Brown wrote:
> > On Thu, Jul 13, 2017 at 09:02:10AM +0100, Lee Jones wrote:
> > > This patch has been rejected by Linus.
> > > https://lkml.org/lkml/2017/7/7/579
> > Hrm, when I used to
On Thu, Jul 13, 2017 at 03:30:39PM +0300, Sagi Grimberg wrote:
> It seems weird that a subsystem has a serial.
But that's actually how NVMe defines them. Which mean we first
need to fix our code to generate a serial number per subsystem,
and on top of that the patch from Johannes seems perfectly
This set of patches update the STM32 CRC driver.
It contains two corrections and one global Kconfig rework.
First correction is about the relaxed usage in scope of arm
platform usage, second about a unbind driver issue.
Last patch is about a Kconfig rework that make configuration
generic for STM32
Use the correct unregister_shashes function to
to remove the registered algo
Signed-off-by: Lionel Debieve
Reviewed-by: Fabien Dessenne
---
drivers/crypto/stm32/stm32_crc32.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/crypto/stm32/stm32_crc32.c
b/drivers/crypto
In case of arm soc support, readl and writel will
be optimized using relaxed functions
Signed-off-by: Lionel Debieve
Reviewed-by: Fabien Dessenne
---
drivers/crypto/stm32/stm32_crc32.c | 15 ---
1 file changed, 8 insertions(+), 7 deletions(-)
diff --git a/drivers/crypto/stm32/stm32
The complete stm32 module is rename as crypto
in order to use generic naming
Signed-off-by: Lionel Debieve
Reviewed-by: Fabien Dessenne
---
drivers/crypto/Makefile | 2 +-
drivers/crypto/stm32/Kconfig | 6 +++---
drivers/crypto/stm32/Makefile | 3 +--
3 files changed, 5 insertions(+), 6
On 13/07/17 13:40, Sudeep Holla wrote:
>
>
> On 11/07/17 16:21, Dietmar Eggemann wrote:
>> On 11/07/17 07:39, Viresh Kumar wrote:
>>> On 10-07-17, 14:46, Rafael J. Wysocki wrote:
[...]
>> Like I said in the other email, since for (future)
>> arm/arm64 fast-switch driver, the return value of
>>
On Thu, Jul 13, 2017 at 03:06:52PM +0200, Christoph Hellwig wrote:
> On Thu, Jul 13, 2017 at 03:30:39PM +0300, Sagi Grimberg wrote:
> > It seems weird that a subsystem has a serial.
>
> But that's actually how NVMe defines them. Which mean we first
> need to fix our code to generate a serial numb
Arnaldo,
Additionally I think we need to calculate the percentage with the sample
period,
not number of samples like perf-report.
What do you think about it ?
For examples, perf-annotate figure out the percentage with number of
samples like below
ui/gtk/annotate.c:
23 static int perf_gtk__
Hi Andrew,
Now is the merge window and we need to resubmit.
We will fix it when we will resubmit.
The version number was used for the ethtool information and module version and
will be removed.
devm_kzalloc - will be used for the allocation of the memory at initialization.
We used pr_ for mess
On Wed, Jul 12, 2017 at 09:29:17PM -0700, Andi Kleen wrote:
> On Wed, Jul 12, 2017 at 05:47:59PM -0500, Josh Poimboeuf wrote:
> > On Wed, Jul 12, 2017 at 03:30:31PM -0700, Andi Kleen wrote:
> > > Josh Poimboeuf writes:
> > > >
> > > > The ORC data format does have a few downsides compared to DWARF
Hi Andrew,
We will separate the patches when we will resubmit.
Aviad
On 7/12/2017 6:43 PM, Andrew Lunn wrote:
> On Wed, Jul 12, 2017 at 10:17:26PM +0800, Aviad Krawczyk wrote:
>
> Hi Avaid
>
>> +
>> +static void hinic_tx_timeout(struct net_device *netdev)
>> +{
>> +struct hinic_dev *nic_d
By submitting completed transfers to the system workqueue there is no
guarantee that completion events will be queued up in the correct order,
so if a large bulk transfer is being read with aio the data may arrive
in the wrong order.
Create a single-threaded workqueue for FunctionFS so that comple
On Thu, Jul 13, 2017 at 01:13:28PM +0200, Marek Szyprowski wrote:
> Hi Christoph,
>
> On 2017-07-05 19:33, Christoph Hellwig wrote:
> >On Mon, Jul 03, 2017 at 11:27:32AM +0200, Marek Szyprowski wrote:
> >>The main question here if we want to merge incomplete solution or not. As
> >>for now, there
As there is no way to actually query the hardware for the current clock
rate, now racalc_rate() just returns the last rate that was previously
set. But if the rate was not set yet, we return the bogus rate of 1000Hz.
The branch clocks actually have the same rate as their parent (xo_board),
so just
This adds documentation of device tree bindings for the STM32
HASH controller.
Signed-off-by: Lionel Debieve
---
.../devicetree/bindings/crypto/st,stm32-hash.txt | 30 ++
1 file changed, 30 insertions(+)
create mode 100644 Documentation/devicetree/bindings/crypto/st,stm32-
This set of patches adds a new crypto driver for STMicroelectronics stm32 HW.
This drivers uses the crypto API and provides with HW-enabled md5, sha1,
sha224, sha256 hash based algorithms.
It makes use of the crypto engine to support ahash requests.
This driver was successfully tested with tcrypt
This module register a HASH module that support multiples
algorithms: MD5, SHA1, SHA224, SHA256.
It includes the support of HMAC hardware processing corresponding
to the supported algorithms. DMA or IRQ mode are used depending
on data length.
Signed-off-by: Lionel Debieve
---
drivers/crypto/stm
On Thu, Jul 13, 2017 at 02:21:53PM +0100, Russell King - ARM Linux wrote:
> My conclusion of the dma_alloc_noncoherent() and dma_cache_sync() API
> when it was introduced is that it's basically a completely broken
> interface, and I've never seen any point to it. Maybe some of that is
> because it
On 07/12/2017 02:41 PM, Jaghathiswari Rankappagounder Natarajan wrote:
This patch has changes to w1.h/w1.c/w1_family.h generic files to
add (optional) hwmon support structures.
Signed-off-by: Jaghathiswari Rankappagounder Natarajan
Acked-by: Evgeniy Polyakov
---
v2
- made changes to support hw
Hi Linus,
Please pull fbdev changes for v4.13. There is nothing really major here,
just a couple of small bugfixes, improvements and cleanups.
Best regards,
--
Bartlomiej Zolnierkiewicz
Samsung R&D Institute Poland
Samsung Electronics
The following changes since commit 32c1431eea4881a6b17bd7c
On Thu, Jul 13, 2017 at 03:58:29PM +0300, Andrey Ryabinin wrote:
> On 07/11/2017 10:05 PM, Kirill A. Shutemov wrote:
> >>> Can use your Signed-off-by for a [cleaned up version of your] patch?
> >>
> >> Sure.
> >
> > Another KASAN-releated issue: dumping page tables for KASAN shadow memory
> > regi
Hi,
On 7/13/2017 5:20 PM, Rob Clark wrote:
> On Thu, Jul 13, 2017 at 1:35 AM, Sricharan R wrote:
>> Hi Vivek,
>>
>> On 7/13/2017 10:43 AM, Vivek Gautam wrote:
>>> Hi Stephen,
>>>
>>>
>>> On 07/13/2017 04:24 AM, Stephen Boyd wrote:
On 07/06, Vivek Gautam wrote:
> @@ -1231,12 +1237,18 @@ s
On Thu, Jul 13, 2017 at 11:05 AM, Sricharan R wrote:
> Hi Vivek,
>
> On 7/13/2017 10:43 AM, Vivek Gautam wrote:
>> Hi Stephen,
>>
>>
>> On 07/13/2017 04:24 AM, Stephen Boyd wrote:
>>> On 07/06, Vivek Gautam wrote:
@@ -1231,12 +1237,18 @@ static int arm_smmu_map(struct iommu_domain
*doma
On Thu, Jul 13, 2017 at 7:27 PM, Vivek Gautam
wrote:
> On Thu, Jul 13, 2017 at 11:05 AM, Sricharan R
> wrote:
>> Hi Vivek,
>>
>> On 7/13/2017 10:43 AM, Vivek Gautam wrote:
>>> Hi Stephen,
>>>
>>>
>>> On 07/13/2017 04:24 AM, Stephen Boyd wrote:
On 07/06, Vivek Gautam wrote:
> @@ -1231,12
From: Gabriel Fernandez
This patch exposes clk_gate_ops::is_enabled as functions
that can be directly called and assigned in places like this so
we don't need wrapper functions that do nothing besides forward
the call.
Signed-off-by: Gabriel Fernandez
Sugested by Stephen Boyd
---
drivers/clk/
From: Gabriel Fernandez
v5:
- return bool instead int for enable_power_domain_write_protection()
- add comment to explain use of CLK_OF_DECLARE_DRIVER()
- add comment to explain why we can't use read_poll_timeout()
- expose clk_gate_ops::is_enabled
- use of __clk_mux_determine_rate & cl
From: Gabriel Fernandez
This patch enables clocks for STM32H743 boards.
Signed-off-by: Gabriel Fernandez
for MFD changes:
Acked-by: Lee Jones
for DT-Bindings
Acked-by: Rob Herring
---
.../devicetree/bindings/clock/st,stm32h7-rcc.txt | 81 ++
drivers/clk/Makefile
On 07/13/2017 05:20 AM, Kefeng Wang wrote:
> No need to return value in queue work, kill ret variable.
Applied, thanks.
--
Jens Axboe
On 12/07/17 12:14, Peter Zijlstra wrote:
> On Wed, Jul 12, 2017 at 02:57:55PM +0530, Viresh Kumar wrote:
>> On 12-07-17, 10:31, Peter Zijlstra wrote:
>>> So the problem with the thread is two-fold; one the one hand we like the
>>> scheduler to directly set frequency, but then we need to schedule
On 13/07/17 14:08, Dietmar Eggemann wrote:
> On 13/07/17 13:40, Sudeep Holla wrote:
>>
>>
>> On 11/07/17 16:21, Dietmar Eggemann wrote:
>>> On 11/07/17 07:39, Viresh Kumar wrote:
On 10-07-17, 14:46, Rafael J. Wysocki wrote:
>
> [...]
>
>>> Like I said in the other email, since for (future)
On 07/13/2017 01:03 AM, Ram Pai wrote:
> On Tue, Jul 11, 2017 at 11:13:56AM -0700, Dave Hansen wrote:
>> On 07/05/2017 02:22 PM, Ram Pai wrote:
>>> +#ifdef CONFIG_PPC64_MEMORY_PROTECTION_KEYS
>>> +void arch_show_smap(struct seq_file *m, struct vm_area_struct *vma)
>>> +{
>>> + seq_printf(m, "Prot
The Allwinner SoCs usually come with a DSI encoder. Add a binding for it.
Signed-off-by: Maxime Ripard
---
Documentation/devicetree/bindings/display/sunxi/sun6i-dsi.txt | 85 +++-
1 file changed, 85 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/sunxi/sun6i-dsi.
The BananaPi M2M has an optional 1280x720 DSI panel. Since that panel is
optional, we can only show a DT patch that would show how to enable it.
Signed-off-by: Maxime Ripard
---
arch/arm/boot/dts/sun8i-r16-bananapi-m2m.dts | 39 +-
1 file changed, 39 insertions(+)
diff --git
The Bananapi M2-Magic is a board with an A33, a USB host and USB OTG
connectors, and 8GB eMMC, an AP6212 WiFi/Bluetooth chip and connectors for
DSI, CSI and GPIOs.
Signed-off-by: Maxime Ripard
---
arch/arm/boot/dts/Makefile | 1 +-
arch/arm/boot/dts/sun8i-r16-bananapi-m2m.dts
The LHR050H41 panel is the panel shipped with the BananaPi M2-Magic. Add a
driver for it.
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/panel/Kconfig | 9 +-
drivers/gpu/drm/panel/Makefile | 1 +-
drivers/gpu/drm/panel/panel-huarui-lhr050h41.c | 444 ++
It seems like the dotclock dividers are a bit less strict range, and can
operate even with a smaller than 6 divider. Loose the boundaries a bit.
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/sun4i/sun4i_dotclock.c | 20 +++-
1 file changed, 19 insertions(+), 1 deletion(-)
dif
The A33 has a MIPI-DSI block, along with its D-PHY. Let's add it in order
to use it in the relevant boards.
Signed-off-by: Maxime Ripard
---
arch/arm/boot/dts/sun8i-a33.dtsi | 50 -
1 file changed, 49 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/su
Some channel0 setup has to be done, no matter what the output interface is
(RGB, CPU, LVDS). Move that code into a common function in order to avoid
duplication.
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/sun4i/sun4i_tcon.c | 26 --
1 file changed, 16 insertions(+),
Just like we did for the TCON enable and disable, for historical reasons we
used to rely on the encoders calling the TCON mode_set function, while the
CRTC has a callback for that.
Let's implement it in order to reduce the boilerplate code.
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/sun4i
The "CPU" (or Intel 8080) interface uses a different interrupt called
TRI_FINISH (most likely TRI being for trigger) to notify the end of frames,
and hence the VBLANK period.
And that interrupt to the possible VBLANK interrupts source.
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/sun4i/sun4
So far, we've required all the TCON-connected encoders to call the TCON
enable and disable functions.
This was made this way because in the RGB/LVDS case, the TCON is the CRTC
and the encoder. However, in all the other cases (HDMI, TV, DSI, etc.), we
have another encoder down the road that needs t
On Thu, Jul 13, 2017 at 04:52:28PM +0300, Kirill A. Shutemov wrote:
> On Thu, Jul 13, 2017 at 03:58:29PM +0300, Andrey Ryabinin wrote:
> > On 07/11/2017 10:05 PM, Kirill A. Shutemov wrote:
> > >>> Can use your Signed-off-by for a [cleaned up version of your] patch?
> > >>
> > >> Sure.
> > >
> > >
Even though that function is defined in the TCON header, it's not defined
nor used anywhere. Remove the prototype.
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/sun4i/sun4i_tcon.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.h
b/drivers/gpu/drm/sun4i/
The atomic_check callback is optional, and we don't implement anything in
some parts of our drivers. Let's remove it.
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/sun4i/sun4i_layer.c | 7 ---
drivers/gpu/drm/sun4i/sun4i_rgb.c | 8
drivers/gpu/drm/sun4i/sun4i_tv.c| 8 --
Some options were not padded as they should, and the order in the Makefile
was chaotic. Fix that.
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/sun4i/Makefile | 26 +-
1 file changed, 13 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/sun4i/Makefile b/driv
regmap_init_mmio_clk allows to specify a clock that needs to be enabled
while accessing the registers.
However, that clock is retrieved through its clock ID, which means it will
lookup that clock based on the current device that registers the regmap,
and, in the DT case, will only look in that dev
The LHR050H41 is a 1280x700 4-lanes DSI panel.
Signed-off-by: Maxime Ripard
---
Documentation/devicetree/bindings/display/panel/huarui,lhr050h41.txt | 19
+++
1 file changed, 19 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/panel/huarui,lhr050h41.t
The depends on relationship is obvious, and using an if statement will
propagate it to every option without the need for each and every one of
them to define it.
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/sun4i/Kconfig | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --gi
Hi,
Here is an preliminary version of the MIPI-DSI support for the Allwinner
SoCs.
This controller can be found on a number of recent SoCs, such as the
A31, A33 or the A64.
Given the sparse documentation, there's a number of obscure areas, but
the current implementation has been tested with a 4-
Most of the Allwinner SoCs since the A31 share the same MIPI-DSI
controller.
While that controller is mostly undocumented, the code is out there and has
been cleaned up in order to be integrated into DRM. However, there's still
some dark areas that are a bit unclear about how the block exactly
ope
Huarui Lighting makes display panel, add it to the list of panels.
Signed-off-by: Maxime Ripard
---
Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt
b/Documentation/devicetree/bindings
On 07/13/2017 05:15 PM, Kirill A. Shutemov wrote:
>>
>> Hm. I don't see this:
>>
>> ...
>> [0.247532] 0xff9e9380-0xff9f 04G
>>p4d
>> [0.247733] 0xff9f-0x 24P
>>
Fixed coding style error flagged checkpatch.pl:
- ERROR: space prohibited after that open parenthesis '('
- WARNING: Block comments use * on subsequent lines
Signed-off-by: Shy More
Output after fixing coding style issues:
$KERN/scripts/checkpatch.pl -f
./media/atomisp/p
On 13/07/17 06:47, Gustavo A. R. Silva wrote:
> This structure is only stored in the ops field of a snd_soc_dai_driver
> structure. That field is declared const, so snd_soc_dai_ops structures
> that have this property can be declared as const also.
>
> Signed-off-by: Gustavo A. R. Silva
> ---
>
Our customer reported that Kernel text may be located on non-mirror
region (movable zone) when both address range mirroring feature and
KASLR are enabled.
The functions of address range mirroring feature are as follows.
- The physical memory region whose descriptors in EFI memory map have
EFI_ME
The original function process_e820_entry() only takes care of each
e820 entry passed.
And move the E820_TYPE_RAM checking logic into process_e820_entries().
And remove the redundent local variable 'addr' definition in
find_random_phys_addr().
Signed-off-by: Baoquan He
Acked-by: Kees Cook
---
Kernel text may be located in non-mirror regions (movable zone) when both
address range mirroring feature and KASLR are enabled.
The address range mirroring feature arranges such mirror region into
normal zone and other region into movable zone in order to locate
kernel code and data in mirror reg
Now process_e820_entry() is not limited to e820 entry processing, rename
it to process_mem_region(). And adjust the code comment accordingly.
Signed-off-by: Baoquan He
Acked-by: Kees Cook
---
arch/x86/boot/compressed/kaslr.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --gi
This makes process_e820_entry() be able to process any kind of memory
region.
Signed-off-by: Baoquan He
Acked-by: Kees Cook
---
arch/x86/boot/compressed/kaslr.c | 25 ++---
1 file changed, 14 insertions(+), 11 deletions(-)
diff --git a/arch/x86/boot/compressed/kaslr.c b/arc
[ Adding Vince...]
On 2017/07/12 12:48PM, Jiri Olsa wrote:
> On Mon, Jun 19, 2017 at 08:01:06PM +0530, Naveen N. Rao wrote:
> > Currently, there is no way to ask for signals to be delivered when a
> > certain number of sideband events have been logged into the ring buffer.
> > This is problemati
From: Casey Leedom
The new flag PCI_DEV_FLAGS_NO_RELAXED_ORDERING indicates that the Relaxed
Ordering Attribute should not be used on Transaction Layer Packets destined
for the PCIe End Node so flagged. Initially flagged this way are Intel
E5-26xx Root Complex Ports which suffer from a Flow Cont
The PCIe Device Control Register use the bit 4 to indicate that
whether the device is permitted to enable relaxed ordering or not.
But relaxed ordering is not safe for some platform which could only
use strong write ordering, so devices are allowed (but not required)
to enable relaxed ordering bit
From: Casey Leedom
cxgb4 Ethernet driver now queries PCIe configuration space to determine
if it can send TLPs to it with the Relaxed Ordering Attribute set.
Remove the enable_pcie_relaxed_ordering() to avoid enable PCIe Capability
Device Control[Relaxed Ordering Enable] at probe routine, to mak
Some devices have problems with Transaction Layer Packets with the Relaxed
Ordering Attribute set. This patch set adds a new PCIe Device Flag,
PCI_DEV_FLAGS_NO_RELAXED_ORDERING, a set of PCI Quirks to catch some known
devices with Relaxed Ordering issues, and a use of this new flag by the
cxgb4 dr
With this patch it's possible to use crypto user API form all
network namespaces, not only form the initial net ns.
Signed-off-by: Christian Langrock
---
crypto/crypto_user.c| 39 ++-
include/net/net_namespace.h | 1 +
2 files changed, 31 insertions(+
On Thu, Jul 13, 2017 at 07:17:56AM -0700, smklearn wrote:
> Fixed coding style error flagged checkpatch.pl:
> - ERROR: space prohibited after that open parenthesis '('
> - WARNING: Block comments use * on subsequent lines
>
> Signed-off-by: Shy More
>
> Output after fixing coding sty
On Thu, Jul 13, 2017 at 08:04:14PM +0800, Jin Yao wrote:
> +#define X86_BR_TYPE_MAP_MAX 16
> +
> +static int
> +common_branch_type(int type)
> +{
> + int i, mask;
> + const int branch_map[X86_BR_TYPE_MAP_MAX] = {
> + PERF_BR_CALL, /* X86_BR_CALL */
> + PER
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