From: Philipp Zabel
If the irq chip device is using the regmap of its parent device or
a syscon regmap that doesn't have an associated device at all,
allow the driver to provide its own device. That makes it possible
to reference the irq controller from other devices running on the
same regmap.
On Fri, 16 Jun, at 01:53:26PM, Tom Lendacky wrote:
> Boot data (such as EFI related data) is not encrypted when the system is
> booted because UEFI/BIOS does not run with SME active. In order to access
> this data properly it needs to be mapped decrypted.
>
> Update early_memremap() to provide an
Commit-ID: 0f2376eb0ff8851124c876eb81806d7ec1b421d1
Gitweb: http://git.kernel.org/tip/0f2376eb0ff8851124c876eb81806d7ec1b421d1
Author: Dmitry Vyukov
AuthorDate: Sat, 17 Jun 2017 11:15:27 +0200
Committer: Ingo Molnar
CommitDate: Thu, 22 Jun 2017 10:19:56 +0200
locking/atomic/x86: Un-mac
Commit-ID: f6dda790094b0d658b59cf108c52805f1f7c11e6
Gitweb: http://git.kernel.org/tip/f6dda790094b0d658b59cf108c52805f1f7c11e6
Author: Dmitry Vyukov
AuthorDate: Sat, 17 Jun 2017 11:15:28 +0200
Committer: Ingo Molnar
CommitDate: Thu, 22 Jun 2017 10:19:56 +0200
locking/atomic/x86: Use 's
Commit-ID: a884d25f383133c845d23c2cce929ba15994ca62
Gitweb: http://git.kernel.org/tip/a884d25f383133c845d23c2cce929ba15994ca62
Author: Dou Liyang
AuthorDate: Wed, 21 Jun 2017 18:14:21 +0800
Committer: Ingo Molnar
CommitDate: Thu, 22 Jun 2017 10:34:41 +0200
x86/apic: Make init_legacy_ir
Commit-ID: ff5060d9b2a73917dbf52654e29b08018e22a1f9
Gitweb: http://git.kernel.org/tip/ff5060d9b2a73917dbf52654e29b08018e22a1f9
Author: Dmitry Vyukov
AuthorDate: Sat, 17 Jun 2017 11:15:29 +0200
Committer: Ingo Molnar
CommitDate: Thu, 22 Jun 2017 10:20:12 +0200
locking/atomic: Add asm-ge
Commit-ID: 538ac46c64a6bc61e71982091fc1eef0026f322e
Gitweb: http://git.kernel.org/tip/538ac46c64a6bc61e71982091fc1eef0026f322e
Author: Dou Liyang
AuthorDate: Thu, 22 Jun 2017 11:15:41 +0800
Committer: Ingo Molnar
CommitDate: Thu, 22 Jun 2017 10:34:42 +0200
x86/apic: Make arch_init_msi/
Commit-ID: fb3a5055cd7098f8d1dd0cd38d717223255f
Gitweb: http://git.kernel.org/tip/fb3a5055cd7098f8d1dd0cd38d717223255f
Author: Kan Liang
AuthorDate: Mon, 19 Jun 2017 07:26:09 -0700
Committer: Ingo Molnar
CommitDate: Thu, 22 Jun 2017 11:07:08 +0200
perf/x86/intel: Add 1G DTLB lo
Commit-ID: 7353425881b170a24990b4d3bdcd14b1156fa8bd
Gitweb: http://git.kernel.org/tip/7353425881b170a24990b4d3bdcd14b1156fa8bd
Author: Andy Lutomirski
AuthorDate: Tue, 20 Jun 2017 22:22:08 -0700
Committer: Ingo Molnar
CommitDate: Thu, 22 Jun 2017 10:57:50 +0200
x86/ldt: Simplify the LD
Commit-ID: d54368127a11c6da0776c109a4c65a7b6a815f32
Gitweb: http://git.kernel.org/tip/d54368127a11c6da0776c109a4c65a7b6a815f32
Author: Andy Lutomirski
AuthorDate: Tue, 20 Jun 2017 22:22:09 -0700
Committer: Ingo Molnar
CommitDate: Thu, 22 Jun 2017 10:57:50 +0200
x86/mm: Remove reset_laz
Commit-ID: fe2d48b805d01e14ddb8144de01de43171eb516f
Gitweb: http://git.kernel.org/tip/fe2d48b805d01e14ddb8144de01de43171eb516f
Author: Jiri Bohac
AuthorDate: Fri, 16 Jun 2017 18:16:02 +0200
Committer: Ingo Molnar
CommitDate: Thu, 22 Jun 2017 11:10:23 +0200
x86/debug: Extend the lower b
On Thu, Jun 22, 2017 at 12:17 PM, Chunyan Zhang wrote:
> On 20 June 2017 at 09:37, Stephen Boyd wrote:
>> On 06/18, Chunyan Zhang wrote:
>>> + kint = DIV_ROUND_CLOSEST(((fvco - refin * nint * CCU_PLL_1M)/1) *
>>> + ((mask >> (shift + i)) + 1), refin * 100) << i;
>>> + cfg[index].
Commit-ID: 3c85d6db5e5f05ae6c3d7f5a0ceceb43746a5ca7
Gitweb: http://git.kernel.org/tip/3c85d6db5e5f05ae6c3d7f5a0ceceb43746a5ca7
Author: Frederic Weisbecker
AuthorDate: Mon, 19 Jun 2017 04:12:00 +0200
Committer: Ingo Molnar
CommitDate: Thu, 22 Jun 2017 11:30:01 +0200
sched/loadavg: Gener
Commit-ID: a0db971e4eb69fc84eb3d7ef94f718b483550b4a
Gitweb: http://git.kernel.org/tip/a0db971e4eb69fc84eb3d7ef94f718b483550b4a
Author: Frederic Weisbecker
AuthorDate: Mon, 19 Jun 2017 04:12:01 +0200
Committer: Ingo Molnar
CommitDate: Thu, 22 Jun 2017 11:30:01 +0200
nohz: Move idle bala
Commit-ID: 87f7583e9205fe5220677d0775f3a4d2b8fe8827
Gitweb: http://git.kernel.org/tip/87f7583e9205fe5220677d0775f3a4d2b8fe8827
Author: Kees Cook
AuthorDate: Wed, 21 Jun 2017 13:00:26 -0700
Committer: Ingo Molnar
CommitDate: Thu, 22 Jun 2017 10:36:25 +0200
locking/refcount: Create unche
Commit-ID: 387bc8b5536eeb0a92f4b4ab553539eaea2ac0ba
Gitweb: http://git.kernel.org/tip/387bc8b5536eeb0a92f4b4ab553539eaea2ac0ba
Author: Frederic Weisbecker
AuthorDate: Mon, 19 Jun 2017 04:12:02 +0200
Committer: Ingo Molnar
CommitDate: Thu, 22 Jun 2017 11:30:02 +0200
sched/fair: Spare id
From: Yang Zhang
use dynamic poll to reduce the cost when the event is not occurred during
poll. The idea is similar to current dynamic halt poll inside KVM:
Before entering idle, we will record the time. After wakeup from idle
(nomally, this is in interrupt handler), we will record the time too.
From: Yang Zhang
This patch introduce a new mechanism to poll for a while before
entering idle state.
David has a topic in KVM forum to describe the problem on current KVM VM
when running some message passing workload in KVM forum. Also, there
are some work to improve the performance in KVM, lik
From: Yang Zhang
Some latency-intensive workload will see obviously performance
drop when running inside VM. The main reason is that the overhead
is amplified when running inside VM. The most cost i have seen is
inside idle path.
This patch introduces a new mechanism to poll for a while before
en
On Thu 2017-06-22 16:23:32, Arvind Yadav wrote:
> File size before:
>text data bss dec hex filename
>3890 1152 8505013ba drivers/base/power/sysfs.o
>
> File size After adding 'const':
>text data bss dec hex filename
>
On 2017/6/22 19:22, root wrote:
From: Yang Zhang
Sorry to use wrong username to send patch because i am using a new
machine which don't setup the git config well.
Some latency-intensive workload will see obviously performance
drop when running inside VM. The main reason is that the overhead
The CCP and PSP devices part of AMD Secure Procesor may share the same
interrupt. Hence we expand the SP device to register a common interrupt
handler and provide functions to CCP and PSP devices to register their
interrupt callback which will be invoked upon interrupt.
Signed-off-by: Brijesh Sing
CCP device (drivers/crypto/ccp/ccp.ko) is part of AMD Secure Processor,
which is not dedicated solely to crypto. The AMD Secure Processor includes
CCP and PSP (Platform Secure Processor) devices.
This patch series adds a framework that allows functional component of the
AMD Secure Processor to be
The CCP device is part of the AMD Secure Processor. In order to expand
the usage of the AMD Secure Processor, create a framework that allows
functional components of the AMD Secure Processor to be initialized and
handled appropriately.
Signed-off-by: Brijesh Singh
---
drivers/crypto/Kconfig
Update pci and platform files to use devres interface to allocate the PCI
and iomap resources. Also add helper functions to consolicate module init,
exit and power mangagement code duplication.
Signed-off-by: Brijesh Singh
---
drivers/crypto/ccp/ccp-dev-v3.c | 8 +++
drivers/crypto/ccp/ccp-d
On Wed, Jun 21, 2017 at 02:10:03AM +0300, Yury Norov wrote:
> On Mon, Jun 19, 2017 at 04:58:16PM +0100, James Morse wrote:
> > Hi Yury,
[...]
> > This is confusing as 'is_compat_task()' matches one of aarch32 or ilp32, but
> > compat_user_mode(regs) only matches aarch32 as it checks the saved sp
File size before:
textdata bss dec hex filename
2280 776 43060 bf4 drivers/base/cpu.o
File size After adding 'const':
textdata bss dec hex filename
2384 648 43036 bdc drivers/base/cpu.o
Signed-off-by: Arvind Yadav
--
2017-06-22 19:22 GMT+08:00 root :
> From: Yang Zhang
>
> Some latency-intensive workload will see obviously performance
> drop when running inside VM. The main reason is that the overhead
> is amplified when running inside VM. The most cost i have seen is
> inside idle path.
> This patch introduce
On 06/22/2017 08:06 AM, Peter Rosin wrote:
> The redundant fb helper .load_lut is no longer used, and can not
> work right without also providing the fb helpers .gamma_set and
> .gamma_get thus rendering the code in this driver suspect.
>
Hi Peter,
STM32 chipsets supports 8-bit CLUT mode but th
On Thu, Jun 22, 2017 at 1:44 PM, Bu Tao wrote:
> 在 2017/6/17 5:51, Arnd Bergmann 写道:
>> On Fri, Jun 16, 2017 at 8:51 AM, Bu Tao wrote:
>>> +Optional properties for board device:
>>> +- ufs-hi3660-use-rate-B: specifies UFS rate-B
>>> +- ufs-hi3660-broken-fastauto : specifies no f
On 22/06/2017 13:22, root wrote:
> ==
>
> +poll_grow: (X86 only)
> +
> +This parameter is multiplied in the grow_poll_ns() to increase the poll time.
> +By default, the values is 2.
> +
> +=
Hi Mark,
Thanks for your review.
On 06/21/2017 05:13 PM, Mark Brown wrote:
On Wed, Jun 21, 2017 at 04:32:06PM +0200, Amelie Delaunay wrote:
A few minor stylistic things but overall this looks really nice, please
send followup patches fixing these style things.
+ /* Determine the first
On 06/21/2017 05:20 PM, Neil Armstrong wrote:
On 06/21/2017 04:32 PM, Amelie Delaunay wrote:
This patch adds the documentation of device tree bindings
for the STM32 SPI controller.
Signed-off-by: Amelie Delaunay
---
.../devicetree/bindings/spi/spi-stm32.txt | 60 ++
On 6/22/2017 12:14 PM, Jarkko Sakkinen wrote:
On Wed, Jun 21, 2017 at 04:29:36PM +0200, Roberto Sassu wrote:
tpm2_pcr_read() now uses tpm_buf functions to build the TPM command
to read a PCR. Those functions are preferred to passing a tpm2_cmd
structure, as they provide protection against buffer
File size before:
text data bss dec hex filename
594 328 0 922 39a drivers/base/topology.o
File size After adding 'const':
textdata bss dec hex filename
634 264 0 898 382 drivers/base/topology.o
Signed-off-by: Arvind
在 2017/6/17 5:51, Arnd Bergmann 写道:
On Fri, Jun 16, 2017 at 8:51 AM, Bu Tao wrote:
add ufs node document for hi3660
Signed-off-by: Bu Tao
---
.../devicetree/bindings/ufs/hi3660-ufs.txt | 58 ++
1 file changed, 58 insertions(+)
create mode 100644 Documentation/d
在 2017/6/22 19:51, Arnd Bergmann 写道:
On Thu, Jun 22, 2017 at 1:44 PM, Bu Tao wrote:
在 2017/6/17 5:51, Arnd Bergmann 写道:
On Fri, Jun 16, 2017 at 8:51 AM, Bu Tao wrote:
+Optional properties for board device:
+- ufs-hi3660-use-rate-B: specifies UFS rate-B
+- ufs-hi3660-broken-
File size before:
textdata bss dec hex filename
431002161 64 45325b10d drivers/block/rbd.o
File size After adding 'const':
textdata bss dec hex filename
432921969 64 45325b10d drivers/block/rbd.o
Signed-off-by: Arvind Yadav
Hi Arnd,
On 22 June 2017 at 19:15, Arnd Bergmann wrote:
> On Thu, Jun 22, 2017 at 12:17 PM, Chunyan Zhang wrote:
>> On 20 June 2017 at 09:37, Stephen Boyd wrote:
>>> On 06/18, Chunyan Zhang wrote:
>
+ kint = DIV_ROUND_CLOSEST(((fvco - refin * nint * CCU_PLL_1M)/1) *
+ ((ma
This patch refactor code to first load all firmware blobs
and then update modem proc to authenticate and boot fw.
Signed-off-by: Avaneesh Kumar Dwivedi
---
drivers/remoteproc/qcom_q6v5_pil.c | 19 ---
1 file changed, 8 insertions(+), 11 deletions(-)
diff --git a/drivers/remotepr
MSS proc on msm8996 can not access fw loaded region without stage
second translation of memory pages where mpss image are loaded.
This patch in order to enable mss boot on msm8996 invoke scm call
to switch or share ownership between apps and modem.
Signed-off-by: Avaneesh Kumar Dwivedi
---
drive
This patch add support for mss boot on msm8996. Major changes
include initializing mss rproc for msm8996, making appropriate
change for executing mss reset sequence etc.
Signed-off-by: Avaneesh Kumar Dwivedi
---
.../devicetree/bindings/remoteproc/qcom,q6v5.txt | 1 +
drivers/remoteproc/qcom_
Two different processors on a SOC need to switch memory ownership
during load/unload. To enable this, second level memory map table
need to be updated, which is done by secure layer.
This patch adds the interface for making secure monitor call for
memory ownership switching request.
Signed-off-by:
This patch set does following
1- Adds new scm call which helps in stage two translation of a memory
region
so that memory ownership sharing and switching can be achieved on
armv8 and later.
2- Enable mss remoteproc on msm8996
Major changes since last patch:
- R
File size before:
textdata bss dec hex filename
409111432 304 42647a697 drivers/block/cciss.o
File size After adding 'const':
textdata bss dec hex filename
410391304 304 42647a697 drivers/block/cciss.o
Signed-off-by: Arvind Yad
2017-06-22 1:24 GMT+03:00 Guenter Roeck :
> On Wed, Jun 21, 2017 at 05:49:43PM +0300, Kirill Esipov wrote:
>> DS3232/DS3234 has the temperature registers with a resolution of
>> 0.25 degree celsius. This enables to get the value through hwmon.
>>
>> # cat /sys/class/hwmon/hwmon0/temp1_input
>
From: Casey Leedom
The new flag PCI_DEV_FLAGS_NO_RELAXED_ORDERING indicates that the Relaxed
Ordering Attribute should not be used on Transaction Layer Packets destined
for the PCIe End Node so flagged. Initially flagged this way are Intel
E5-26xx Root Complex Ports which suffer from a Flow Cont
From: Casey Leedom
cxgb4 Ethernet driver now queries PCIe configuration space to determine
if it can send TLPs to it with the Relaxed Ordering Attribute set.
Signed-off-by: Casey Leedom
Signed-off-by: Ding Tianhong
---
drivers/net/ethernet/chelsio/cxgb4/cxgb4.h | 1 +
drivers/net/ethern
Some devices have problems with Transaction Layer Packets with the Relaxed
Ordering Attribute set. This patch set adds a new PCIe Device Flag,
PCI_DEV_FLAGS_NO_RELAXED_ORDERING, a set of PCI Quirks to catch some known
devices with Relaxed Ordering issues, and a use of this new flag by the
cxgb4 dr
The PCIe Device Control Register use the bit 4 to indicate that
whether the device is permitted to enable relaxed ordering or not.
But relaxed ordering is not safe for some platform which could only
use strong write ordering, so devices are allowed (but not required)
to enable relaxed ordering bit
On Thu, Jun 22, 2017 at 1:58 PM, Bu Tao wrote:
> 在 2017/6/22 19:51, Arnd Bergmann 写道:
>> On Thu, Jun 22, 2017 at 1:44 PM, Bu Tao wrote:
>>> 在 2017/6/17 5:51, Arnd Bergmann 写道:
On Fri, Jun 16, 2017 at 8:51 AM, Bu Tao wrote:
>>>
>>> I do not know wheher other SoC need to use the optional prop
On Wed, 21 Jun 2017, Andy Lutomirski wrote:
> On Wed, Jun 21, 2017 at 6:38 AM, Thomas Gleixner wrote:
> > That requires a conditional branch
> >
> > if (asid >= NR_DYNAMIC_ASIDS) {
> > asid = 0;
> >
> > }
> >
> > The question is whether 4 IDs wo
On Thu, 2017-06-22 at 17:34 +0530, Arvind Yadav wrote:
> File size before:
>text data bss dec hex filename
> 43100 2161 64 45325b10d drivers/block/rbd.o
>
> File size After adding 'const':
>text data bss dec hex filename
> 4
On Wed, 21 Jun 2017, Thiago Jung Bauermann wrote:
> Michael Ellerman writes:
> >> Notes:
> >> This patch applies on tip/smp/hotplug, it should probably be carried
> >> there.
> >
> > stop_machine_cpuslocked() doesn't exist in mainline so I think it has to
> > be carried there right?
>
> Yes.
Cavium ThunderX2 SMMUv3 implementation has two Silicon Erratas.
1. Errata ID #74
SMMU register alias Page 1 is not implemented
2. Errata ID #126
SMMU doesnt support unique IRQ lines and also MSI for gerror,
eventq and cmdq-sync
The following patchset does software workaround for these two
On 12/06/2017 20:49, Rafael J. Wysocki wrote:
> On Monday, June 12, 2017 05:55:10 PM Daniel Lezcano wrote:
>> Some hardware have clusters with different idle states. The current code does
>> not support this and fails as it expects all the idle states to be identical.
>>
>> Because of this, the Med
From: Linu Cherian
Cavium ThunderX2 implementation doesn't support second page in SMMU
register space. Hence, resource size is set as 64k for this model.
Signed-off-by: Linu Cherian
Signed-off-by: Geetha Sowjanya
---
drivers/acpi/arm64/iort.c | 15 ++-
1 files changed, 14 insert
From: Geetha Sowjanya
Cavium ThunderX2 SMMU doesn't support MSI and also doesn't have unique irq
lines for gerror, eventq and cmdq-sync.
New named irq "combined" is set as a errata workaround, which allows to
share the irq line by register single irq handler for all the interrupts.
Signed-off-b
MPX (without MAWA extension) cannot handle addresses above 47-bit, so we
need to make sure that MPX cannot be enabled if we already have VMA above
the boundary and forbid creating such VMAs once MPX is enabled.
The patch implements mpx_unmapped_area_check() which is called from all
variants of get
From: Linu Cherian
Cavium ThunderX2 SMMU implementation doesn't support page 1 register space
and PAGE0_REGS_ONLY option is enabled as an errata workaround.
This option when turned on, replaces all page 1 offsets used for
EVTQ_PROD/CONS, PRIQ_PROD/CONS register access with page 0 offsets.
SMMU r
On x86, 5-level paging enables 56-bit userspace virtual address space.
Not all user space is ready to handle wide addresses. It's known that
at least some JIT compilers use higher bits in pointers to encode their
information. It collides with valid pointers with 5-level paging and
leads to crashes.
Rename these helpers to be consistent with spelling of TASK_SIZE and
related constants.
Signed-off-by: Kirill A. Shutemov
---
arch/x86/include/asm/elf.h | 4 ++--
arch/x86/kernel/sys_x86_64.c | 2 +-
arch/x86/mm/hugetlbpage.c| 2 +-
arch/x86/mm/mmap.c | 10 +-
4 files
Most of things are in place and we can enable support of 5-level paging.
The patch makes XEN_PV dependent on !X86_5LEVEL. XEN_PV is not ready to
work with 5-level paging.
Signed-off-by: Kirill A. Shutemov
Reviewed-by: Juergen Gross
---
Documentation/x86/x86_64/5level-paging.txt | 64 ++
As Ingo requested I've split and updated last two patches for my previous
patchset.
Please review and consider applying.
Kirill A. Shutemov (5):
x86: Enable 5-level paging support
x86/mm: Rename tasksize_32bit/64bit to task_size_32bit/64bit
x86/mpx: Do not allow MPX if we have mappings abov
All bits and pieces now in place and we can allow userspace to have VMAs
above 47-bit.
Signed-off-by: Kirill A. Shutemov
---
arch/x86/include/asm/processor.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.
On 22.06.2017 11:23, Boris Brezillon wrote:
> On Thu, 22 Jun 2017 13:47:43 +0530
> Archit Taneja wrote:
>
>> On 06/22/2017 01:20 PM, Benjamin Gaignard wrote:
>>> 2017-06-20 19:31 GMT+02:00 Eric Anholt :
Archit Taneja writes:
> On 06/16/2017 08:13 PM, Eric Anholt wrote:
>>
Here's my attempt at a backport to 3.2. This is only tested on
x86_64 and I think I should introduce local variables for
vma_start_gap() in a few places. I had to cherry-pick commit
09884964335e "mm: do not grow the stack vma just because of an overrun
on preceding vma" before this one (which was
On Thu, 22 Jun 2017, Ingo Molnar wrote:
>
> * Nicolas Pitre wrote:
>
> > On Wed, 21 Jun 2017, Ingo Molnar wrote:
> >
> > > I've applied the first patch to the scheduler tree yesterday, but the
> > > other
> > > changes unfortunately conflicted with other pending scheduler work - could
> > > y
After commit 9e442aa6a753 ("x86: remove DMA_ERROR_CODE"), the inlining
decisions in the qat driver changed slightly, introducing a new false-positive
warning:
drivers/crypto/qat/qat_common/qat_algs.c: In function
'qat_alg_sgl_to_bufl.isra.6':
include/linux/dma-mapping.h:228:2: error: 'sz_out' may
Andi,
On Wed, 21 Jun 2017, Andi Kleen wrote:
I asked for proper cover letters with a proper PATCH prefix for the first
submission and a PATCH vN prefix for subsequent submissions politely more
than once.
I'm tired of your obnoxious refusal to cooperate with other people.
>From now on patches wh
在 2017/6/22 20:15, Arnd Bergmann 写道:
On Thu, Jun 22, 2017 at 1:58 PM, Bu Tao wrote:
在 2017/6/22 19:51, Arnd Bergmann 写道:
On Thu, Jun 22, 2017 at 1:44 PM, Bu Tao wrote:
在 2017/6/17 5:51, Arnd Bergmann 写道:
On Fri, Jun 16, 2017 at 8:51 AM, Bu Tao wrote:
I do not know wheher other SoC need
On Thu, 22 Jun 2017 14:29:07 +0200
Andrzej Hajda wrote:
> On 22.06.2017 11:23, Boris Brezillon wrote:
> > On Thu, 22 Jun 2017 13:47:43 +0530
> > Archit Taneja wrote:
> >
> >> On 06/22/2017 01:20 PM, Benjamin Gaignard wrote:
> >>> 2017-06-20 19:31 GMT+02:00 Eric Anholt :
> Archit Tan
From: Sameer Nanda
Under each thermal zone there is a file called "mode". Writing enabled
or disabled to this file allows a given thermal zone to be enabled or
disabled. Honor writes to this file by enabling or disabling the
polling timers.
With this change, in the acpi_thermal_add path, acpi_th
On Tue, 20 Jun 2017, Bastien Nocera wrote:
> This driver does 2 things:
> - Apply the MULTI_INPUT quirk to create separate joypad device nodes
>for each one of the 4 connectors.
> - Rename the input devices so that their names are different, and allow
>users to recognise which device cor
On 20/06/17 14:23, Christoph Hellwig wrote:
> On Wed, May 24, 2017 at 11:24:27AM +0100, Vladimir Murzin wrote:
>> This patch adds a simple implementation of mmap to dma_noop_ops.
>
> Currently we use dma_common_mmap as the generic fallback if a dma_ops
> instance doesn't implement a mmap method.
On 20/06/17 14:24, Christoph Hellwig wrote:
>> -sg_dma_address(sg) = (dma_addr_t)virt_to_phys(va);
>> +sg_dma_address(sg) = (dma_addr_t)(virt_to_phys(va) -
>> PFN_PHYS(dev->dma_pfn_offset));
>
> Needs a line break instead of the overly long line.
Will do.
>
> Otherwise
On Thu, Jun 22, 2017 at 01:30:45PM +0100, Ben Hutchings wrote:
> Here's my attempt at a backport to 3.2. This is only tested on
> x86_64 and I think I should introduce local variables for
> vma_start_gap() in a few places. I had to cherry-pick commit
> 09884964335e "mm: do not grow the stack vma
On Wed, 2017-06-21 at 20:07 +0800, John Crispin wrote:
> Hi
>
> comments inline
>
>
> > +static int mtk_pwm_clk_enable(struct pwm_chip *chip, struct pwm_device
> > *pwm)
> > +{
> > + ret = clk_prepare_enable(pc->clks[MTK_CLK_PWM1 + pwm->hwpwm]);
> > + if (ret < 0) {
> > + clk_dis
Added support for suspend/resume functionality for the ADC IP
in sama5d2 SoC.
In order to enter Suspend to ram mode (backup + self refresh mode for
memory), in which the ADC IP is no longer powered, we need to reset the
pins to default state, for the scenario when they are also used for I2C
bus to
On Thu, Jun 22, 2017 at 09:47:46AM +0200, Jiri Slaby wrote:
> On 06/14/2017, 03:27 PM, Josh Poimboeuf wrote:
> > I agree with all your comments, will fix them all. Thanks for the
> > review.
>
> This is not the correct way:
> ++ if (flags & O_WRONLY)
> ++ cmd = ELF_C_WRITE;
> ++
From: Laurentiu Tudor
dpni.c is using byte order macros and error codes but does
not explicitly include the required kernel header, so add it.
Signed-off-by: Laurentiu Tudor
---
drivers/staging/fsl-dpaa2/ethernet/dpni.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/staging/fsl-
It's an 8 MiB flash with 4 KiB erase sectors.
Signed-off-by: Harry Chou
---
drivers/mtd/spi-nor/spi-nor.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index dea8c9c..1f84765 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/driv
On Mon, Jun 19, 2017 at 04:40:04PM +0200, Thomas Breitung wrote:
> The bits of BWC, DAHTS and SAHTS in the DMA mode register must be cleared
> before a new value can be or-ed in.
Applied, thanks
--
~Vinod
On 20/06/17 14:42, Christoph Hellwig wrote:
> Wouldn't the smal patch below solve the same issue in a simple way?
>
> diff --git a/drivers/base/dma-coherent.c b/drivers/base/dma-coherent.c
> index 640a7e63c453..e8f8447d705b 100644
> --- a/drivers/base/dma-coherent.c
> +++ b/drivers/base/dma-cohere
On Wed, 2017-06-21 at 10:48 -0700, Brian Norris wrote:
>
> Yes, that all sounds nice. But for my sake, can you describe better
> what's actually going on there (e.g., can you point me at which code
> does this)?
It's much easier with mac80211, it has all the state. Basically the
reconfig is in i
On Thu, 2017-06-22 at 14:46 +0200, Willy Tarreau wrote:
> On Thu, Jun 22, 2017 at 01:30:45PM +0100, Ben Hutchings wrote:
> > Here's my attempt at a backport to 3.2. This is only tested on
> > x86_64 and I think I should introduce local variables for
> > vma_start_gap() in a few places. I had to c
On Wed, 2017-06-21 at 11:27 -0700, Brian Norris wrote:
>
> > I'm not sure what you mean by "we need to atually stop all the
> > virtual interfaces ([...]) first".
>
> Judging by your following comments, I may have been completely
> mistaken.
> (But that's why I asked you folks!)
:)
> > There ar
On 06/22/2017 11:29 AM, Ingo Molnar wrote:
> Note that this patch breaks in various cross-builds - here's the Alpha
> defconfig
> build:
>
> /home/mingo/tip/kernel/sched/debug.c: In function 'print_rt_rq':
> /home/mingo/tip/kernel/sched/debug.c:556:60: error: 'struct rt_rq' has no
> member
> n
As the comparison uses process substitution to pass files after
conversion to DTS format, the diff header doesn't show the real
filenames, but the names of the file descriptors used:
--- /dev/fd/63 2017-06-22 11:21:47.531637188 +0200
+++ /dev/fd/62 2017-06-22 11:21:47.531637188 +0200
Th
Thiago Jung Bauermann writes:
> Michael Ellerman writes:
>> Thiago Jung Bauermann writes:
>>
>>> Calling arch_update_cpu_topology from a CPU hotplug state machine callback
>>> hits a deadlock because the function tries to get a read lock on
>>> cpu_hotplug_lock while the state machine still hol
On Thu, Jun 22, 2017 at 01:58:11PM +0100, Ben Hutchings wrote:
> On Thu, 2017-06-22 at 14:46 +0200, Willy Tarreau wrote:
> > On Thu, Jun 22, 2017 at 01:30:45PM +0100, Ben Hutchings wrote:
> > > Here's my attempt at a backport to 3.2. This is only tested on
> > > x86_64 and I think I should introdu
On Wed, Jun 21, 2017 at 4:09 PM, Arnd Bergmann wrote:
> Without CONFIG_I2C, we get a build failure:
>
> sound/soc/codecs/es8316.c:633:1: error: data definition has no type or
> storage class [-Werror]
> sound/soc/codecs/es8316.c:633:1: error: type defaults to 'int' in declaration
> of 'module_i2
On 22.06.2017 14:41, Boris Brezillon wrote:
> On Thu, 22 Jun 2017 14:29:07 +0200
> Andrzej Hajda wrote:
>
>> On 22.06.2017 11:23, Boris Brezillon wrote:
>>> On Thu, 22 Jun 2017 13:47:43 +0530
>>> Archit Taneja wrote:
>>>
On 06/22/2017 01:20 PM, Benjamin Gaignard wrote:
> 2017-06-20 1
On 20/06/17 14:49, Christoph Hellwig wrote:
> On Wed, May 24, 2017 at 11:24:29AM +0100, Vladimir Murzin wrote:
>> This patch introduces default coherent DMA pool similar to default CMA
>> area concept. To keep other users safe code kept under CONFIG_ARM.
>
> I don't see a CONFIG_ARM in the code, a
Add a new IORESOURCE_ALLOCATED flag that is automatically used
when alloc_resource() is used internally in kernel/resource.c
and free_resource() now takes this flag into account.
The core of __request_region() was factored out into a new function
called __request_declared_region() that needs struc
In order to make request_*muxed_region() behave more like
mutex_lock(), a possible failure case needs to be eliminated.
When drivers do not properly share the same I/O region, e.g.
one is using request_region() and the other is using
request_muxed_region(), the kernel didn't warn the user about it.
Use the new request_declared_muxed_region() macro to
synchronize access to the I/O port pair 0xcd6 / 0xcd7.
At the same time, remove the long lifetime request_region()
call to reserve these I/O ports, so the sp5100_tco watchdog
driver can also load.
This fixes an old regression in Linux 4.4-rc4,
Use the new request_declared_muxed_region() macro to synchronize
accesses to the SB800 I/O port pair (0xcd6 / 0xcd7) with the
PCI quirk for isochronous USB transfers and with the i2c-piix4
driver.
At the same time, remove the long lifetime request_region() call
to reserve these I/O ports, similarl
This patch series fixes a regression introduced by:
commit 2fee61d22e606fc99ade9079fda15fdee83ec33e
Author: Christian Fetzer
Date: Thu Nov 19 20:13:48 2015 +0100
i2c: piix4: Add support for multiplexed main adapter in SB800
The regression caused sp5100_tco fail to load:
sp5100_tco: SP510
This patch uses the previously introduced macro called
request_declared_muxed_region() to synchronize access to
the I/O port pair 0xcd6 / 0xcd7 on SB800.
These I/O ports are also used by i2c-piix4 and sp5100_tco,
so synchronization is necessary. The other drivers will also
be modified to use the n
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