On Fri, Jun 16, 2017 at 10:45:55AM +0200, Michal Hocko wrote:
>On Fri 16-06-17 16:11:42, Wei Yang wrote:
>> Well, I love this patch a lot. We don't need to put the hotadd memory in one
>> zone and move it to another. This looks great!
>>
>> On Mon, May 15, 2017 at 10:58:24AM +0200, Michal Hocko wr
Hi!
This series adds support for an 8-bit clut mode in the atmel-hlcdc
driver.
For various reasons I have only tested it with the fbdev interface,
and am therefore not really sure if it works w/o patch 2 and 3.
Also, when using it with the fbdev emulation layer, something seems
to allocate the f
DRM drivers supporting clut may want a convenient way to only use
non-default .gamma_set and .gamma_get ops in the drm_fb_helper_funcs
in order to avoid the following
/*
* The driver really shouldn't advertise pseudo/directcolor
* visuals if it can't deal with the palette
All layers of chips support this, the only variable is the base address
of the lookup table in the register map.
Signed-off-by: Peter Rosin
---
drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c | 48 +
drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c| 13 +++
drivers/gp
The clut is also synchronized with the drm gamma_lut state.
Signed-off-by: Peter Rosin
---
drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c | 49 ++
drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c | 12 +--
drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h | 4 +++
3 files
On Fri, Jun 9, 2017 at 9:45 AM, Richard Genoud wrote:
> 2017-06-09 9:42 GMT+02:00 Linus Walleij :
>> On Thu, Jun 1, 2017 at 10:08 PM, Ralph Sennhauser
>> wrote:
>>
>>> As it turns out more than just Armada 370 and XP support using GPIO
>>> lines as PWM lines. For example the Armada 38x family has
On 9 June 2017 at 11:01, Ard Biesheuvel wrote:
> On 8 June 2017 at 02:37, Kees Cook wrote:
>> On Wed, Jun 7, 2017 at 1:54 AM, Ard Biesheuvel
>> wrote:
>>> On 7 June 2017 at 03:12, Kees Cook wrote:
On Tue, Jun 6, 2017 at 10:17 AM, Mark Rutland wrote:
> On Tue, Jun 06, 2017 at 05:13:07P
On Fri, Jun 9, 2017 at 12:09 PM, Gregory CLEMENT
wrote:
> In some place in the driver regmap_update_bits was misused. Indeed the
> last argument is not the value of the bit (or group of bits) itself but
> the mask value inside the register.
>
> So when setting the bit N, then the value must be BI
of_device_ids are not supposed to change at runtime. All functions
working with of_device_ids provided by work with const
of_device_ids. So mark the non-const structs as const.
File size before:
textdata bss dec hex filename
2376 808 1283312 cf0 drivers/crypt
On Mon, Jun 12, 2017 at 5:34 PM, Gregory CLEMENT
wrote:
> In some place in the driver regmap_update_bits was misused. Indeed the
> last argument is not the value of the bit (or group of bits) itself but
> the mask value inside the register.
>
> So when setting the bit N, then the value must be BI
On Fri, Jun 16, 2017 at 06:57:30AM +0200, Christophe JAILLET wrote:
> Le 15/06/2017 à 19:20, Mark Brown a écrit :
> > if (!of_property_read_u32(node, "rockchip,playback-channels", &val)) {
> > if (val >= 2 && val <= 8)
> > soc_dai->playback.channels_max = val;
On 06/06/2017 06:35 AM, Ram Pai wrote:
> The value of the AMR register at the time of the exception
> is made available in gp_regs[PT_AMR] of the siginfo.
But its already available there in uctxt->uc_mcontext.regs->amr
while inside the signal delivery context in the user space. The
pt_regs already
On Mon, Jun 12, 2017 at 5:34 PM, Gregory CLEMENT
wrote:
> The offset property of the pinctrl node, when a regmap is used in the
> device tree, was never used nor documented in the binding. Moreover, the
> compatible string is enough to let the driver know which offset using.
>
> So this patch rem
On Mon, Jun 12, 2017 at 5:34 PM, Gregory CLEMENT
wrote:
> From: Russell King
>
> Armada 8040 also needs orion pinctrl, and as these symbols are only
> selected, there's no need to make them depend on PLAT_ORION.
>
> Reviewed-by: Thomas Petazzoni
> Signed-off-by: Russell King
> Signed-off-by: G
On Mon, Jun 12, 2017 at 5:34 PM, Gregory CLEMENT
wrote:
> This commit makes sure the drivers for the Armada 7K/8K pin controllers
> are enabled.
>
> Reviewed-by: Thomas Petazzoni
> Signed-off-by: Gregory CLEMENT
Acked-by: Linus Walleij
Please merge this through ARM SoC.
Yours,
Linus Walleij
On Mon, Jun 12, 2017 at 5:34 PM, Gregory CLEMENT
wrote:
> From: Hanna Hawa
>
> This commit adds a pinctrl driver for the pin-muxing controller found in
> the AP806 part of the Marvell Armada 7K and 8K SoCs. Its register
> interface is compatible with the one used by previous mvebu pin
> controll
On Mon, Jun 12, 2017 at 5:34 PM, Gregory CLEMENT
wrote:
> From: Hanna Hawa
>
> This commit adds a pinctrl driver for the CP110 part of the Marvell
> Armada 7K and 8K SoCs. The Armada 7K has a single CP110, where almost all
> the MPP pins are available. On the other side, the Armada 8K has two
>
Hi Heiko,
On 2017/6/15 23:10, Heiko Stuebner wrote:
Hi Frank,
Am Donnerstag, 15. Juni 2017, 15:23:16 CEST schrieb Frank Wang:
From: Finley Xiao
Add a efuse node in the device tree for the rk3228 SoC.
Signed-off-by: Finley Xiao
---
arch/arm/boot/dts/rk322x.dtsi | 17 +
1
On Mon, Jun 12, 2017 at 5:34 PM, Gregory CLEMENT
wrote:
> From: Hanna Hawa
>
> This commit adds a pinctrl driver for the CP110 part of the Marvell
> Armada 7K and 8K SoCs. The Armada 7K has a single CP110, where almost all
> the MPP pins are available. On the other side, the Armada 8K has two
>
On Fri, Jun 16, 2017 at 10:16:30AM +0200, Ingo Molnar wrote:
>
> * kernel test robot wrote:
>
> > Greetings,
> >
> > 0day kernel testing robot got the below dmesg and the first bad commit is
> >
> > https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master
> >
> > commit c88d
Sysctl test will fail in some items if the value of /proc/sys/kernel
/sysctrl_writes_strict is 0 as the default value in kernel older than v4.5.
Make this test more robust and compatible with older kernels by checking and
update sysctrl_writes_strict value and restore it when test is done.
Signed
On Mon, Jun 12, 2017 at 5:34 PM, Gregory CLEMENT
wrote:
> The Armada 7K and 8K SoCs use the same gpio controller as most of the
> other mvebu SoCs. However, the main difference is that the GPIO
> controller is part of a bigger system controller, and a syscon is used to
> control the overall syste
warning: cast to restricted __le16
Signed-off-by: Jaya Durga
---
drivers/staging/wlan-ng/hfa384x_usb.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/staging/wlan-ng/hfa384x_usb.c
b/drivers/staging/wlan-ng/hfa384x_usb.c
index a812e55..0e95e45 100644
--- a/drivers/st
Hi Michael,
On Friday 16 June 2017 10:42 AM, Michael Ellerman wrote:
>
> That function (perf_get_regs_user()) didn't exist until 4.7, ie:
>
> ed4a4ef85cf5 ("powerpc/perf: Add support for sampling interrupt register
> state")
>
> So there must be something else going on.
>
> I'll hold off on mergi
Am Freitag, 16. Juni 2017, 17:24:23 CEST schrieb Frank Wang:
> Hi Heiko,
>
> On 2017/6/15 23:10, Heiko Stuebner wrote:
> > Hi Frank,
> >
> > Am Donnerstag, 15. Juni 2017, 15:23:16 CEST schrieb Frank Wang:
> >> From: Finley Xiao
> >>
> >> Add a efuse node in the device tree for the rk3228 SoC.
>
+ Heiner.
On 15/06/17 17:18, Jerome Brunet wrote:
> Add support for the interrupt gpio controller found on Amlogic's meson
> SoC family.
>
> Unlike what the IP name suggest, it is not directly linked to the gpio
> subsystem. This separate controller is able to spy on the SoC pad. It is
> essentia
of_device_ids are not supposed to change at runtime. All functions
working with of_device_ids provided by work with const
of_device_ids. So mark the non-const structs as const.
Signed-off-by: Arvind Yadav
---
drivers/mtd/spi-nor/cadence-quadspi.c | 2 +-
1 file changed, 1 insertion(+), 1 deleti
On Fri, Jun 16, 2017 at 02:57:08PM +0530, Jaya Durga wrote:
> warning: cast to restricted __le16
What does this mean? It doesn't tell us why you are doing what you are
doing here.
Please be much more specific and descriptive.
thanks,
greg k-h
On Fri, Jun 16, 2017 at 10:20:04AM +0200, Johannes Thumshirn wrote:
> Strange, as I tested with nvme-loop all the time...
Yeah, it's actually there, but for some reason find on sysfs
behaves strange:
root@testvm:~# find /sys -name uuid
root@testvm:~# cat /sys/class/nvme/nvme2/nvme2n1/uuid
6665a6
On an AMD Carrizo laptop, when EHCI runtime PM is enabled, EHCI ports do
not respond to any device plugging event.
As Alan Stern points out [1], the PME signal is not enabled when
controller is in D3, therefore it's not being woken up when new deivces
get plugged in.
Testing shows PME signal work
This series adds support for usb2 on RK3328 SoCs.
Tested on RK3328 evaluation board.
William Wu (2):
arm64: dts: rockchip: add usb2 nodes for RK3328 SoCs
arm64: dts: rockchip: enable usb2 for RK3328 evaluation board
arch/arm64/boot/dts/rockchip/rk3328-evb.dts | 25 ++
arch/arm64/boot
Rockchip's RK3328 evaluation board has one usb2 otg controller
and one usb2 host controller which consist of EHCI and OHCI.
Each usb controller connects with one usb2 phy port through
UTMI+ interface. Let's enable them to support usb2 on RK3328
evaluation board.
Signed-off-by: William Wu
---
arc
This patch adds usb2 otg/host controllers and phys nodes
for Rockchip RK3328 SoCs.
Signed-off-by: William Wu
---
arch/arm64/boot/dts/rockchip/rk3328.dtsi | 76
1 file changed, 76 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
b/arch/arm64/b
On Fri, Jun 16, 2017 at 3:52 PM, Pali Rohár wrote:
> Should not this check to be rather:
>
> (kbd_token_bits != 0 && (kbd_token_bits & BIT(KBD_LED_OFF_TOKEN)) !=
> BIT(KBD_LED_OFF_TOKEN))
>
> To express that we have at least one token at it is different from
> KBD_LED_OFF_TOKEN token?
Yes, this
On 06/16/2017 11:40 AM, Christoph Hellwig wrote:
> On Fri, Jun 16, 2017 at 10:20:04AM +0200, Johannes Thumshirn wrote:
>> Strange, as I tested with nvme-loop all the time...
>
> Yeah, it's actually there, but for some reason find on sysfs
> behaves strange:
>
> root@testvm:~# find /sys -name uuid
On Wed, 2017-06-14 at 03:01:25 UTC, Alexey Kardashevskiy wrote:
> When trapped on WARN_ON(), report_bug() is expected to return
> BUG_TRAP_TYPE_WARN so the caller could increment NIP by 4 and continue.
> The __builtin_constant_p() path of the PPC's WARN_ON() calls (indirectly)
> __WARN_FLAGS() whic
034 ("of: Provide dummy
> > of_device_compatible_match() for compile-testing"), but reverting it
> > doesn't help. It seems like yesterday's linux-next also hangs. Right
> > now I cannot continue with debugging, but if nothing will get clear,
> > I'll back
of_device_ids are not supposed to change at runtime. All functions
working with of_device_ids provided by work with const
of_device_ids. So mark the non-const structs as const.
File size before:
textdata bss dec hex filename
89081096 624 106282984 drivers/block
On Fri, Jun 16, 2017 at 11:48:32AM +0200, Johannes Thumshirn wrote:
> On 06/16/2017 11:40 AM, Christoph Hellwig wrote:
> > On Fri, Jun 16, 2017 at 10:20:04AM +0200, Johannes Thumshirn wrote:
> >> Strange, as I tested with nvme-loop all the time...
> >
> > Yeah, it's actually there, but for some re
On 06/16/2017 11:58 AM, Christoph Hellwig wrote:
> Heh. Now we just need the nvme-cli patches to verify it independently :)
I'm on it ;-)
--
Johannes Thumshirn Storage
jthumsh...@suse.de+49 911 74053 689
SUSE LINUX GmbH, M
On 14-06-17, 18:13, Mark Brown wrote:
> On Mon, May 15, 2017 at 04:17:13PM +0530, Viresh Kumar wrote:
> > > I think you need to be looking at some combination of getting the
> > > devices you're interested in started up early and more precisely
> > > describing the end result you're trying to achi
Hi Peter,
On Fri, 16 Jun 2017 11:12:25 +0200
Peter Rosin wrote:
> All layers of chips support this, the only variable is the base address
> of the lookup table in the register map.
>
> Signed-off-by: Peter Rosin
> ---
> drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c | 48
> +
On Fri, 2017-06-16 at 10:35 +0100, Marc Zyngier wrote:
> + Heiner.
>
> On 15/06/17 17:18, Jerome Brunet wrote:
> > Add support for the interrupt gpio controller found on Amlogic's meson
> > SoC family.
> >
> > Unlike what the IP name suggest, it is not directly linked to the gpio
> > subsystem. T
This patch adds support to the JESD216B standard and parses the SFDP
tables to dynamically initialize the 'struct spi_nor_flash_parameter'.
Signed-off-by: Cyrille Pitchen
---
Hi all,
starting a new series since most patches of previous series have already
been merged into the spi-nor/next branch
On Friday 16 June 2017 17:46:58 Kai-Heng Feng wrote:
> On Fri, Jun 16, 2017 at 3:52 PM, Pali Rohár wrote:
> > Should not this check to be rather:
> >
> > (kbd_token_bits != 0 && (kbd_token_bits & BIT(KBD_LED_OFF_TOKEN)) !=
> > BIT(KBD_LED_OFF_TOKEN))
> >
> > To express that we have at least one t
On Fri, Jun 16, 2017 at 10:52 AM, Pali Rohár wrote:
> On Friday 16 June 2017 15:35:39 Kai-Heng Feng wrote:
>> - if (kbd_token_bits != 0 || ret == 0)
>> + /*
>> + * If KBD_LED_OFF_TOKEN is the only token,
>> + * consider there is no keyboard backlight.
>> + */
>> + if ((
This adds support for the Synopsys Designware HDMI RX PHY e405. This
phy receives and decodes HDMI video that is delivered to a controller.
Main features included in this driver are:
- Equalizer algorithm that chooses the phy best settings
according to the detected HDMI cable chara
This is an initial submission for the Synopsys Designware HDMI RX
Controller Driver. This driver interacts with a phy driver so that
a communication between them is created and a video pipeline is
configured.
The controller + phy pipeline can then be integrated into a fully
featured system that ca
Document the bindings for the Synopsys Designware HDMI RX.
Signed-off-by: Jose Abreu
Cc: Carlos Palminha
Cc: Rob Herring
Cc: Mark Rutland
Cc: Mauro Carvalho Chehab
---
.../devicetree/bindings/media/snps,dw-hdmi-rx.txt | 41 ++
1 file changed, 41 insertions(+)
create mod
The Synopsys Designware HDMI RX controller is an HDMI receiver controller that
is responsible to process digital data that comes from a phy. The final result
is a stream of raw video data that can then be connected to a video DMA, for
example, and transfered into RAM so that it can be displayed.
T
Add a entry for Synopsys Designware HDMI Receivers drivers
and phys.
Signed-off-by: Jose Abreu
Cc: Carlos Palminha
---
MAINTAINERS | 7 +++
1 file changed, 7 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 053c3bd..e798040 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -11294,6 +
Remove excess member description to fix following warnings in sphinx
build:
Excess struct/union/enum/typedef member 'ver_major' description in
'fsl_mc_device_id'
Excess struct/union/enum/typedef member 'ver_minor' description in
'fsl_mc_device_id'
Signed-off-by: sayli karnik
---
include/linux/mo
when building with make C=1 CF=-D__CHECK_ENDIAN__
drivers/staging/wlan-ng/hfa384x_usb.c:3383:36: warning: cast to restricted
__le16
fixed by using the le16_to_cpus function.
Signed-off-by: Jaya Durga
---
drivers/staging/wlan-ng/hfa384x_usb.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(
Hi,
As the previous discussed on http://crosreview.com/379681, we have hit a
failure [0] of ec's xfer, when we support the spi's pd to turn on/off.
(Says: support the Sdioaudio pd of rk3399 on http://crosreview.com/378562)
[0]:
..
[ 5.579694 ] cros-ec-spi spi5.0: EC failed to respond in time
Hi Geert,
On Fri, Jun 16, 2017 at 4:18 PM, Geert Uytterhoeven
wrote:
> Hi Magnus,
>
> On Thu, Jun 15, 2017 at 12:29 PM, Magnus Damm wrote:
>> Now when both 32-bit and 64-bit code inside the driver is using
>> fwspec it is possible to replace the utlb handling with fwspec ids
>> that get populate
Correct function parameter in kernel-doc comment to fix following
warnings in the sphinx build:
.//drivers/net/phy/phy.c:259: warning: No description found for
parameter 'features'
.//drivers/net/phy/phy.c:259: warning: Excess function parameter
'feature' description in 'phy_lookup_setting'
Signe
On Sat, 3 Jun 2017, Christoph Hellwig wrote:
> +
> +bool irq_affinity_set(int irq, struct irq_desc *desc, const cpumask_t *mask)
This should be named irq_affinity_force() because it circumvents the 'move
in irq context' mechanism. I'll do that myself. No need to resend.
Thanks,
tglx
On Fri, 2017-06-16 at 09:46 +0100, Marc Zyngier wrote:
> On 15/06/17 17:17, Jerome Brunet wrote:
> > This patch series adds support for the GPIO interrupt controller found on
> > Amlogic's meson SoC families.
> >
> > Unlike what the name suggests, this controller is not part of the SoC
> > GPIO su
On 06/16/2017 12:35 AM, David Daney wrote:
... this allows gating of inline assembly code that causes llvm to
fail when emitting BPF.
Signed-off-by: David Daney
I don't have a better idea at the moment, perhaps there could be
a clang rewrite plugin that would ignore all inline assembly code
s
Hi,
> I'm not sure I agree regarding the vgpu statement, maybe this is not
> dmabuf specific, but what makes it vgpu specific? We need to
> separate
> our current usage plans from what it's actually describing and I
> don't
> see that it describes anything vgpu specific.
Well, it describes a f
On Sat, 3 Jun 2017, Christoph Hellwig wrote:
> +static void irq_affinity_online_irq(unsigned int irq, struct irq_desc *desc,
> + unsigned int cpu)
> +{
> +
> + cpumask_and(mask, affinity, cpu_online_mask);
> + cpumask_set_cpu(cpu, mask);
> + if (irqd_has_
Michal Hocko wrote:
> On Fri 16-06-17 09:54:34, Tetsuo Handa wrote:
> [...]
> > And the patch you proposed is broken.
>
> Thanks for your testing!
>
> > --
> > [ 161.846202] Out of memory: Kill process 6331 (a.out) score 999 or
> > sacrifice child
> > [ 161.850327] Killed process 6331
After a recent upgrade of a Ubuntu xenial machine, a particular
autofs multi-map mount setup stopped working. A simplified example is:
::
auto.master
::
/net/etc/auto.net
::
auto.net
::
localhost / :/ /loc :/loc
Accessing /net/localhost/
On 06/16/2017 11:35 AM, Arvind Yadav wrote:
> of_device_ids are not supposed to change at runtime. All functions
> working with of_device_ids provided by work with const
> of_device_ids. So mark the non-const structs as const.
>
> Signed-off-by: Arvind Yadav
Works for me
Reviewed-by: Marek Vasu
On 16/06/17 11:02, Jerome Brunet wrote:
> On Fri, 2017-06-16 at 10:35 +0100, Marc Zyngier wrote:
>> + Heiner.
>>
>> On 15/06/17 17:18, Jerome Brunet wrote:
>>> Add support for the interrupt gpio controller found on Amlogic's meson
>>> SoC family.
>>>
>>> Unlike what the IP name suggest, it is not d
On Sat, 3 Jun 2017, Christoph Hellwig wrote:
> +static void irq_affinity_online_irq(unsigned int irq, struct irq_desc *desc,
> + unsigned int cpu)
> +{
> + const struct cpumask *affinity;
> + struct irq_data *data;
> + struct irq_chip *chip;
> + unsig
NeilBrown writes:
> On Thu, Jun 15 2017, Andrew Morton wrote:
>> On Wed, 07 Jun 2017 12:08:38 +1000 NeilBrown wrote:
>>> --- a/fs/autofs4/dev-ioctl.c
>>> +++ b/fs/autofs4/dev-ioctl.c
>>> @@ -344,7 +344,7 @@ static int autofs_dev_ioctl_fail(struct file *fp,
>>> int status;
>>>
>>> token
On Fri, 2017-06-16 at 14:50 +0530, Anshuman Khandual wrote:
> On 06/06/2017 06:35 AM, Ram Pai wrote:
> > The value of the AMR register at the time of the exception
> > is made available in gp_regs[PT_AMR] of the siginfo.
>
> But its already available there in uctxt->uc_mcontext.regs->amr
> while i
Rockchip's RK3328 evaluation board has one usb2 otg controller
and one usb2 host controller which consist of EHCI and OHCI.
Each usb controller connects with one usb2 phy port through
UTMI+ interface. Let's enable them to support usb2 on RK3328
evaluation board.
Signed-off-by: William Wu
---
Chan
This patch adds usb2 otg/host controllers and phys nodes
for Rockchip RK3328 SoCs.
Signed-off-by: William Wu
---
Changes in v2:
- set usb2 otg dr_mode as "otg"
arch/arm64/boot/dts/rockchip/rk3328.dtsi | 76
1 file changed, 76 insertions(+)
diff --git a/arch/arm
This series adds support for usb2 on RK3328 SoCs.
Tested on RK3328 evaluation board.
William Wu (2):
arm64: dts: rockchip: add usb2 nodes for RK3328 SoCs
arm64: dts: rockchip: enable usb2 for RK3328 evaluation board
arch/arm64/boot/dts/rockchip/rk3328-evb.dts | 25 ++
arch/arm64/boot
Stephen Rothwell writes:
> On Fri, 16 Jun 2017 11:13:35 +1000 Stephen Rothwell
> wrote:
>> On Fri, 16 Jun 2017 10:57:22 +1000 Michael Ellerman
>> wrote:
>> > "Rowand, Frank" writes:
>> > > On Thursday, June 15, 2017 2:25 AM, Abdul Haleem
>> > > [mailto:abdha...@linux.vnet.ibm.com] wrote:
This RFC suggest three changes from the migrate disable/enable
mechanism. Two of them are fixes, and the last one is a
suggestion/improvement.
As migrate_disable/enable is RT specific, this patch set is
RT specific.
Daniel Bristot de Oliveira (3):
rt: Increase/decrease the nr of migratable task
In the case of an affinity change during a migrate_disable section,
__set_cpus_allowed_ptr will not try to move the task from a CPU
in which it cannot execute anymore.
So, after enabling migration, if the current task cannot execute in
the current CPU anymore, migrate it away.
Signed-off-by: Dani
Currently, if the affinity of a task changes when it is with migration
disabled, the nr_cpus_allowed is not being updated, creating an
inconsistency between nr_cpus_allowed and cpumask_weight(cpus_allowed)
This patch fixes this problem by calling set_cpus_allowed_common()
if the cpumask of a task
There is a problem in the migrate_disable()/enable() implementation
regarding the number of migratable tasks in the rt/dl RQs. The problem
is the following:
When a task is attached to the rt runqueue, it is checked if it either
can run in more than one CPU, or if it is with migration disable. If
e
On 05/12/17 04:42, Minghsiu Tsai wrote:
> From: Daniel Kurtz
>
> Experiments show that the:
> (1) mtk-mdp uses the _MPLANE form of CAPTURE/OUTPUT
Please drop this, since this no longer applies to this patch.
> (2) CAPTURE types use CROP targets, and OUTPUT types use COMPOSE targets
Are you r
Good day dear, i hope this mail meets you well? my name is Jack, from the U.S.
I know this may seem inappropriate so i ask for your forgiveness but i wish to
get to know you better, if I may be so bold. I consider myself an easy-going
man, adventurous, honest and fun loving person but I am curre
;> now I cannot continue with debugging, but if nothing will get clear,
>>> I'll back to it at this evening.
>>
>> Sorry, forgot to attach the config. This is it. Also, I run arm64 on
>> qemu.
>
> The next-20170616 boots well for me. I didn't manage
Dear RT folks!
I'm pleased to announce the v4.11.5-rt1 patch set.
The release has been delayed due to the hotplug rework that was started
before the final v4.11 release. However the new code has not been
stabilized yet and it was decided to bring back the old patches before
delaying the v4.11-RT
On Wed, 14 Jun 2017, Tom Lendacky wrote:
> A recent change added a new system_state value, SYSTEM_SCHEDULING, which
> exposed a warning issued by early_ioreamp() when the system_state was not
> SYSTEM_BOOTING. Since early_ioremap() can be called when the system_state
> is SYSTEM_SCHEDULING, the che
On Fri 16-06-17 19:27:19, Tetsuo Handa wrote:
> Michal Hocko wrote:
> > On Fri 16-06-17 09:54:34, Tetsuo Handa wrote:
> > [...]
> > > And the patch you proposed is broken.
> >
> > Thanks for your testing!
> >
> > > --
> > > [ 161.846202] Out of memory: Kill process 6331 (a.out) score 99
On Sat, 3 Jun 2017, Christoph Hellwig wrote:
> +bool irq_affinity_set(int irq, struct irq_desc *desc, const cpumask_t *mask)
> +{
> + struct irq_data *data = irq_desc_get_irq_data(desc);
> + struct irq_chip *chip = irq_data_get_irq_chip(data);
> + bool ret = false;
> +
> + if (!irq_
Now that AVR32 is gone, we can use the proper IO accessors that are
correctly handling endianness.
Signed-off-by: Alexandre Belloni
---
drivers/clocksource/tcb_clksrc.c | 58
1 file changed, 29 insertions(+), 29 deletions(-)
diff --git a/drivers/clocksou
Ram Pai writes:
> diff --git a/arch/powerpc/include/uapi/asm/ptrace.h
> b/arch/powerpc/include/uapi/asm/ptrace.h
> index 8036b38..109d0c2 100644
> --- a/arch/powerpc/include/uapi/asm/ptrace.h
> +++ b/arch/powerpc/include/uapi/asm/ptrace.h
> @@ -49,6 +49,8 @@ struct pt_regs {
> unsigned long
Hi Mark,
thanks for the comments.
On Fri, Jun 9, 2017 at 8:53 PM, Mark Rutland wrote:
> On Mon, Jun 05, 2017 at 12:21:04PM +0530, Ganapatrao Kulkarni wrote:
>> This patch adds a perf driver for the PMU UNCORE devices DDR4 Memory
>> Controller(DMC) and Level 3 Cache(L3C).
>
> Can you elaborate a
On Fri, Jun 16, 2017 at 10:33 AM, Mika Westerberg
wrote:
> On Thu, Jun 15, 2017 at 06:01:02PM +, Gabriele Paoloni wrote:
>> Hi Mika
>>
>> > -Original Message-
>> > From: linux-pci-ow...@vger.kernel.org [mailto:linux-pci-
>> > ow...@vger.kernel.org] On Behalf Of Mika Westerberg
>> > Sen
CMA has gained a recent helper function for calculating the start
of a plane buffer's physical address. Use that instead of the
hand rolled version.
Cc: Brian Starkey
Signed-off-by: Liviu Dudau
---
drivers/gpu/drm/arm/malidp_planes.c | 12 +---
1 file changed, 5 insertions(+), 7 deletio
Expose and export the tegra_bpmp_mrq_return function for use of drivers
outside the core BPMP driver. This function is used to reply to
messages originating from the BPMP, which is required in the thermal
driver.
Signed-off-by: Mikko Perttunen
---
drivers/firmware/tegra/bpmp.c | 5 +++--
include
In Tegra186, the BPMP (Boot and Power Management Processor) implements
an interface that is used to read system temperatures, including CPU
cluster and GPU temperatures. This binding describes the thermal sensor
that is exposed by BPMP.
Signed-off-by: Mikko Perttunen
---
.../thermal/nvidia,tegra
This adds the thermal sensor device provided by the BPMP, and the
relevant thermal sensors to the Tegra186 device tree.
Signed-off-by: Mikko Perttunen
---
arch/arm64/boot/dts/nvidia/tegra186.dtsi | 48
1 file changed, 48 insertions(+)
diff --git a/arch/arm64/boo
On Tegra186, the BPMP (Boot and Power Management Processor) exposes an
interface to thermal sensors on the system-on-chip. This driver
implements access to the interface. It supports reading the
temperature, setting trip points and receiving notification of a
tripped trip point.
Signed-off-by: Mik
On Fri, Jun 16, 2017 at 10:16:30AM +0200, Ingo Molnar wrote:
>
> * kernel test robot wrote:
>
> > Greetings,
> >
> > 0day kernel testing robot got the below dmesg and the first bad commit is
> >
> > https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master
> >
> > commit c88d
commit 46ddd79e893b ("usb: gadget: udc: atmel: Remove AVR32 bits from the
driver") left the accessor macros introduced by commit a3dd3befd7cb ("usb:
gadget: atmel_usba: use endian agnostic IO on ARM"). They can now be
removed.
Signed-off-by: Alexandre Belloni
---
drivers/usb/gadget/udc/atmel_usb
"Kirill A. Shutemov" writes:
> This patch uses modifed pmdp_invalidate(), that return previous value of pmd,
> to transfer dirty and accessed bits.
>
> Signed-off-by: Kirill A. Shutemov
> ---
> fs/proc/task_mmu.c | 8
> mm/huge_memory.c | 29 -
> 2 files
CMA has gained a recent helper function for calculating the start
of the plane buffer's physical address. Use that instead of the
hand rolled version.
Signed-off-by: Liviu Dudau
---
drivers/gpu/drm/arm/hdlcd_crtc.c | 9 +
1 file changed, 1 insertion(+), 8 deletions(-)
diff --git a/drive
This commit applies commit 388f9b20f98d ("Documentation/process/howto:
Only send regression fixes after -rc1") to Korean translation.
Signed-off-by: SeongJae Park
---
Documentation/translations/ko_KR/howto.rst | 18 ++
1 file changed, 10 insertions(+), 8 deletions(-)
diff --git
On Thu, Jun 15, 2017 at 9:02 AM, Dmitry Vyukov wrote:
> On Wed, Jun 14, 2017 at 11:15 PM, Arnd Bergmann wrote:
>> diff --git a/lib/Kconfig.kmemcheck b/lib/Kconfig.kmemcheck
>> index 846e039a86b4..58b9f3f81dc8 100644
>> --- a/lib/Kconfig.kmemcheck
>> +++ b/lib/Kconfig.kmemcheck
>> @@ -7,6 +7,7 @@
On Thu, 2017-06-15 at 17:54 +0200, Matthias Brugger wrote:
> Commit e4fda3a04275 ("serial: don't register CIR serial ports") adds a
> check for PORT_8250_CIR to serial8250_register_8250_port(). But the
> code
> isn't needed as the function never takes the branch when the port is
> CIR
> serial port
JFYI I will repost sometimes next week unless there is another feedback
by then.
--
Michal Hocko
SUSE Labs
101 - 200 of 798 matches
Mail list logo
