Hi,
On Wed, May 24, 2017 at 08:13:18PM +0800, Icenowy Zheng wrote:
> As we have already the support for the PWM controller on V3s SoC, add
> its device node in the SoC's DTSI file.
>
> Signed-off-by: Icenowy Zheng
> ---
> arch/arm/boot/dts/sun8i-v3s.dtsi | 8
> 1 file changed, 8 insert
Hi,
On Wed, May 24, 2017 at 08:13:19PM +0800, Icenowy Zheng wrote:
> Allwinner V3s have two PWM channels, the first channel can be only at
> PB4 pin, and the second channel PB5.
>
> Add their pinmux configurations.
>
> Signed-off-by: Icenowy Zheng
> ---
> arch/arm/boot/dts/sun8i-v3s.dtsi | 10
> +struct vfio_vgpu_dmabuf_info {
> + __u32 argsz;
> + __u32 flags;
> + struct vfio_vgpu_plane_info plane_info;
> + __s32 fd;
> + __u32 pad;
> +};
Hmm, now you have argsz and flags twice in vfio_vgpu_dmabuf_info ...
I think we should have something like this:
struct vfio_vgpu
The ZTE SoC drivers are only useful when building for a ZTE ZX platform.
Fixes: 4c2c2e39713b8cfb ("soc: zte: pm_domains: Prepare for supporting ARMv8
zx2967 family")
Signed-off-by: Geert Uytterhoeven
Reviewed-by: Baoyou Xie
---
v2:
- Add Reviewed-by.
---
drivers/soc/zte/Kconfig | 1 +
1 file
From: Rabin Vincent
There currently appears to be no way for userspace to find out the
underlying volume number for a mounted ubifs file system, since ubifs
uses anonymous block devices. The volume name is present in
/proc/mounts but UBI volumes can be renamed after the volume has been
mounted.
This fixes a regression in commit 4d6501dce079 where I didn't notice
that MIPS and OpenRISC were reinitialising p->{set,clear}_child_tid to
NULL after our initialisation in copy_process().
We can simply get rid of the arch-specific initialisation here since it
is now always done in copy_process()
Hi everyone,
On Thu, Apr 27, 2017 at 4:35 AM, Jacek Anaszewski
wrote:
> On 04/26/2017 04:54 AM, Alexandre Courbot wrote:
>> On Wed, Apr 26, 2017 at 4:15 AM, Jacek Anaszewski
>> wrote:
>>> Hi Alexandre,
>>>
>>> Thanks for the patch.
>>>
>>> On 04/25/2017 08:19 AM, Alexandre Courbot wrote:
v4
Hi,
On Sat, May 27, 2017 at 06:23:06PM +0800, Icenowy Zheng wrote:
> Allwinner R40 SoC have a clock controller module in the style of the
> SoCs beyond sun6i, however, it's more rich and complex.
>
> Add support for it.
>
> Signed-off-by: Icenowy Zheng
> ---
> Changes in v3:
> - Rebased on curr
Hi,
On Wed, May 24, 2017 at 08:13:20PM +0800, Icenowy Zheng wrote:
> The 40-pin LCD connector on Lichee Pi Zero has backlight pins, which is
> controlled by the PWM0 controller of the V3s SoC, and the controlling
> part is on the board.
>
> Add the PWM and backlight device nodes in the device tre
clk_prepare_enable() can fail here and we must check its return value.
Signed-off-by: Arvind Yadav
---
drivers/iio/adc/aspeed_adc.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/iio/adc/aspeed_adc.c b/drivers/iio/adc/aspeed_adc.c
index 62670cb..e0ea411 100644
-
On Sat, May 27, 2017 at 02:19:51PM +0300, Alexey Budankov wrote:
> Solution:
>
> cpu indexed trees for perf_event_context::pinned_groups and
> perf_event_context::flexible_groups lists are introduced. Every tree node
> keeps a list of groups allocated for the same cpu. A tree references only
> gro
On 29/05/2017 08:05, Andrew Jeffery wrote:
> On Fri, 2017-05-26 at 10:48 +0200, Daniel Lezcano wrote:
>> The recent changes made the fttmr010 to be more generic and support different
>> timers with a very few differences like moxart or aspeed.
>>
>> The aspeed timer uses a countdown and there is a
On Sat, May 27, 2017 at 02:19:51PM +0300, Alexey Budankov wrote:
> @@ -571,6 +587,27 @@ struct perf_event {
>* either sufficies for read.
>*/
> struct list_headgroup_entry;
> + /*
> + * Node on the pinned or flexible tree located at the event context;
Hi Linus,
here is an overdue pull request for pin control fixes, the most
prominent feature is to make Intel Chromebooks (and I suspect any
other Cherryview-based Intel thing) happy again, which we really
want to see.
There is a patch hitting drivers/firmware/* that I was uncertain to
who actuall
On Tue, 16 May 2017 12:11:39 +0200
Ralph Sennhauser wrote:
> The source files namei.c and copy_up.c in overlayfs new use
> exportfs_decode_fh which depends on CONFIG_EXPORTFS being set. Select
> it in Kconfig.
This issue is still present in 4.12-rc3
Ralph
>> - Thinking further on this, I realized that for common case signal
>> polarity is something defined by chip, and thus this knowledge belongs
>> to chip's driver and not to chip user's device tree. Moreover, device
>> tree writer could easily be not aware of signal polarity (too many
>> datasheet
Hi Cosar,
Thank you for the patch
On 22/05/17 16:34, Cosar Dindar wrote:
> This patch adds CRC (CRC32 Crypto) support for STM32F4 series.
>
> As an hardware limitation polynomial and key setting are not supported.
> They are fixed as 0x4C11DB7 (poly) and 0x (key).
> CRC32C Castagnoli algo
Le 25/05/2017 à 18:45, kbuild test robot a écrit :
Hi Balbir,
[auto build test ERROR on powerpc/next]
[also build test ERROR on v4.12-rc2 next-20170525]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day-ci/linu
On Fri, May 19, 2017 at 6:04 PM, Gregory CLEMENT
wrote:
> Document the device tree binding for the pin controllers found on the
> Armada 7K and Armada 8K SoCs.
>
> Signed-off-by: Gregory CLEMENT
This patch does not apply on my pinctrl "devel" branch.
And I have no other patches to Marvell docs
On 27/05/2017 11:58, Daniel Lezcano wrote:
> The CLOCKSOUCE_OF_DECLARE macro is used widely
"CLOCKSOURCE" is misspelled ;-)
Regards.
On 03/05/17 13:05, Benoît Thébaudeau wrote:
> The eSDHC can only DMA from 32-bit-aligned addresses.
>
> This fixes the following test cases of mmc_test:
> 11: Badly aligned write
> 12: Badly aligned read
> 13: Badly aligned multi-block write
> 14: Badly aligned multi-block read
>
> Signed
On 03/05/17 13:05, Benoît Thébaudeau wrote:
> On i.MX25, the eSDHC DAT line software reset (SYSCTL.RSTD) unexpectedly
> clears at least the data transfer width (PROCTL.DTW), which then results
> in data CRC errors. This behavior is not documented, but it has actually
> been observed. Consequently,
On Tue, May 23, 2017 at 3:06 PM, Gregory CLEMENT
wrote:
> On mar., mai 23 2017, Linus Walleij wrote:
>> Please rebase and resend the rest of the patches.
>
> Actually I was wrong with my assumption that there was no dependency.
> For the binding documentation there is dependecy accross the seri
On 03/05/17 13:05, Benoît Thébaudeau wrote:
> On i.MX, SYSCTL.SDCLKFS may always be set to 0 in order to make the SD
> clock frequency prescaler divide by 1 in SDR mode, even with the eSDHC.
> The previous minimum prescaler value of 2 in SDR mode with the eSDHC was
> a code remnant from PowerPC, wh
Add nodes for the SPICC controller on GX common dtsi, GXBB and
GXL dtsi files.
Signed-off-by: Neil Armstrong
---
arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 9 +
arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 7 +++
arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 7 +++
3 files ch
On Wed, May 24, 2017 at 4:32 PM, Gregory CLEMENT
wrote:
> Since the commit "gpio: mvebu: switch to regmap for register access" the
> driver use the regmap. Explicitly select the REGMAP_MMIO symbol to fix
> build error.
>
> Reported-by: kbuild test robot
> Signed-off-by: Gregory CLEMENT
Patch a
On Mon, May 29, 2017 at 7:39 AM, Stephen Rothwell wrote:
> After merging the gpio tree, today's linux-next build (arm
> orion5x_defconfig) failed like this:
>
> drivers/gpio/gpio-mvebu.c:1062: undefined reference to
> `__devm_regmap_init_mmio_clk'
> drivers/gpio/gpio-mvebu.c:1078: undefined refe
On 03/05/17 13:05, Benoît Thébaudeau wrote:
> The SDHCI_QUIRK_NO_MULTIBLOCK quirk was used as a workaround for the
> ENGcm07207 erratum. However, it caused excruciatingly slow SD transfers
> (300 kB/s on average), and this erratum actually does not imply that
> multiple-block transfers are not supp
On Mon, May 22, 2017 at 2:59 PM, Neil Armstrong wrote:
> The SPICC controller has dedicated SPI pins, this patchs add the pins
> definition in the GXL pinctrl driver.
>
> Signed-off-by: Neil Armstrong
Patch applied.
Yours,
Linus Walleij
On Mon, May 22, 2017 at 2:59 PM, Neil Armstrong wrote:
> The SPICC controller has dedicated SPI pins, this patchs add the pins
> definition in the GXBB pinctrl driver
>
> Signed-off-by: Neil Armstrong
Patch applied.
Yours,
Linus Walleij
Hi,
On Sat, May 27, 2017 at 6:23 PM, Icenowy Zheng wrote:
> From: Chen-Yu Tsai
>
> The Allwinner R40 SoC is marketed as the successor to the A20 SoC.
> The R40 is a smaller chip than the A20, but features the same set
> of programmable pins, with a couple extra pins and some new pin
> functions.
Witam,
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maksymalnej wysokosci 3% w skali roku? Skontaktuj sie z nami po wiecej
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Dziekuje.
BSN Capital Partners Ltd (London)
Zarzadzanie.
--
Angielska wersja
On Mon, May 29, 2017 at 3:41 PM, Maxime Ripard
wrote:
> Hi,
>
> On Wed, May 24, 2017 at 08:13:20PM +0800, Icenowy Zheng wrote:
>> The 40-pin LCD connector on Lichee Pi Zero has backlight pins, which is
>> controlled by the PWM0 controller of the V3s SoC, and the controlling
>> part is on the board
Hi Jagan,
On Tue, May 23, 2017 at 06:30:37PM +0530, Jagan Teki wrote:
> From: Jagan Teki
>
> Add support for Olimex A13-512-SOM board, and this particular
> design is like A13-SOM-WIFI can mount on-top of A13-SOM.
>
> https://www.olimex.com/Products/SOM/A13/A13-SOM-512/
> https://www.olimex.com
On Sat, May 20, 2017 at 6:02 PM, Masahiro Yamada
wrote:
> Use of_device_get_match_data() instead of of_match_device().
> It allows us to remove the forward declaration of pcs_of_match.
>
> Signed-off-by: Masahiro Yamada
Patch applied with Tony's ACK.
Yours,
Linus Walleij
Commit-ID: dac6ca243c4c49a9ca7507d3d66140ebfac8b04b
Gitweb: http://git.kernel.org/tip/dac6ca243c4c49a9ca7507d3d66140ebfac8b04b
Author: Borislav Petkov
AuthorDate: Sun, 28 May 2017 22:04:14 +0200
Committer: Ingo Molnar
CommitDate: Mon, 29 May 2017 08:22:48 +0200
x86/microcode/AMD: Chang
Commit-ID: 5d9070b1f0fc9a159a9a3240c43004828408444b
Gitweb: http://git.kernel.org/tip/5d9070b1f0fc9a159a9a3240c43004828408444b
Author: Borislav Petkov
AuthorDate: Sun, 28 May 2017 11:03:42 +0200
Committer: Ingo Molnar
CommitDate: Mon, 29 May 2017 08:22:49 +0200
x86/debug/32: Convert a
On Mon, May 22, 2017 at 8:41 PM, Andy Shevchenko
wrote:
> On Mon, 2017-04-03 at 07:23 +0800, kbuild test robot wrote:
>> tree: https://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git
>> x86/platform
>> head: d4d969909bef4c1e103eec0fc2c820773811fb72
>> commit: d4d969909bef4c1e103eec0fc2c820
Many users of kernel async. crypto services have a pattern of
starting an async. crypto op and than using a completion
to wait for it to end, resulting of the same code repeating
itself in multiple places, sometime with coding errors.
This patch aims to introduce a generic "wait for async.
crypto
Invoking a possibly async. crypto op and waiting for completion
while correctly handling backlog processing is a common task
in the crypto API implementation and outside users of it.
This patch adds a generic implementation for doing so in
preparation for using it across the board instead of hand
DRBG is starting an async. crypto op and waiting for it complete.
Move it over to generic code doing the same.
The code now also passes CRYPTO_TFM_REQ_MAY_SLEEP flag indicating
crypto request memory allocation may use GFP_KERNEL which should
be perfectly fine as the code is obviously sleeping for
algif starts several async crypto ops and waits for their completion.
Move it over to generic code doing the same.
Signed-off-by: Gilad Ben-Yossef
---
crypto/af_alg.c | 27 ---
crypto/algif_aead.c | 14 +++---
crypto/algif_hash.c | 29 +
public_key_verify_signature() is starting an async crypto op and
waiting for it to complete. Move it over to generic code doing
the same.
Signed-off-by: Gilad Ben-Yossef
---
crypto/asymmetric_keys/public_key.c | 28
1 file changed, 4 insertions(+), 24 deletions(-)
d
ima starts several async crypto ops and waits for their completions.
Move it over to generic code doing the same.
Signed-off-by: Gilad Ben-Yossef
Acked-by: Mimi Zohar
---
security/integrity/ima/ima_crypto.c | 56 +++--
1 file changed, 17 insertions(+), 39 deleti
On Mon, May 22, 2017 at 10:56 PM, Paul Gortmaker
wrote:
> Fixups here tend to be more all over the map vs. some of the other
> repeated/systematic ones we've seen elsewhere.
>
> We remove module.h from code that isn't doing anything modular at
> all; if they have __init sections, then replace it
cifs starts an async. crypto op and waits for their completion.
Move it over to generic code doing the same.
Signed-off-by: Gilad Ben-Yossef
Acked-by: Pavel Shilovsky
---
fs/cifs/smb2ops.c | 30 --
1 file changed, 4 insertions(+), 26 deletions(-)
diff --git a/fs/cif
testmgr is starting async. crypto ops and waiting for them to complete.
Move it over to generic code doing the same.
This also provides a test of the generic crypto async. wait code.
Signed-off-by: Gilad Ben-Yossef
---
crypto/testmgr.c | 184 +
dm-verity is starting async. crypto ops and waiting for them to complete.
Move it over to generic code doing the same.
This also fixes a possible data coruption bug created by the
use of wait_for_completion_interruptible() without dealing
correctly with an interrupt aborting the wait prior to the
fscrypt starts several async. crypto ops and waiting for them to
complete. Move it over to generic code doing the same.
Signed-off-by: Gilad Ben-Yossef
---
fs/crypto/crypto.c | 28
fs/crypto/fname.c | 36 ++--
fs/cry
The code sample is waiting for an async. crypto op completion.
Adapt sample to use the new generic infrastructure to do the same.
This also fixes a possible data coruption bug created by the
use of wait_for_completion_interruptible() without dealing
correctly with an interrupt aborting the wait pr
On Mon, May 22, 2017 at 10:56 PM, Paul Gortmaker
wrote:
> None of the Kconfigs for any of these drivers are tristate,
> meaning that they currently are not being built as a module by anyone.
>
> Lets remove the modular code that is essentially orphaned, so that
> when reading the drivers there is
gcm is starting an async. crypto op and waiting for it complete.
Move it over to generic code doing the same.
Signed-off-by: Gilad Ben-Yossef
---
crypto/gcm.c | 32 ++--
1 file changed, 6 insertions(+), 26 deletions(-)
diff --git a/crypto/gcm.c b/crypto/gcm.c
index 3
On Mon, May 22, 2017 at 10:56 PM, Paul Gortmaker
wrote:
> Fixups here tend to be more of a conglomerate of some of the other
> repeated/systematic ones we've seen in the earlier pinctrl cleanups.
>
> We remove module.h from code that isn't doing anything modular at
> all; if they have __init sec
On Mon, May 22, 2017 at 10:56 PM, Paul Gortmaker
wrote:
> This is the last of the pinctrl cleanups I have in my queue.
Awesome.
> Linus - thanks for your patience in merging all these to date.
You are the patient one. I'm just merging...
I was sold on the technical merit if these patches once
On Tue, May 23, 2017 at 11:18 AM, Arvind Yadav
wrote:
> clk_prepare_enable() can fail here and we must check its return value.
>
> Signed-off-by: Arvind Yadav
Patch applied.
Normally we use goto's for the errorpath but in this case I see the
goto is used for positive exit in this driver so thi
On Sat, May 27, 2017 at 12:58:14PM -0700, Kees Cook wrote:
> FAST_REFCOUNT=n: use function-based refcount_t with cmpxvhg and
> full-verification
> FAST_REFCOUNT=y without arch-specific implementation: use atomic_t
> with no verification (i.e. no functional change from now)
> FAST_REFCOUNT=y with ar
Hello!
Why "soc_camera:" in the subject?
The 'soc_camera" driver has been removed (replaced by a "normal" V4L2
driver).
MBR, Sergei
Hyunchul,
Am 29.05.2017 um 04:24 schrieb Hyunchul Lee:
>>> This is just broken. First ubifs should still properly propagate
>>> the errors, and second freezing/unfreezing read only file systems is
>>> perfectly valid,
>>
>> it is right.
>
> if updating TNC is failed, ubifs might become inconsis
On Tue, May 23, 2017 at 8:37 PM, jmondi wrote:
>> I did not follow too much.
>> But it seems IMX7ULP/Vybrid to be also a fan of generic
>> output-enable/input-enable
>> property.
>>
>> See:
>> Figure 5-2. GPIO PAD in Page 241
>> http://www.nxp.com/assets/documents/data/en/reference-manuals/VFXXXR
Hi,
On Thu, 25 May 2017 23:33:43 +
Darwin Dingel wrote:
> Hi,
>
> We are also having the same problem where the IFC (nand flash) was
> reporting ECC uncorrectable errors on single bitflips with erased pages.
> Applying this patch with some minor modifications seems to solve our
> issue.
On Fri 26-05-17 14:25:09, Heiko Carstens wrote:
> On Wed, May 24, 2017 at 10:39:57AM +0200, Michal Hocko wrote:
> > On Wed 24-05-17 10:20:22, Heiko Carstens wrote:
> > > Having the ZONE_MOVABLE default was actually the only point why s390's
> > > arch_add_memory() was rather complex compared to oth
On Tue, May 23, 2017 at 4:09 PM, Neil Armstrong wrote:
> GPIODV_18 entry was missing in the original driver push.
>
> Fixes: 0f15f500ff2c ("pinctrl: meson: Add GXL pinctrl definitions")
> Signed-off-by: Neil Armstrong
Patch applied with Jerome's review tag.
Yours,
Linus Walleij
On Tue, May 23, 2017 at 4:09 PM, Neil Armstrong wrote:
> GPIODV_18 entry was missing in the original driver push.
>
> Fixes: 468c234f9ed7 ("pinctrl: amlogic: Add support for Amlogic Meson GXBB
> SoC")
> Signed-off-by: Neil Armstrong
Patch applied with Jerome's review tag.
Yours,
Linus Walleij
On Wed, May 24, 2017 at 10:20 AM, Neil Armstrong
wrote:
> The AO I2S pins were incorrectly defined with the EE pin offset.
>
> Cc: Jerome Brunet
> Fixes: 2899adf0422 ("pinctrl: meson: gxl: add i2s output pins")
> Signed-off-by: Neil Armstrong
Patch applied with Jerome's review tag.
Yours,
Lin
On Wed, May 24, 2017 at 10:20 AM, Neil Armstrong
wrote:
> The AO SPDIF pins were incorrectly defined with the EE pin offset.
>
> Cc: Jerome Brunet
> Fixes: b840d649f9ec ("pinctrl: meson: gxl: add spdif output pins")
> Signed-off-by: Neil Armstrong
Patch applied with Jerome's review tag.
Yours
On Sat, May 27, 2017 at 6:23 PM, Icenowy Zheng wrote:
> From: Chen-Yu Tsai
>
> The Banana Pi M2 Ultra is an SBC based on the Allwinner R40 SoC. The
> form factor and position of various connectors, leds and buttons is
> similar to the Banana Pi M1+, Banana Pi M3, and is exactly the same
> as the
On Wed, May 24, 2017 at 10:20 AM, Neil Armstrong
wrote:
> Add the AO and EE domain CEC pins for the Amlogic Meson GXBB SoCs.
>
> Signed-off-by: Neil Armstrong
Patch applied with Jerome's review tag.
Yours,
Linus Walleij
On Thu, May 25, 2017 at 10:28:24PM +0800, Icenowy Zheng wrote:
> + compatible = "allwinner,sun8i-v3s-de2-mixer";
> + reg = <0x0110 0x10>;
> >>>
> >>>The display engine also has an interrupt. Please list it
> >>
> >> It's a overall interr
On 23.3.2017 14:16, Geliang Tang wrote:
> Use sg_phys() instead of open-coding it.
>
> Signed-off-by: Geliang Tang
> ---
> arch/microblaze/kernel/dma.c | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/arch/microblaze/kernel/dma.c b/arch/microblaze/kernel/dma.c
> index
On Wed, May 24, 2017 at 10:20 AM, Neil Armstrong
wrote:
> Add the AO and EE domain CEC pins for the Amlogic Meson GXL SoCs.
>
> Signed-off-by: Neil Armstrong
Patch applied with Jerome's review tag.
Yours,
Linus Walleij
Amir, Hyunchul,
Am 29.05.2017 um 07:40 schrieb Amir Goldstein:
> On Mon, May 29, 2017 at 7:40 AM, Hyunchul Lee wrote:
>>
>> and I missed the following case.
>>
>> in some embedded systems, clean-up for shutdown should be fast.
>> during this clean-up, freeze file system to guarantee integrity.
>>
On Wed, May 24, 2017 at 10:20 AM, Neil Armstrong
wrote:
> The Amlogic Meson GXL SoCs embeds an 10/100 Ethernet PHY, this patchs enables
> the Link and Activity LEDs signals.
>
> Signed-off-by: Neil Armstrong
Patch applied with Jerome's review tag.
Yours,
Linus Walleij
On 30.3.2017 21:45, Nicolai Stange wrote:
> In preparation for making the clockevents core NTP correction aware,
> all clockevent device drivers must set ->min_delta_ticks and
> ->max_delta_ticks rather than ->min_delta_ns and ->max_delta_ns: a
> clockevent device's rate is going to change dynamica
On 19.5.2017 13:43, Tobias Klauser wrote:
> Add the new statx syscall.
>
> Signed-off-by: Tobias Klauser
> ---
> arch/microblaze/include/asm/unistd.h | 2 +-
> arch/microblaze/include/uapi/asm/unistd.h | 1 +
> arch/microblaze/kernel/syscall_table.S| 1 +
> 3 files changed, 3 insertions
Hi Matias,
On Mon, May 15, 2017 at 06:31:58AM +, Javier Gonzalez wrote:
> >
> > On 13 May 2017, at 21.50, Rakesh Pandit wrote:
> >
> > While creating new device with NVM_DEV_CREATE if LUNs are already
> > allocated ioctl would return -ENOMEM which is wrong. This patch
> > propagates -EBUSY
Hi Joel,
On Fri, 2017-05-26 at 13:32 +1000, Joel Stanley wrote:
> This adds the bindings documentation for a basic single-register reset
> controller.
>
> The bindings describe a single 32-bit register that contains up to 32
> reset lines, each deasserted by clearing the appropriate bit in the
>
+++ Xie XiuQi [20/05/17 15:46 +0800]:
From: Wanlong Gao
Module name has a limited length, but currently the build system
allows the build finishing even if the module name is too long.
CC
/root/kprobe_example/abcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyz
The suspend/resume behavior of the TPM can be controlled by setting
"powered-while-suspended" in the DTS. This is useful for the cases
when hardware does not power-off the TPM.
Signed-off-by: Sonny Rao
Signed-off-by: Enric Balletbo i Serra
Reviewed-by: Jason Gunthorpe
Reviewed-by: Jarkko Sakkin
Add a new powered-while-suspended property to control the behavior of the
TPM suspend/resume.
Signed-off-by: Enric Balletbo i Serra
Signed-off-by: Sonny Rao
Reviewed-by: Jason Gunthorpe
Reviewed-by: Jarkko Sakkinen
Acked-by: Rob Herring
---
Changes since v3.
- Rebased on top of linux-next
On Fri, May 5, 2017 at 4:47 PM, wrote:
> From: Sunil Goutham
>
> Processing queue full of TLB invalidation commands might
> take more time on some platforms than current timeout
> of 100us. So increased drain timeout value.
>
> Also now udelay time is increased exponentially for each poll.
>
> S
Add device tree description info for Cortina 10G phy devices.
Signed-off-by: Bogdan Purcareata
---
v3 -> v4:
- Consistency nit between phy label and reg value.
- Add CORTINNA trademark info.
Patch introduced in v3 of the patchset.
Documentation/devicetree/bindings/net/cortina.txt | 21
Add basic support for Cortina PHY drivers. Support only CS4340 for now.
The phys are not compatible with IEEE 802.3 clause 22/45 registers.
Implement proper read_status support. The generic 10G phy driver causes
bus register access errors.
The driver should be described using the "ethernet-phy-id
So far, the Cortina family phys (CS4340 in this particular case) are only
supported in fixed link mode (via fixed_phy_register). The generic 10G
phy driver does not work well with the phylib state machine, when the phy
is registered via of_phy_connect. This prohibits the user from describing the
ph
On Sun, May 28, 2017 at 11:30 AM, Wolfram Sang
wrote:
> It is 'R-Car', not 'RCar'. No code or binding changes, only descriptive text.
>
> Signed-off-by: Wolfram Sang
Acked-by: Geert Uytterhoeven
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux b
On Sun, May 28, 2017 at 11:30 AM, Wolfram Sang
wrote:
> It is 'R-Car', not 'r-car'. No code or binding changes, only descriptive text.
>
> Signed-off-by: Wolfram Sang
Acked-by: Geert Uytterhoeven
> --- a/Documentation/devicetree/bindings/dma/shdma.txt
> +++ b/Documentation/devicetree/bindings/
On Sun, May 28, 2017 at 11:30 AM, Wolfram Sang
wrote:
> It is 'R-Car', not 'RCar'. No code or binding changes, only descriptive text.
>
> Signed-off-by: Wolfram Sang
Acked-by: Geert Uytterhoeven
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux b
On Thu, May 25, 2017 at 10:55:47PM -0700, Alexei Starovoitov wrote:
> +++ b/kernel/bpf/arraymap.c
> @@ -462,26 +462,22 @@ static void *perf_event_fd_array_get_ptr(struct bpf_map
> *map,
>
> event = perf_file->private_data;
> ee = ERR_PTR(-EINVAL);
> + /* Per-task events are not
On Sun, May 28, 2017 at 11:30 AM, Wolfram Sang
wrote:
> It is 'R-Car', not 'RCar'. No code or binding changes, only descriptive text.
>
> Signed-off-by: Wolfram Sang
Acked-by: Geert Uytterhoeven
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux b
On Thu, 25 May 2017 11:49:13 +1200
Chris Packham wrote:
> Use mtd_device_register() instead of mtd_device_parse_register() to
> eliminate two unused parameters.
>
> Signed-off-by: Chris Packham
> Reviewed-by: Andrew Lunn
> Tested-by: Andrew Lunn
Acked-by: Boris Brezillon
> ---
> Changes in
On Sun, May 28, 2017 at 11:30 AM, Wolfram Sang
wrote:
> It is 'R-Car', not 'RCar'. No code or binding changes, only descriptive text.
>
> Signed-off-by: Wolfram Sang
Acked-by: Geert Uytterhoeven
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux b
On Thu, 25 May 2017 11:49:12 +1200
Chris Packham wrote:
> This allows registering of this device via a Device Tree.
>
> Signed-off-by: Chris Packham
> Reviewed-by: Andrew Lunn
> Tested-by: Andrew Lunn
Acked-by: Boris Brezillon
> ---
> Changes in v2:
> - collect review/test from Andrew
> Ch
On Thu, 25 May 2017 11:49:14 +1200
Chris Packham wrote:
> erasesize is meaningful for flash devices but for SRAM there is no
> concept of an erase block so erasesize is set to 0. When partitioning
> these devices instead of ensuring partitions fall on erasesize
> boundaries we ensure they fall on
When registering for the Xenstore watch of the node control/sysrq the
handler will be called at once. Don't issue an error message if the
Xenstore node isn't there, as it will be created only when an event
is being triggered.
Signed-off-by: Juergen Gross
---
drivers/xen/manage.c | 7 +--
1 f
On Thu, 25 May 2017 11:49:15 +1200
Chris Packham wrote:
> Setting the of_node for the mtd device allows the generic mtd code to
> setup the partitions. Additionally we must specify a non-zero erasesize
> for the partitions to be writeable.
>
> Signed-off-by: Chris Packham
> Reviewed-by: Andrew
On Sun, May 28, 2017 at 11:30 AM, Wolfram Sang
wrote:
> It is 'R-Car', not 'RCar'. No code or binding changes, only descriptive text.
>
> Signed-off-by: Wolfram Sang
Acked-by: Geert Uytterhoeven
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux b
On 29.05.2017 10:46, Peter Zijlstra wrote:
On Sat, May 27, 2017 at 02:19:51PM +0300, Alexey Budankov wrote:
@@ -571,6 +587,27 @@ struct perf_event {
* either sufficies for read.
*/
struct list_headgroup_entry;
+ /*
+* Node on the pinned or
On Sun, May 28, 2017 at 11:30 AM, Wolfram Sang
wrote:
> It is 'R-Car', not 'RCar'. No code or binding changes, only descriptive text.
>
> Signed-off-by: Wolfram Sang
Acked-by: Geert Uytterhoeven
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux b
On Tue, May 23, 2017 at 7:03 PM, Andy Shevchenko
wrote:
> This is preparatory patch for enabling GPIO ACPI to configure a pin
> accordingly.
>
> Signed-off-by: Andy Shevchenko
> Tested-by: Jarkko Nikula
> Reviewed-by: Mika Westerberg
Patch applied.
Yours,
Linus Walleij
On Thu, 25 May 2017 11:49:16 +1200
Chris Packham wrote:
> The mchp23lcv1024 is similar to the mchp23k256, the differences (from a
> software point of view) are the capacity of the chip and the size of the
> addresses used.
>
> There is no way to detect the specific chip so we must be told via a
On Tue, May 23, 2017 at 7:03 PM, Andy Shevchenko
wrote:
> By some reason acpi_find_gpio() and acpi_gpio_count() have compared
> connection ID to "gpios" when tries to check if suffix is needed or not.
>
> Don't do any assumptions about what connection ID can be and, when defined,
> use it only wi
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