This adds support usb2-phy for rk322x SoCs and amend phy Documentation.
Signed-off-by: Frank Wang
---
.../bindings/phy/phy-rockchip-inno-usb2.txt| 1 +
drivers/phy/phy-rockchip-inno-usb2.c | 60 ++
2 files changed, 61 insertions(+)
diff --git a/Documen
From: William Wu
When resume phy, it need about 1.5 ~ 2ms to wait for
utmi_clk which used for USB controller to become stable.
Signed-off-by: William Wu
Signed-off-by: Frank Wang
---
drivers/phy/phy-rockchip-inno-usb2.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/phy/phy-ro
From: William Wu
At the current rockchip-inno-usb2 phy driver framework, it can
only support usb2-phy which comprises with one otg-port and one
host-port.
However, some Rockchip SoCs' (e.g RK3228, RK3229) usb2-phy comprises
with two host-ports, so we use index of otg id for one host-port
configu
From: William Wu
In rockchip-inno-usb2 phy driver, we use otg_sm_work to
dynamically manage power consumption for phy otg-port.
If the otg-port works as peripheral mode and does not
communicate with usb host, we will suspend phy.
But once suspend phy, the phy no longer has any internal
clock run
On Wed, May 17, 2017 at 10:08:45PM -0400, Steven Rostedt wrote:
>
> From: "Steven Rostedt (VMware)"
>
> As stack tracing now requires "rcu watching", force RCU to be watching when
> recording a stack trace.
>
> Link: http://lkml.kernel.org/r/20170512172449.879684...@goodmis.org
>
> Cc: "Paul E
Hi,
Sorry, I forgot to declare that this change required below patch on
patchwork.
https://patchwork.kernel.org/patch/9703945/
BR.
Frank
On 2017/5/18 11:18, kbuild test robot wrote:
Hi Frank,
[auto build test ERROR on rockchip/for-next]
[also build test ERROR on v4.12-rc1 next-20170517
On Wed, May 17, 2017 at 07:55:20AM -0700, Paul E. McKenney wrote:
> On Wed, May 17, 2017 at 12:40:10PM +0200, Peter Zijlstra wrote:
> > On Tue, May 16, 2017 at 07:27:42AM -0700, Paul E. McKenney wrote:
> > > On Tue, May 16, 2017 at 05:46:06AM -0700, Paul E. McKenney wrote:
[ . . . ]
> >
> > With
The A83T clock control unit is a hybrid of some new style clock designs
from the A80, and old style layout from the other Allwinner SoCs.
Like the A80, the SoC does not have a low speed 32.768 kHz oscillator.
Unlike the A80, there is no clock input either. The only low speed clock
available is the
The datasheets for Allwinner SoCs set strict requirements on the
stability of the external crystal oscillators. Add the accuracy
for the main 24MHz oscillator to the device tree.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a
Now that the CCU device tree binding headers have been merged, we can
use the properly named macros in the device tree, instead of raw
numbers.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/arch/arm/
Hi everyone,
This is v3 of my A83T CCU series. This is for 4.13.
Changes since v2:
- Dropped patches "clk: Provide option to query hardware for clk phase"
and "clk: sunxi-ng: Add class of phase clocks supporting MMC new timing
modes".
- Dropped support for MMC new timing mode. T
Now that we have support for the A83T CCU, add a device node for it,
and replace any existing placeholder clock phandles with the correct
ones.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 15 +--
1 file changed, 13 insertions(+), 2 deletions(-)
diff --git a/a
The A83T clock control unit is a hybrid of some new style clock designs
from the A80, and old style layout from the other Allwinner SoCs.
Like the A80, the SoC does not have a low speed 32.768 kHz oscillator.
Unlike the A80, there is no clock input either. The only low speed clock
available is the
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