Use a managed backlight device to get rid of acpi_fujitsu_bl_remove().
Change the parent of the backlight device from NULL to the FUJ02B1 ACPI
device as the latter is required for the backlight device to work.
Signed-off-by: Michał Kępień
---
drivers/platform/x86/fujitsu-laptop.c | 23 ++
Any set_lcd_level() call can fail for one of two reasons: either
requested brightness is outside the allowed range or the ACPI method
used for setting brightness level is not available. For
bl_update_status(), the first case is handled by backlight core, which
means bl_update_status() will not eve
The backlight part of fujitsu-laptop is only used by laptops which are
incapable of using the standard ACPI video interface for handling
brightness changes. Conversely, on laptops which are capable of using
the latter, no vendor-specific ACPI calls should be made unless
explicitly requested by the
Hi,
cristian.bir...@microchip.com writes:
> From: Cristian Birsan
>
> Check fifo configuration values against device tree values for endpoint fifo
> in auto configuration mode (fifo_mode=0).
>
> Signed-off-by: Cristian Birsan
> ---
> drivers/usb/gadget/udc/atmel_usba_udc.c | 24 +++
On Thu, Mar 30, 2017 at 12:15 PM, Chanwoo Choi wrote:
> On 2017년 03월 30일 17:59, Andy Shevchenko wrote:
>> On Thu, Mar 30, 2017 at 11:39 AM, Chanwoo Choi wrote:
>>> This patch just uses the BIT() macro to make the code simple.
>>
>>> for (i = 0; i < edev->max_supported; i++) {
>>>
Add ghes handling for SEI so that the host kernel could parse and
report detailed error information for SEI which occur in the guest
kernel.
If there were no CPER records, (or the system doesn't support SEI as a GHES
notification mechanism), then yes we should still call kvm_inject_vabt().
Signed
Error Synchronization Barrier (ESB; part of the ARMv8.2 Extensions)
is used to synchronize Unrecoverable errors. That is, containable errors
architecturally consumed by the PE and not silently propagated.
With ESB it is generally possible to isolate an unrecoverable error
between two ESB instructi
On 30/03/17 13:25, Felipe Balbi wrote:
>
> Hi,
>
> Roger Quadros writes:
>> To avoid checkpatch warnings with new patches let's
>> start using the BIT() macro wherever possible.
>>
>> Signed-off-by: Roger Quadros
>
> this didn't apply cleanly, I have manually applied it since it was so
> simpl
From: Wang Xiongfeng
Since SEI is asynchronous, the error data has been consumed. So we must
suppose that all the memory data current process can write are
contaminated. If the process doesn't have shared writable pages, the
process will be killed, and the system will continue running normally.
O
Hi,
cristian.bir...@microchip.com writes:
> From: Cristian Birsan
>
> Use dev_warn() to display EP configuration error to avoid silent failure.
>
> Signed-off-by: Cristian Birsan
> ---
> drivers/usb/gadget/udc/atmel_usba_udc.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> d
On Thu, Mar 30, 2017 at 12:54 PM, Ingo Molnar wrote:
>> > Minor nit: just out of general principle (because the rest of the code
>> > looks so
>> > nice) I'd properly tabulate the last column as well - something like:
>> >
>> > GPIO_LOOKUP(":00:0c.0", -1, "device-wakeup",
>> > GPI
ARM APEI extension proposal added SEI (asynchronous SError interrupt)
notification type for ARMv8.
Add a new GHES error source handling function for SEI. In firmware
first mode, if an error source's notification type is SEI. Then GHES
could parse and report the detail error information.
Signed-of
Add a per-cpu variable to indicate sei is processing, with which we could use to
reserve a separate virtual space address page for sei in next patch
Signed-off-by: Xie XiuQi
---
arch/arm64/kernel/traps.c | 4
include/acpi/ghes.h | 2 ++
2 files changed, 6 insertions(+)
diff --git a/a
On Thu, Mar 30, 2017 at 08:43:39AM +0200, Ingo Molnar wrote:
>
> * Mark Rutland wrote:
>
> > With some minimal CPP, it can be a lot more manageable:
> >
> >
> > #define INSTR_ATOMIC_XCHG(order)\
> > static __always_inline int atomic_xchg##order(atomic_t
On arm64 platform, SEI may interrupt code which had interrupts masked.
But SEI could be masked, so it's not treated as NMI, however SEA is
treated as NMI.
So, the memory area used to transfer hardware error information from
BIOS to Linux can be determined only in NMI, SEI(arm64), IRQ or timer
han
Add a new trace event for ARM processor error information, so that
the user will know what error occurred. With this information the
user may take appropriate action.
These trace events are consistent with the ARM processor error
information table which defined in UEFI 2.6 spec section N.2.4.4.1.
Add a per-cpu variable to indicate sei is processing, with which we could use to
reserve a separate virtual space address page for sei in next patch
Signed-off-by: Xie XiuQi
---
arch/arm64/kernel/traps.c | 4
include/acpi/ghes.h | 2 ++
2 files changed, 6 insertions(+)
diff --git a/a
Hi,
Minas Harutyunyan writes:
> After data out stage gadget driver should not initate ZLP on control EP,
> because it is up to function driver.
not true always, depends on return value from ->setup(). Which problem
did you have? Which gadget driver? How did you reproduce? Which other
tests did
On Thu, Mar 30, 2017 at 12:24 PM, Chanwoo Choi wrote:
> On 2017년 03월 30일 18:05, Andy Shevchenko wrote:
>> On Thu, Mar 30, 2017 at 11:39 AM, Chanwoo Choi wrote:
>>> The extcon core already provides the extcon_register_notifier() function
>>> in order to register the notifier block which is used to
ARM APEI extension proposal added SEI (asynchronous SError interrupt)
notification type for ARMv8.
Add a new GHES error source handling function for SEI. In firmware
first mode, if an error source's notification type is SEI. Then GHES
could parse and report the detail error information.
Signed-of
Add a new trace event for ARM processor error information, so that
the user will know what error occurred. With this information the
user may take appropriate action.
These trace events are consistent with the ARM processor error
information table which defined in UEFI 2.6 spec section N.2.4.4.1.
From: Wang Xiongfeng
Since SEI is asynchronous, the error data has been consumed. So we must
suppose that all the memory data current process can write are
contaminated. If the process doesn't have shared writable pages, the
process will be killed, and the system will continue running normally.
O
According to <> document, we add RAS extension
feature runtime detection, which would be used for error recovery
in the future.
Signed-off-by: Xie XiuQi
Reviewed-by: Kefeng Wang
---
arch/arm64/include/asm/cpucaps.h | 3 ++-
arch/arm64/include/asm/sysreg.h | 2 ++
arch/arm64/kernel/cpufeature
Error Synchronization Barrier (ESB; part of the ARMv8.2 Extensions)
is used to synchronize Unrecoverable errors. That is, containable errors
architecturally consumed by the PE and not silently propagated.
With ESB it is generally possible to isolate an unrecoverable error
between two ESB instructi
Add ghes handling for SEI so that the host kernel could parse and
report detailed error information for SEI which occur in the guest
kernel.
If there were no CPER records, (or the system doesn't support SEI as a GHES
notification mechanism), then yes we should still call kvm_inject_vabt().
Signed
ARM APEI extension proposal added SEI (asynchronous SError interrupt)
notification type for ARMv8.
Add a new GHES error source handling function for SEI. In firmware
first mode, if an error source's notification type is SEI. Then GHES
could parse and report the detail error information.
In firmwa
ARM APEI extension proposal added SEI (asynchronous SError interrupt)
notification type for ARMv8.
Add a new GHES error source handling function for SEI. In firmware
first mode, if an error source's notification type is SEI. Then GHES
could parse and report the detail error information.
In firmwa
On arm64 platform, SEI may interrupt code which had interrupts masked.
But SEI could be masked, so it's not treated as NMI, however SEA is
treated as NMI.
So, the memory area used to transfer hardware error information from
BIOS to Linux can be determined only in NMI, SEI(arm64), IRQ or timer
han
On Thu, Mar 30, 2017 at 03:18:44PM +0530, Anurup M wrote:
>
>
> On Tuesday 21 March 2017 10:22 PM, Mark Rutland wrote:
> >+static int hisi_hw_perf_event_init(struct perf_event *event)
> >>+{
> >>+ struct hw_perf_event *hwc = &event->hw;
> >>+ struct hisi_pmu *hisi_pmu = to_hisi_pmu(event->pmu
Amir,
Am 30.03.2017 um 12:35 schrieb Amir Goldstein:
>> Reading deeper into the proved that I was wrong.
>> AFAIKT UBIFS' journal has currently no way to revive a deleted inode.
>> So, we have to think about a new solution.
>>
>
> Not that I know anything about ubifs, but why do you need the dele
On Thu, 2017-03-30 at 15:24 +0900, Daeseok Youn wrote:
> The condition line in if-statement is needed to be shorthen to
> improve readability.
>
> Signed-off-by: Daeseok Youn
> ---
How about a define for ATOMISP_IS_CHT(isp) instead - as we will need
these tests in other places where there are IS
On 2017년 03월 30일 19:38, Andy Shevchenko wrote:
> On Thu, Mar 30, 2017 at 12:15 PM, Chanwoo Choi wrote:
>> On 2017년 03월 30일 17:59, Andy Shevchenko wrote:
>>> On Thu, Mar 30, 2017 at 11:39 AM, Chanwoo Choi
>>> wrote:
This patch just uses the BIT() macro to make the code simple.
>>>
Remove the description for the non-existing 'num_crtc' to fix the
build warning: ./drivers/gpu/drm/drm_fb_cma_helper.c:557: warning:
Excess function parameter 'num_crtc' description in
'drm_fbdev_cma_init'.
Signed-off-by: Tamara Diaconita
---
drivers/gpu/drm/drm_fb_cma_helper.c | 1 -
1 file cha
On 2017년 03월 30일 19:42, Andy Shevchenko wrote:
> On Thu, Mar 30, 2017 at 12:24 PM, Chanwoo Choi wrote:
>> On 2017년 03월 30일 18:05, Andy Shevchenko wrote:
>>> On Thu, Mar 30, 2017 at 11:39 AM, Chanwoo Choi
>>> wrote:
The extcon core already provides the extcon_register_notifier() function
>>>
Hi Paolo,
On Thu, 30 Mar 2017 11:40:41 +0200 Paolo Bonzini wrote:
>
> On 30/03/2017 00:21, Stephen Rothwell wrote:
> >
> > I noticed that several commits in the kvm tree
> > (git://git.kernel.org/pub/scm/virt/kvm/kvm.git#linux-next) today have
> > no Signed-off-by for their committer :-(
>
>
This fails at step 1. The removal of the frame interval support now
means my setup script fails when trying to set the frame interval on
the camera:
Enumerating pads and links
Setting up format SRGGB8_1X8 816x616 on pad imx219 0-0010/0
Format set: SRGGB8_1X8 816x616
Setting up frame interval 1/25
On Wed, Mar 29, 2017 at 10:56 AM, Arnd Bergmann wrote:
> And here is a workaround that I applied locally to avoid the ICE, but
> I wouldn't want to have this upstream.
>
> commit 8712fd8979a5730318a84922fbcb8791ea5af40e
> Author: Arnd Bergmann
> Date: Wed Mar 29 10:53:48 2017 +0200
>
> work
Hi Masahiro
2017-03-22 16:30 Masahiro Yamada :
> 2017-03-21 23:33 GMT+09:00 Piotr Sroka :
> > DTS properties are used instead of fixed data
> > because PHY settings can be different for different chips/boards.
> > Add description of new DLL PHY delays.
> >
> > Signed-off-by: Piotr Sroka
> > ---
On Thu, Mar 30, 2017 at 1:56 PM, Chanwoo Choi wrote:
> On 2017년 03월 30일 19:42, Andy Shevchenko wrote:
>> On Thu, Mar 30, 2017 at 12:24 PM, Chanwoo Choi wrote:
>>> On 2017년 03월 30일 18:05, Andy Shevchenko wrote:
On Thu, Mar 30, 2017 at 11:39 AM, Chanwoo Choi
wrote:
> +/**
> + *
On 23/03/2017 14:05, Mason wrote:
> +/*
> + * This should probably be module_platform_driver ?
> + */
> +builtin_platform_driver(tango_pcie_driver);
For the sake of completeness,
ERROR: "pci_ecam_map_bus" [drivers/pci/host/pcie-tango.ko] undefined!
ERROR: "pci_host_common_probe" [drivers/pci/hos
On Thu, 2017-03-30 at 12:27 +0200, Nicolai Stange wrote:
> So, please correct me if I'm wrong, there are two problems with
> indefinitely blocking debugfs files' fops:
>
> 1. The one which actually hung your system:
> An indefinitely blocking debugfs_remove() while holding a lock.
> Other ta
On Thu, 2017-03-30 at 08:47 +0200, Jan Kara wrote:
> On Wed 29-03-17 13:54:31, Jeff Layton wrote:
> > On Wed, 2017-03-29 at 13:15 +0200, Jan Kara wrote:
> > > On Tue 21-03-17 14:46:53, Jeff Layton wrote:
> > > > On Tue, 2017-03-21 at 14:30 -0400, J. Bruce Fields wrote:
> > > > > On Tue, Mar 21, 201
On Thu, Mar 30, 2017 at 1:52 PM, Chanwoo Choi wrote:
> On 2017년 03월 30일 19:38, Andy Shevchenko wrote:
>> On Thu, Mar 30, 2017 at 12:15 PM, Chanwoo Choi wrote:
>>> On 2017년 03월 30일 17:59, Andy Shevchenko wrote:
> for (i = 0; i < edev->max_supported; i++) {
> count
Add comments for the virtio_driver members that were not documented.
Signed-off-by: Cornelia Huck
---
include/linux/virtio.h | 4
1 file changed, 4 insertions(+)
diff --git a/include/linux/virtio.h b/include/linux/virtio.h
index 8f4d4bf..e80adf2 100644
--- a/include/linux/virtio.h
+++ b/in
The pattern did not catch include/linux/virtio.h.
Signed-off-by: Cornelia Huck
---
MAINTAINERS | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index a9ae6c1..f96b3f9 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -10902,7 +10902,7 @@ F: drivers/v
Just some stuff I noticed while looking at virtio patches.
Cornelia Huck (2):
MAINTAINERS: fix virtio file pattern
virtio: virtio_driver doc
MAINTAINERS| 2 +-
include/linux/virtio.h | 4
2 files changed, 5 insertions(+), 1 deletion(-)
--
2.8.4
From: Yazen Ghannam
MCA bank 3 is reserved on systems pre-Fam17h, so it didn't have a name.
However, MCA bank 3 is defined on Fam17h systems and can be accessed
using legacy MSRs. Without a name we get a stack trace on Fam17h systems
when trying to register sysfs files for bank 3 on kernels that
On 03/24/2017 at 08:04 PM, Kirill A. Shutemov wrote:
> On Mon, Mar 20, 2017 at 02:11:31PM +0800, Xunlei Pang wrote:
>> I found that the kdump is broken on linux-4.11.0-rc2+
> That's actually tip tree or linux-next. The problematic change is not in
> Linus' tree.
>
>> , probably
>> due to the 5level
On Thu 30-03-17 12:02:03, Ilya Dryomov wrote:
> On Thu, Mar 30, 2017 at 8:25 AM, Michal Hocko wrote:
> > On Wed 29-03-17 16:25:18, Ilya Dryomov wrote:
[...]
> >> We got rid of osdc->request_mutex in 4.7, so these workers are almost
> >> independent in newer kernels and should be able to free up me
> --- a/kernel/sched/fair.c
> +++ b/kernel/sched/fair.c
> @@ -2767,7 +2767,7 @@ static const u32 __accumulated_sum_N32[]
> * Approximate:
> * val * y^n,where y^32 ~= 0.5 (~1 scheduling period)
> */
> -static __always_inline u64 decay_load(u64 val, u64 n)
> +static u64 decay_load(u64 val
On Thu, 2017-03-30 at 10:41 +1100, Dave Chinner wrote:
> On Wed, Mar 29, 2017 at 01:54:31PM -0400, Jeff Layton wrote:
> > On Wed, 2017-03-29 at 13:15 +0200, Jan Kara wrote:
> > > On Tue 21-03-17 14:46:53, Jeff Layton wrote:
> > > > On Tue, 2017-03-21 at 14:30 -0400, J. Bruce Fields wrote:
> > > > >
On Mon, 2017-03-27 at 11:01 +0200, Willy TARREAU wrote:
> On Mon, Mar 27, 2017 at 10:26:07AM +0200, Geert Uytterhoeven wrote:
> > On Mon, Mar 27, 2017 at 10:11 AM, Willy TARREAU > m> wrote:
> > > On Fri, Mar 24, 2017 at 04:19:43PM +0100, Geert Uytterhoeven
> > > wrote:
> > > > On Fri, Mar 24, 2017
On Thu, Mar 30, 2017 at 01:32:51PM +0300, Andy Shevchenko wrote:
On Thu, 2017-03-30 at 18:22 +0800, kbuild test robot wrote:
drivers/net//irda/smsc-ircc2.c:
> > drivers/net//irda/smsc-ircc2.c:
Just out of my curiosity, why do we have // in some reports?
Log shows the bisect runs
Add the bindings for the pinmux functions in the
ARTPEC-6 SoC, including bias and drive strength.
Signed-off-by: Jesper Nilsson
---
.../bindings/pinctrl/axis,artpec6-pinctrl.txt | 85 ++
MAINTAINERS| 1 +
2 files changed, 86 inser
Hi Linus,
On Thu, 30 Mar 2017 11:03:45 +0200
Linus Walleij wrote:
> On Wed, Mar 29, 2017 at 6:04 PM, Boris Brezillon
> wrote:
>
> > Add a driver for Cadence GPIO controller.
>
> IIUC Cadence do a lot of things. Are there variants of this controller?
I'll let Simon answer that one.
> Think
Add pinctrl driver support for the Axis ARTPEC-6 SoC.
There are only some pins that actually have different
functions available, but all can control bias (pull-up/-down)
and drive strength.
Code originally written by Chris Paterson.
Signed-off-by: Jesper Nilsson
---
MAINTAINERS
Enable the pinctrl driver for ARTPEC-6 in the artpec6.dtsi
with all main pinmux functions.
Add pinctrl information to the relevant (uart) nodes.
Signed-off-by: Jesper Nilsson
---
arch/arm/boot/dts/artpec6.dtsi | 87 ++
1 file changed, 87 insertions(+)
dif
On Fri, Mar 24, 2017 at 3:06 PM, Andy Shevchenko
wrote:
> It looks like panel.c belongs to auxdisplay subsystem.
>
> Move it to drivers/auxdisplay folder.
> No functional changes intended.
>
> Signed-off-by: Andy Shevchenko
Acked-by: Geert Uytterhoeven
Gr{oetje,eeting}s,
On Thu, 30 Mar 2017 15:38:54 +0530
Sekhar Nori wrote:
> On Thursday 30 March 2017 03:30 PM, Boris Brezillon wrote:
> > On Thu, 30 Mar 2017 13:13:58 +0530
> > Sekhar Nori wrote:
> >
> >> Hi Boris,
> >>
> >> On Wednesday 29 March 2017 08:33 PM, Boris Brezillon wrote:
> >>> On Mon, 27 Mar 2017
Tobias Regnery writes:
> Explicit include the right header to fix this issue.
uuid.h indeed declares generate_random_uuid(). Looks good to me.
Reviewed-by: Aurelien Aptel
--
Aurélien Aptel / SUSE Labs Samba Team
GPG: 1839 CB5F 9F5B FB9B AA97 8C99 03C8 A49B 521B D5D3
SUSE Linux GmbH, Maxfelds
Hi Tony,
On Monday 27 March 2017 08:35 PM, Tony Lindgren wrote:
> * Kishon Vijay Abraham I [170326 23:27]:
>> On Thursday 23 March 2017 05:16 AM, Tony Lindgren wrote:
>>> +static const struct phy_ops ops = {
>>> + .owner = THIS_MODULE,
>>> +};
>>
>> Given that this phy doesn't have any
Em Wed, Mar 29, 2017 at 05:43:22PM -0700, Andi Kleen escreveu:
> Hi Arnaldo,
>
> This pull requests contains updates to the Intel PMU events JSON files,
> plus two one liner code fixes for the JSON files (also appended as patch)
>
> The most remarkable change is support for Sandy Bridge to Skylak
On Thu, Mar 30, 2017 at 1:29 PM, Boris Brezillon
wrote:
> Linus Walleij wrote:
>> then in your dynamic gpiochip something like
>>
>> ret = bgpio_init(&g->gc, dev, 4,
>> g->base + GPIO_DATA_IN,
>> g->base + GPIO_DATA_SET,
>>
2017-03-30 14:47 GMT+08:00 Wanpeng Li :
> Cc Peterz, Thomas,
> 2017-03-30 12:27 GMT+08:00 Mike Galbraith :
>> On Wed, 2017-03-29 at 16:08 -0400, Rik van Riel wrote:
>>
>>> In other words, the tick on cpu0 is aligned
>>> with the tick on the nohz_full cpus, and
>>> jiffies is advanced while the nohz
On Thu, Mar 30, 2017 at 1:27 PM, Jesper Nilsson wrote:
> Add the bindings for the pinmux functions in the
> ARTPEC-6 SoC, including bias and drive strength.
>
> Signed-off-by: Jesper Nilsson
Pretty much ideal bindings. Just giving some slack for the DT
maintainers to look at it first.
Yours,
L
tree: https://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git x86/asm
head: 19d436268dde95389c616bb3819da73f0a8b28a8
commit: 19d436268dde95389c616bb3819da73f0a8b28a8 [3/3] debug: Add _ONCE() logic
to report_bug()
config: c6x-evmc6678_defconfig (attached as .config)
compiler: c6x-elf-gcc (G
On Wednesday 29 March 2017 09:05 PM, Tejun Heo wrote:
> On Fri, Mar 24, 2017 at 04:38:24PM +0100, Bartlomiej Zolnierkiewicz wrote:
>> On Thursday, March 23, 2017 07:27:05 PM Sekhar Nori wrote:
>>> On Wednesday 22 March 2017 11:50 PM, Bartlomiej Zolnierkiewicz wrote:
Hi,
This patchset
On Tuesday 28 March 2017 06:42 AM, David Lechner wrote:
> This moves the spi0_cs3_pin pinconf node from the LEGO EV3 file to the
> common DA850 include file. This node is applicable to any board, and
> therefore belongs in the common file.
>
> Signed-off-by: David Lechner
Applied for v4.12
Than
From: Michal Hocko
arch_add_memory doesn't need for_device parameter anymore because
devm_memremap_pages already does all what it needs to.
zone_for_memory doesn't have any user anymore as well as the whole zone
shifting infrastructure so drop them as well.
Signed-off-by: Michal Hocko
---
arc
From: Michal Hocko
the primary purpose of this helper is to query the node state so use
the node id directly. This is a preparatory patch for later changes.
Signed-off-by: Michal Hocko
---
mm/memory_hotplug.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/mm/memory
Add description for existing parameter 'pipe' to fix the build
warning: ./drivers/gpu/drm/i915/intel_lpe_audio.c:342: warning: No
description found for parameter 'pipe'.
Signed-off-by: Tamara Diaconita
---
drivers/gpu/drm/i915/intel_lpe_audio.c | 1 +
1 file changed, 1 insertion(+)
diff --git a
From: Michal Hocko
The current memory hotplug implementation relies on having all the
struct pages associate with a zone during the physical hotplug phase
(arch_add_memory->__add_pages->__add_section->__add_zone). In the vast
majority of cases this means that they are added to ZONE_NORMAL. This
h
From: Michal Hocko
There shouldn't be any reason to add initialized when we can tell the
same thing from checking whether there are any pages spanned to the
zone. Remove zone_is_initialized() and replace it by zone_is_empty
which can be used for the same set of tests.
This shouldn't have any vis
From: Michal Hocko
these functions are unreachable because tile doesn't support memory
hotplug becasuse it doesn't select ARCH_ENABLE_MEMORY_HOTPLUG nor
it supports SPARSEMEM.
This code hasn't been compiled for a while obviously because nobody has
noticed that __add_pages has a different signatu
From: Michal Hocko
init_currently_empty_zone doesn't have any error to return yet it is
still an int and callers try to be defensive and try to handle potential
error. Remove this nonsense and simplify all callers.
This patch shouldn't have any visible effect
Signed-off-by: Michal Hocko
---
i
Hi,
I have posted a crude RFC for this rework [1] and there didn't seem any
objections so I have split up the patch into smaller chunks which will
make the review easier hopefully.
Motivation:
Movable onlining is a real hack with many downsides - mainly
reintroduction of lowmem/highmem issues we u
On 03/30/2017 12:27 PM, Andrey Ryabinin wrote:
> Commit 5803ed292e63 ("mm: mark all calls into the vmalloc subsystem
> as potentially sleeping") added might_sleep() to remove_vm_area() from
> vfree(), and commit 763b218ddfaf ("mm: add preempt points into
> __purge_vmap_area_lazy()") actually made v
On 30/03/17 13:23, Richard Weinberger wrote:
> Am 30.03.2017 um 11:49 schrieb Richard Weinberger:
>> Am 30.03.2017 um 11:32 schrieb Adrian Hunter:
diff --git a/fs/ubifs/dir.c b/fs/ubifs/dir.c
index 0858213a4e63..0139155045fe 100644
--- a/fs/ubifs/dir.c
+++ b/fs/ubifs/dir.c
Hi,
I am trying to add support of new component framework API in ARC PGU driver.
The point is that for now we have ARC PGU driver which works with adv7511
encoder. Both of them don't support component framework API. I had to add
support of component framework based dw_hdmi encoder to ARC PGU dri
On Thu, Mar 30, 2017 at 1:33 PM, Jesper Nilsson wrote:
> Add pinctrl driver support for the Axis ARTPEC-6 SoC.
> There are only some pins that actually have different
> functions available, but all can control bias (pull-up/-down)
> and drive strength.
> Code originally written by Chris Paterson.
Hi Marc,
[auto build test ERROR on v4.9-rc8]
[also build test ERROR on next-20170330]
[cannot apply to pci/next]
[if your patch is applied to the wrong git tree, please drop us a note to help
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url:
https://github.com/0day-ci/linux/commits/Marc-Gonzalez/Tango-PCIe
Hi All,
Here is a patch-series adding drivers for Intel FPGA devices.
The Intel FPGA driver provides interfaces for userspace applications to
configure, enumerate, open, and access FPGA accelerators on platforms
equipped with Intel(R) FPGA solutions and enables system level management
functions s
Add a document for Intel FPGA driver overview.
Signed-off-by: Enno Luebbers
Signed-off-by: Xiao Guangrong
Signed-off-by: Wu Hao
---
Documentation/fpga/intel-fpga.txt | 259 ++
1 file changed, 259 insertions(+)
create mode 100644 Documentation/fpga/intel-fpg
From: Zhang Yi
The Intel FPGA device appears as a PCIe device on the system. This patch
implements the basic framework of the driver for Intel PCIe device which
locates between CPU and Accelerated Function Units (AFUs).
Signed-off-by: Tim Whisonant
Signed-off-by: Enno Luebbers
Signed-off-by: S
During FPGA device (e.g PCI-based) discovery, platform devices are
registered for different FPGA function units. But the device node path
isn't quite friendly to applications.
Consider this case, applications want to access child device's sysfs file
for some information.
1) Access using bus-based
From: Xiao Guangrong
This patch abstracts the common operations of the sub features, and defines
the feature_ops data structure, including init, uinit and ioctl function
pointers. And this patch adds some common helper functions for FME and AFU
drivers, e.g feature_dev_use_begin/end which are use
From: Xiao Guangrong
Device Featuer List structure creates a link list of feature headers
within the MMIO space to provide an extensiable way of adding features.
The Intel FPGA PCIe driver walks through the feature headers to enumerate
feature devices, FPGA Management Engine (FME) and FPGA Port
From: Kang Luwei
The header register set is always present for FPGA Management Engine (FME),
this patch implements init and uinit function for header sub feature and
introduce several read-only sysfs interfaces for the capability and status.
Sysfs interfaces:
* /sys/class/fpga///ports_num
Read
FPGA_GET_API_VERSION and FPGA_CHECK_EXTENSION ioctls are common ones which
need to be supported by all feature devices drivers including FME and AFU.
Userspace application can use these ioctl interfaces to get the API info
and check if specific extension is supported or not in current driver.
This
DMA memory regions are required for Accelerated Function Unit (AFU) usage.
These two ioctls allow user space applications to map user memory regions
for dma, and unmap them after use. Iova is returned from driver to user
space application via FPGA_PORT_DMA_MAP ioctl. Application needs to unmap
it a
From: Xiao Guangrong
User Accelerated Function Unit sub feature exposes the MMIO region of
the AFU. After valid green bitstream (GBS) is programmed and port is
enabled, then this MMIO region could be accessed.
This patch adds support to enumerate the AFU MMIO region and expose it
to userspace vi
FPGA_GET_API_VERSION and FPGA_CHECK_EXTENSION ioctls are common ones which
need to be supported by all feature devices drivers including FME and AFU.
This patch implements above 2 ioctls in Intel FPGA Accelerated Function
Unit (AFU) driver.
Signed-off-by: Tim Whisonant
Signed-off-by: Enno Luebber
On Intel FPGA devices, the Accelerated Function Unit (AFU), can be
reprogrammed for different functions. It connects to the FPGA
infrastructure("blue bistream") via a Port. Port CSRs are implemented
separately from the AFU CSRs to provide control and status of the Port.
Once valid green bitstream i
On Thu, Mar 30, 2017 at 04:21:08AM -0700, Paul Turner wrote:
> > --- a/kernel/sched/fair.c
> > +++ b/kernel/sched/fair.c
> > @@ -2767,7 +2767,7 @@ static const u32 __accumulated_sum_N32[]
> > * Approximate:
> > * val * y^n,where y^32 ~= 0.5 (~1 scheduling period)
> > */
> > -static __al
The header register set is always present for the Port/AFU, it is mainly
for capability, control and status of the ports that AFU connected to.
This patch implements header sub feature support. Below user interfaces
are created by this patch.
Sysfs interface:
* /sys/class/fpga///id
Read-only. P
From: Kang Luwei
Partial Reconfiguration (PR) is the most important function for FME. It
allows reconfiguration for given Port/Accelerated Function Unit (AFU).
This patch adds support for PR sub feature. In this patch, it registers
a fpga_mgr and implements fpga_manager_ops, and invoke fpga_mgr_
On Thu, Mar 30, 2017 at 5:46 AM, Michael Neuling wrote:
>> > wrote:
>> > > Hi Greg,
>> > >
>> > > Today's linux-next merge of the tty tree got a conflict in:
>> > >
>> > > drivers/tty/tty_ldisc.c
>> > >
>> > > between commit:
>> > >
>> > > 5362544bebe8 ("tty: don't panic on OOM in tty_set_ldis
From: Kang Luwei
The FPGA Management Engine (FME) provides power, thermal management,
performance counters, partial reconfiguration and other functions. For each
function, it is packaged into a private feature linked to the FME feature
device in the 'Device Feature List'. It's a platform device c
For FPGA Management Engine (FME), it requires fpga_for_each_port callback
for actions on ports, so export this function from PCIe driver by adding
the callback to the platform data.
Signed-off-by: Tim Whisonant
Signed-off-by: Enno Luebbers
Signed-off-by: Shiva Rao
Signed-off-by: Christopher Rau
From: Xiao Guangrong
For feature devices drivers, both the FPGA Management Engine (FME) and
Accelerated Function Unit (AFU) driver need to expose user interfaces via
the device file, for example, mmap and ioctls.
This patch adds chardev support in the pcie driver for feature devices,
FME and AFU
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