Hi Niklas,
On Friday 10 March 2017 09:17 PM, Niklas Cassel wrote:
>
>
> On 03/10/2017 01:56 PM, Kishon Vijay Abraham I wrote:
>> Hi Niklas,
>>
>> On Friday 10 March 2017 06:01 PM, Niklas Cassel wrote:
>>> On 03/10/2017 12:36 PM, Kishon Vijay Abraham I wrote:
Hi,
On Thursday 09 Mar
It's simply extension for one more page table level.
Signed-off-by: Kirill A. Shutemov
---
arch/x86/mm/gup.c | 33 +++--
1 file changed, 27 insertions(+), 6 deletions(-)
diff --git a/arch/x86/mm/gup.c b/arch/x86/mm/gup.c
index 1f3b6ef105cd..456dfdfd2249 100644
--- a/
5-level paging support is required from hardware when compiled with
CONFIG_X86_5LEVEL=y. We may implement runtime switch support later.
Signed-off-by: Kirill A. Shutemov
---
arch/x86/boot/cpucheck.c | 9 +
arch/x86/boot/cpuflags.c | 12 ++--
arch/
This patch extends x86 headers to enable 5-level paging support.
It's still based on . We will get to the
point where we can have later.
Signed-off-by: Kirill A. Shutemov
---
arch/x86/include/asm/pgtable-2level_types.h | 1 +
arch/x86/include/asm/pgtable-3level_types.h | 1 +
arch/x86/includ
Allocate additional page table level and change efi_sync_low_kernel_mappings()
to make syncing logic work with additional page table level.
Signed-off-by: Kirill A. Shutemov
Reviewed-by: Matt Fleming
---
arch/x86/platform/efi/efi_64.c | 33 +++--
1 file changed, 23 i
This patch covers simple cases only.
Signed-off-by: Kirill A. Shutemov
---
arch/x86/kernel/tboot.c| 6 +-
arch/x86/kernel/vm86_32.c | 6 +-
arch/x86/mm/fault.c| 39 +--
arch/x86/mm/init_32.c | 22
Nothing special: just handle one more level.
Signed-off-by: Kirill A. Shutemov
---
arch/x86/mm/ident_map.c | 47 ---
1 file changed, 40 insertions(+), 7 deletions(-)
diff --git a/arch/x86/mm/ident_map.c b/arch/x86/mm/ident_map.c
index 4473cb4f8b90..2c
Straight-forward extension of existing code to support additional page
table level.
Signed-off-by: Kirill A. Shutemov
---
arch/x86/mm/pageattr.c | 56 --
1 file changed, 41 insertions(+), 15 deletions(-)
diff --git a/arch/x86/mm/pageattr.c b/arch/
We don't need it anymore. 17be0aec74fb ("x86/asm/entry/64: Implement
better check for canonical addresses") made canonical address check
generic wrt. address width.
Signed-off-by: Kirill A. Shutemov
---
arch/x86/entry/entry_64.S | 7 ++-
1 file changed, 2 insertions(+), 5 deletions(-)
diff
This basically restores slightly modified version of original
sync_global_pgds() which we had before foldedl p4d was introduced.
The only modification is protection against 'address' overflow.
Signed-off-by: Kirill A. Shutemov
---
arch/x86/mm/init_64.c | 37 +
With folded p4d, pgd_clear() is nop. Change clear_pgds() to use
p4d_clear() instead.
Signed-off-by: Kirill A. Shutemov
Cc: Dmitry Vyukov
---
arch/x86/mm/kasan_init_64.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/arch/x86/mm/kasan_init_64.c b/arch/x86/mm/kasa
Add operations to allocate/release p4ds. Xen requires more work.
Signed-off-by: Kirill A. Shutemov
---
arch/x86/include/asm/paravirt.h | 44 +++
arch/x86/include/asm/paravirt_types.h | 7 +-
arch/x86/include/asm/pgalloc.h| 2 ++
arch/x86/kernel
Most of things are in place and we can enable support of 5-level paging.
Enabling XEN with 5-level paging requires more work. The patch makes XEN
dependent on !X86_5LEVEL.
Signed-off-by: Kirill A. Shutemov
---
arch/x86/Kconfig | 5 +
arch/x86/xen/Kconfig | 1 +
2 files changed, 6 insert
Here is v5 of 5-level paging patchset. Please review and consider applying.
== Overview ==
x86-64 is currently limited to 256 TiB of virtual address space and 64 TiB
of physical address space. We are already bumping into this limit: some
vendors offers servers with 64 TiB of memory today.
To ove
Simple extension to support one more page table level.
Signed-off-by: Kirill A. Shutemov
---
arch/x86/mm/dump_pagetables.c | 49 ---
1 file changed, 42 insertions(+), 7 deletions(-)
diff --git a/arch/x86/mm/dump_pagetables.c b/arch/x86/mm/dump_pagetables.
With 4-level paging copying happens on p4d level, as we have pgd_none()
always false when p4d_t folded.
Signed-off-by: Kirill A. Shutemov
---
arch/x86/mm/fault.c | 27 ---
1 file changed, 24 insertions(+), 3 deletions(-)
diff --git a/arch/x86/mm/fault.c b/arch/x86/mm/fau
The first part of memory map (up to %esp fixup) simply scales existing
map for 4-level paging by factor of 9 -- number of bits addressed by
additional page table level.
The rest of the map is uncahnged.
Signed-off-by: Kirill A. Shutemov
---
Documentation/x86/x86_64/mm.txt | 33 +
Split these helpers few per-level functions and add p4d support.
Signed-off-by: Xiong Zhang
[kirill.shute...@linux.intel.com: split off into separate patch]
Signed-off-by: Kirill A. Shutemov
---
arch/x86/xen/mmu.c | 245 -
arch/x86/xen/mmu.h |
Properly populate addition pagetable level if CONFIG_X86_5LEVEL is
enabled.
Signed-off-by: Kirill A. Shutemov
---
arch/x86/mm/init_64.c | 71 ---
1 file changed, 62 insertions(+), 9 deletions(-)
diff --git a/arch/x86/mm/init_64.c b/arch/x86/mm/ini
Extends pagetable headers to support new paging mode.
Signed-off-by: Kirill A. Shutemov
---
arch/x86/include/asm/pgtable_64.h | 11 +++
arch/x86/include/asm/pgtable_64_types.h | 20 +++
arch/x86/include/asm/pgtable_types.h| 10 +-
arch/x86/mm/pgtable.c
On x86, 5-level paging enables 56-bit userspace virtual address space.
Not all user space is ready to handle wide addresses. It's known that
at least some JIT compilers use higher bits in pointers to encode their
information. It collides with valid pointers with 5-level paging and
leads to crashes.
This patch bring support for non-folded additional page table level.
Signed-off-by: Kirill A. Shutemov
Cc: Dmitry Vyukov = 5 && i < PTRS_PER_P4D; i++)
+ kasan_zero_p4d[i] = __p4d(p4d_val);
+
kasan_map_early_shadow(early_level4_pgt);
kasan_map_early_shadow(init_level4
This patch converts x86 to use proper folding of new page table level
with .
That's a bit of kitchen sink, but I don't see how to split it further.
Signed-off-by: Kirill A. Shutemov
---
arch/x86/include/asm/paravirt.h | 33 +-
arch/x86/include/asm/paravirt_types.h | 12 ++-
arch/x86
From: Jiri Kosina
Date: Wed, 8 Mar 2017 16:03:32 +0100 (CET)
> From: Jiri Kosina
>
> The original reason [1] for having hidden qdiscs (potential scalability
> issues in qdisc_match_from_root() with single linked list in case of large
> amount of qdiscs) has been invalidated by 59cc1f61f0 ("net:
set_up_temporary_text_mapping() and relocate_restore_code() require
trivial adjustments to handle additional page table level.
Signed-off-by: Kirill A. Shutemov
---
arch/x86/power/hibernate_64.c | 49 ++-
1 file changed, 35 insertions(+), 14 deletions(-)
With 5-level paging randomization happens on P4D level instead of PUD.
Maximum amount of physical memory also bumped to 52-bits for 5-level
paging.
Signed-off-by: Kirill A. Shutemov
---
arch/x86/mm/kaslr.c | 82 -
1 file changed, 63 insertions
On 3/9/2017 18:57, Hans Verkuil wrote:
Hi Songjun,
On 08/03/17 03:25, Wu, Songjun wrote:
Hi Colin,
Thank you for your comment.
It is a bug, will be fixed in the next patch.
Do you mean that you will provide a new patch for this? Is there anything
wrong with this patch? It seems reasonable
We don't need extra virtual address space for ESPFIX, so it stays within
one PUD page table for both 4- and 5-level paging.
Signed-off-by: Kirill A. Shutemov
---
arch/x86/kernel/espfix_64.c | 12 +++-
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/arch/x86/kernel/espfix_64
Handle additional page table level in kexec code.
Signed-off-by: Kirill A. Shutemov
---
arch/x86/include/asm/kexec.h | 1 +
arch/x86/kernel/machine_kexec_32.c | 4 +++-
arch/x86/kernel/machine_kexec_64.c | 14 --
3 files changed, 16 insertions(+), 3 deletions(-)
diff --git a
This patch adds support for 5-level paging during early boot.
It generalizes boot for 4- and 5-level paging on 64-bit systems with
compile-time switch between them.
Signed-off-by: Kirill A. Shutemov
---
arch/x86/boot/compressed/head_64.S | 23 +--
arch/x86/include/asm/pgtable.h
From: Madalin Bucur
Date: Thu, 9 Mar 2017 16:36:55 +0200
> This patch set introduces a series of fixes and features to the DPAA 1
> drivers. Besides activating hardware Rx checksum offloading, four traffic
> classes are added for Tx traffic prioritisation.
>
> The changes are also available on t
From: "Gautham R. Shenoy"
Currently, the powernv cpu-offline function assumes that platform idle
states such as stop on POWER9, winkle/sleep/nap on POWER8 are always
available. On POWER8, it picks nap as the default state if other deep
idle states like sleep/winkle are not available and enabled i
From: "Gautham R. Shenoy"
Hi,
This patchset contains fixes to make CPU-Hotplug working on correctly
on POWER9 DD1 systems.
There are three patches in the series.
- The first patch adds a fallback mechanism for CPU-Hotplug when no
platform idle state is available.
- The second patch ensures
From: "Gautham R. Shenoy"
Currently during idle-init on power9, if we don't find suitable stop
states in the device tree that can be used as the
default_stop/deepest_stop, we set stop0 (ESL=1,EC=1) as the default
stop state psscr to be used by power9_idle and deepest stop state
which is used by C
From: "Gautham R. Shenoy"
POWER9 platform can be configured to rebalance per-thread resources
within a core in order to improve SMT performance. Certain STOP
states can be configure to relinquish resources include some
hypervisor SPRs in order to enable SMT thread folding.
Due to relinquishing
Hi,
4.11.0-rc1 failed to boot on Power 6 LPAR with the below warnings.
Machine Type : Power 6 LPAR
Kernel : 4.11.0-rc1
Config : p6-BE-config file attached
rq->clock_update_flags < RQCF_ACT_SKIP
[ cut here ]
WARNING: CPU: 8 PID: 0 at kernel/sched/sched.h:833
.update_block
On March 13, 2017 8:36 AM Minchan Kim wrote:
>
> Anyone doesn't use ret variable. Remove it.
>
> Acked-by: Kirill A. Shutemov
> Signed-off-by: Minchan Kim
> ---
Acked-by: Hillf Danton
> mm/rmap.c | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/mm/rmap.c b/mm/rm
This patch fixes an issue that this driver doesn't take care of the runtime
PM. This code assumed that devm_phy_create() called pm_runtime_enable(dev),
but it misunderstood the dev_phy_create()'s specification.
This driver should call the own pm_runtime_pm() before dev_phy_create().
Fixes: f3b5a8d
On 2017.03.12 10:12 Rafael J. Wysocki wrote:
> This patch series fixes a couple of bugs in intel_pstate, cleans up the code
> in
> it somewhat and makes some changes targeted at overhead reductions.
>
If clean up and overhead reductions are being considered, is there any interest
in changing the
On March 13, 2017 8:36 AM Minchan Kim wrote:
>
> If we found lazyfree page is dirty, try_to_unmap_one can just
> SetPageSwapBakced in there like PG_mlocked page and just return
> with SWAP_FAIL which is very natural because the page is not
> swappable right now so that vmscan can activate it.
>
From: Thierry Reding
Date: Fri, 10 Mar 2017 17:34:52 +0100
> This series of patches start with a few cleanups that I ran across while
> adding Tegra186 support to the stmmac driver. It then adds code for FIFO
> size parsing from feature registers and finally enables support for the
> incarnation
On Sun, Mar 12, 2017 at 10:48 PM, Guenter Roeck wrote:
> On 03/11/2017 09:25 AM, Krzysztof Kozlowski wrote:
>>
>> The Exynos4412 has the same watchdog as newer SoCs (e.g. Exynos5250).
>> Just like the others, for working it requires additional steps in Power
>> Management Unit: unmasking the reset
On Sun, Mar 12, 2017 at 11:01 PM, Greg KH wrote:
>> So I blame this on flight level 350, but we discussed this at kernel
>> summit. Every patch we cherry-pick over comes with a "cherry-picked from
>> $sha1" line, as long as you ignore any such sha1 as duplicate you won't
>> see the same patch twic
Hi,
Our LSI(Broadcom) SAS3.5 HBA device's support virtual SES device.
Whenever we load the mpt3sas driver then we are observing below error message,
"Wrong diagnostic page; asked for 7 got 0"
Our virtual SES device doesn't support Diagnostic page 7, it supports
only below diagnostic pages,
• 0
On Sun, Mar 12, 2017 at 10:56 PM, Guenter Roeck wrote:
> On 03/11/2017 09:42 AM, Krzysztof Kozlowski wrote:
>>
>> Structures watchdog_device, watchdog_ops and s3c2410_wdt_variant are not
>> modified so they can be made const to increase code safeness.
>>
>> Signed-off-by: Krzysztof Kozlowski
>> -
Commit-ID: bd174169c7a12a37b3b4aa2221f084ade010b182
Gitweb: http://git.kernel.org/tip/bd174169c7a12a37b3b4aa2221f084ade010b182
Author: David Windsor
AuthorDate: Fri, 10 Mar 2017 10:34:12 -0500
Committer: Ingo Molnar
CommitDate: Mon, 13 Mar 2017 07:41:08 +0100
locking/refcount: Add refc
From: Geliang Tang
Date: Sat, 11 Mar 2017 08:46:56 +0800
> Use setup_timer() instead of init_timer() to simplify the code.
>
> Signed-off-by: Geliang Tang
Applied.
From: Geliang Tang
Date: Sat, 11 Mar 2017 08:46:59 +0800
> Use setup_timer() instead of init_timer() to simplify the code.
>
> Signed-off-by: Geliang Tang
Applied.
On Sun, Mar 12, 2017 at 10:52 PM, Greg KH wrote:
> Why don't the maintainers know which tree to put them in when they are
> submitted? As an example, if I get a patch that needs to go to Linus, I
> put it in my usb-linus branch, and when it hits a -rc release, I then
> merge that -rc back into my
From: Vivien Didelot
Date: Sat, 11 Mar 2017 16:12:46 -0500
> The purpose of this patch series is to rework the code related to the
> Address Translation Unit (ATU), and bring support for it to the 88E6390
> family of switch chips.
>
> All Global (1) ATU related code have been reworked and moved
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