Register addresses are normally displayed in hex throughout the Arizona
driver. Update the arizona_poll_reg function to follow this convention.
Signed-off-by: Charles Keepax
---
drivers/mfd/arizona-core.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/mfd/arizona
Hello!
On 3/9/2017 11:39 AM, Sekhar Nori wrote:
It took a while to get to it but here is the draft driver patch
against v4.11-rc1. Please test.
I tested this on DM6446 EVM. I was able to mount existing partitions on
the hard disk and see that the directory listing looks good[1]. I will do
mo
On Thu, Mar 09, 2017 at 10:15:13AM +0100, Michal Hocko wrote:
> Greg, do you see any obstacle to have this merged. The discussion so far
> shown that a) vendors are not using the code as is b) there seems to be
> an agreement that something else than we have in the kernel is really
> needed.
Well,
On 03/09/2017 10:26 AM, Reshetova, Elena wrote:
>
>> On 03/09/2017 08:18 AM, Reshetova, Elena wrote:
On Mon, Mar 06, 2017 at 04:21:09PM +0200, Elena Reshetova wrote:
> refcount_t type and corresponding API should be
> used instead of atomic_t when the variable is used as
> a refer
Felipe,
On 08/03/17 16:05, Roger Quadros wrote:
> The streaming_maxburst module parameter is 0 offset (0..15)
> so we must add 1 while using it for wBytesPerInterval
> calculation for the SuperSpeed companion descriptor.
>
> Without this host uvcvideo driver will always see the wrong
> wBytesPerI
Hi Pavel,
On Wed, Mar 8, 2017 at 10:22 PM, Pavel Machek wrote:
> Well, I have fast CPUs, but most of the time they just compile
> stuff. Especially bisect is compile-heavy. I suspect going back to
> gcc-3.2 would bring me bigger advantages than CPU upgrade...
I hope you do use ccache or distcc?
On 09-03-17, 16:15, YuanTian Tang wrote:
> From: Tang Yuantian
>
> On some platforms, property device-type may be missed in soc node
> in dts which caused the bus-frequency can not be obtained correctly.
>
> This patch enhanced the bus-frequency calculation. When property
> device-type is missed
2017-03-09 9:23 GMT+08:00 Wanpeng Li :
> 2016-12-20 0:17 GMT+08:00 Paolo Bonzini :
>> Since bf9f6ac8d749 ("KVM: Update Posted-Interrupts Descriptor when vCPU
>> is blocked", 2015-09-18) the posted interrupt descriptor is checked
>> unconditionally for PIR.ON. Therefore we don't need KVM_REQ_EVENT
On 2017-03-09 01:32, Paul Gortmaker wrote:
*snip* *snip*
> If the mux subsystem isn't board specific (and at a glance, it seems
> like it is not) then it might be the former and not the latter. But I
> leave that call up to you
The mux subsystem may be needed for some boards and not for others,
On Wed, Mar 08, 2017 at 12:38:40PM -0500, Dan Streetman wrote:
>
> It looks like the crypto_scomp interface is buried under
> include/crypto/internal/scompress.h, however that's exactly what zswap
> should be using. We don't need to switch to an asynchronous interface
> that's rather significantl
Help a bit the compiler to provide better code:
unsigned int f(int i)
{
return 1 << (31 - i);
}
unsigned int g(int i)
{
return 0x8000 >> i;
}
Disassembly of section .text:
:
0: 20 63 00 1f subfic r3,r3,31
4: 39 20 00 01 li r9,1
8: 7d 23
This patch allows the use of IRQ to notify the change of GPIO status
on MPC8xx CPM IO ports. This then allows to associate IRQs to GPIOs
in the Device Tree.
Ex:
CPM1_PIO_C: gpio-controller@960 {
#gpio-cells = <2>;
compatible = "fsl,cpm1-pario-bank-c";
Hello!
On 3/9/2017 11:47 AM, Roger Quadros wrote:
As per [1] issue #4,
"The periodic EP scheduler always tries to schedule the EPs
that have large intervals (interval equal to or greater than
128 microframes) into different microframes. So it maintains
an internal counter and increments for eac
On Thu, Mar 9, 2017 at 10:46 AM, Andrey Ryabinin
wrote:
> On 03/08/2017 11:10 AM, Nikolay Borisov wrote:
>
>>
>> So apparently this is indeed a false positive, resulting from using the old
>> compiler. I used the attached patch to verify it.
>>
>> And what it prints is :
>> [ 17.184288] Assigned
From: Rafał Miłecki
Printing with pr_* functions requires adding line break manually.
Signed-off-by: Rafał Miłecki
---
Hi,
I think this change is so trivial it's not worth splitting per single
driver. Are you OK with that?
---
drivers/clocksource/arc_timer.c | 14 +++---
dri
On Thu, Mar 9, 2017 at 10:24 AM, Zefan Li wrote:
> On 2017/3/3 3:15, Dmitry Vyukov wrote:
>> Hello,
>>
>> The following program triggers WARNING in cgroup_kill_sb:
>> https://gist.githubusercontent.com/dvyukov/47a37d3b899ece1f57e512dc6c90bca6/raw/250894f3d6e2954eed01bac39e4c3b7ec59a9c31/gistfile1.
Add device IDs for DRA74x and DRA72x devices. These devices have
configurable PCI endpoint.
Signed-off-by: Kishon Vijay Abraham I
---
include/linux/pci_ids.h |2 ++
1 file changed, 2 insertions(+)
diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
index a4f77fe..5f6b71d 100644
-
Hi Tyler Baicar,
On 2017/3/7 4:45, Tyler Baicar wrote:
> Currently there are trace events for the various RAS
> errors with the exception of ARM processor type errors.
> Add a new trace event for such errors so that the user
> will know when they occur. These trace events are
> consistent with the
On Thu, Mar 09, 2017 at 02:38:06PM +0800, Dave Young wrote:
> Add efi/kexec list.
>
> On 03/08/17 at 12:16pm, Omar Sandoval wrote:
[snip]
> I have no more clue yet from your provided log, but the runtime value is
> odd to me. It is set in below code:
>
> arch/x86/platform/efi/efi.c: efi_systab_
On Wed 08-03-17 18:21:30, Kirill A. Shutemov wrote:
> On Wed, Mar 08, 2017 at 02:57:35PM +0100, Michal Hocko wrote:
> > On Mon 06-03-17 23:45:13, Kirill A. Shutemov wrote:
> > > Convert all non-architecture-specific code to 5-level paging.
> > >
> > > It's mostly mechanical adding handling one mor
Am Mittwoch, den 01.03.2017, 20:22 +0200 schrieb Georgi Djakov:
> This patch introduce a new API to get the requirement and configure the
> interconnect buses across the entire chipset to fit with the current demand.
>
> The API is using a consumer/provider-based model, where the providers are
> t
Hi Mike
On 3/9/2017 7:37 AM, Mike Looijmans wrote:
> On 06-03-17 13:27, Ramiro Oliveira wrote:
>> Add option in Kconfig to use Xilinx VDMA in ARC processors.
>>
>> Signed-off-by: Ramiro Oliveira
>> ---
>> drivers/dma/Kconfig | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --g
On 9.03.2017 11:46, Andrey Ryabinin wrote:
> On 03/08/2017 11:10 AM, Nikolay Borisov wrote:
>
>>
>> So apparently this is indeed a false positive, resulting from using the old
>> compiler. I used the attached patch to verify it.
>>
>> And what it prints is :
>> [ 17.184288] Assigned fbdev-
Hi Hans,
On ven., 2017-03-03 at 15:27 +0100, Hans de Goede wrote:
> On 03-03-17 10:24, Jean Delvare wrote:
> > On Sat, 25 Feb 2017 18:23:55 +0100, Hans de Goede wrote:
> > > 1) Rather then add cmdline options for all things which can be DMI quirked
> > > and thus may need to be specified, this onl
Hello,
Le 09/03/2017 à 08:01, Peter Senna Tschudin a écrit :
> On Wed, Mar 08, 2017 at 02:40:25PM -0800, Jeff Kirsher wrote:
>> On Wed, 2017-03-08 at 17:19 +0100, Romain Perier wrote:
>>> The PCI pool API is deprecated. This commit replaces the PCI pool old
>>> API by the appropriate function wit
On Thu 09-03-17 10:30:28, Greg KH wrote:
> On Thu, Mar 09, 2017 at 10:15:13AM +0100, Michal Hocko wrote:
> > Greg, do you see any obstacle to have this merged. The discussion so far
> > shown that a) vendors are not using the code as is b) there seems to be
> > an agreement that something else than
On 03/08/2017 11:10 AM, Nikolay Borisov wrote:
>
> So apparently this is indeed a false positive, resulting from using the old
> compiler. I used the attached patch to verify it.
>
> And what it prints is :
> [ 17.184288] Assigned fbdev-blacklist.conff(880001ea8020)20 whole
> object: f
2017-03-06 17:04 GMT+01:00 Daniel Vetter :
> On Mon, Mar 06, 2017 at 11:58:05AM +0100, Mark Brown wrote:
>> On Mon, Mar 06, 2017 at 11:40:41AM +0100, Daniel Vetter wrote:
>>
>> > No one gave a thing about android in upstream, so Greg KH just dumped it
>> > all into staging/android/. We've discussed
Hi Elaine,
you should also add the RK805 to the device tree bindings documentation in
Documentation/devicetree/bindings/mfd/rk808.txt
Regards,
Wadim
Am 09.03.2017 um 09:49 schrieb Elaine Zhang:
> Elaine Zhang (4):
> mfd: rk808: fix up the chip id get failed
> linux: mfd: rk808: add rk805 r
Hi,
linkhuge_rw test case fails on 4.11.0-rc1 kernel.
# HUGETLB_VERBOSE=99 HUGETLB_DEBUG=yes HUGETLB_SHARE=0
LD_LIBRARY_PATH=./obj64 HUGETLB_ELFMAP=R ./tests/obj64/linkhuge_rw
libhugetlbfs [pkvmhab012:8026]: INFO: Found pagesize 16384 kB
libhugetlbfs [pkvmhab012:8026]: INFO: Detected page sizes
On 09/03/2017 10:40, Wanpeng Li wrote:
> 2017-03-09 9:23 GMT+08:00 Wanpeng Li :
>> 2016-12-20 0:17 GMT+08:00 Paolo Bonzini :
>>> Since bf9f6ac8d749 ("KVM: Update Posted-Interrupts Descriptor when vCPU
>>> is blocked", 2015-09-18) the posted interrupt descriptor is checked
>>> unconditionally for
The drm_encoder structure provides us with a pointer to the crtc
currently tied to the encoder. Subsequently we can extract the
tcon and backend pointers from our crtc structure, instead of
getting it directly from the sun4i_drv structure.
Signed-off-by: Chen-Yu Tsai
---
drivers/gpu/drm/sun4i/su
Some Allwinner SoCs have 2 display pipelines, as in 2 of each
components, including the frontend, backend, TCON, and any other
extras.
As the backend and TCON are always paired together and form the CRTC,
we need to know which backend or TCON we are currently probing, so we
can pair them when init
Some Allwinner SoCs have two display pipelines (frontend -> backend ->
tcon).
Previously we only supported one pipeline. This patch extends the
current driver to support two. It extends the tcon and backend pointers
in sun4i_drv into arrays, and makes the related bind functions store
the pointer i
sun4i_crtc controls the backend and tcon hardware blocks of the display
pipeline.
Pass pointers to the underlying devices into the crtc init function,
instead of trying to fetch them from the drm_device structure. This
avoids the headache of trying to figure out which devices the crtc
is actually
sun4i_layer only controls the backend hardware block of the display
pipeline.
Pass pointers to the underlying backend in the layer init function,
instead of trying to fetch it from the drm_device structure. This
avoids the headache of trying to figure out which device the layers
actually belong to
The digital AIF interfaces has been renamed in the sun8i audio codec
driver so the audio-routing in the device tree must be renamed too.
Signed-off-by: Mylène Josserand
---
arch/arm/boot/dts/sun8i-a33.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/
An unwanted space is present in an audio widget's name on the dapm
routing. It causes an error on the recognition of this widget (error:
("no dapm match for AIF1 Slot 0 Right").
Remove the space fixes it.
Signed-off-by: Mylène Josserand
---
sound/soc/sunxi/sun8i-codec.c | 2 +-
1 file changed,
Update the driver to use SND_SOC_DAPM_AIF_IN instead of
SND_SOC_DAPM_DAC.
Rename the interface's widgets to be more precise on which slot
the interface is connected.
Signed-off-by: Mylène Josserand
---
sound/soc/sunxi/sun8i-codec.c | 20 +++-
1 file changed, 11 insertions(+), 9 d
Some Allwinner SoCs have 2 display pipelines, as in 2 of each
components, including the frontend, backend, TCON, and any other
extras.
As the backend and TCON are always paired together and form the CRTC,
we need to know which backend or TCON we are currently probing, so we
can pair them when init
tcon0 contains a muxing register used to mux tcon output to downstream
hdmi or mipi dsi encoders. tcon0 must be available for the mux to be
configured.
Whether the display subsystem is enabled or not is now solely controlled
by the display-engine node.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/b
The Allwinner A31/A31s SoCs have 2 display pipelines, as in 2 display
frontends, backends, and tcons each. The relationship between the
backends and tcons are 1:1, but the frontends can feed either backend.
Add device nodes and of graph nodes describing this relationship.
Signed-off-by: Chen-Yu T
The TCON driver calls sun4i_tcon_init_regmap and sun4i_tcon_init_clocks
in its bind function. The former creates a regmap and writes to several
register to clear its configuration to a known default. The latter
initializes various clocks. This includes enabling the bus clock for
register access and
A pointer to the underlying tcon of the crtc was added to the sun4i_crtc
structure in "drm/sun4i: Add backend and tcon pointers to sun4i_crtc".
However the crtc init function was still using the copy from sun4i_drv
to set drm_crtc.port. This was an oversight when the patches were
reordered.
Switch
Hi Maxime,
This is part 3 of my sun4i drm clean up series. In this part support
for 2 display pipelines is added, after some more code cleanups and
restructuring.
While this series enables the second display pipeline, there's no
usable output at the moment. For the A31, the second TCON's panel
in
The backporch programmed into the tcon registers is actually the
backporch + hsync length from the display timings, as indicated in
the interface timing diagrams found in the user manual of the A31
and A33 SoCs.
The comments for channel 0 mistakenly describe the discrepancy as
TCON backporch = fro
devm_input_allocate_device() already causes the supplied struct device
to be set as the parent of the input device, so doing it again is
redundant.
Signed-off-by: Michał Kępień
---
This patch needs my recent intel-hid cleanup series to apply cleanly.
In other words, it should apply on top of test
Hello Akshay,
unfortunately there are not many CAN controllers for the SPI bus. I just
know the MPC251x, which behaves badly (message losses) under Linux,
especially at hight bit-rates due to insufficient RX buffering. What is
your experience with that driver for the HI-311x?
Thanks,
Wolfga
From: Borislav Petkov
Hi,
here's the latest incarnation of the CEC collector. I think I've taken
care of all review comments but feel free to correct me here. The
introductory comment in cec.c should explain the whole deal - I'm
referring to there so that we have that text in the actual source a
On Wed, 8 Mar 2017, Bartosz Golaszewski wrote:
> Some users of irq_alloc_generic_chip() are modules which can be
> removed (e.g. gpio-ml-ioh) but have no means of freeing the allocated
> generic chip. Provide a function for that.
They have means, i.e. kfree(gc). If you want a wrapper for that the
On Thu, Mar 9, 2017 at 10:58 AM, Nikolay Borisov
wrote:
>
>
> On 9.03.2017 11:46, Andrey Ryabinin wrote:
>> On 03/08/2017 11:10 AM, Nikolay Borisov wrote:
>>
>>>
>>> So apparently this is indeed a false positive, resulting from using the old
>>> compiler. I used the attached patch to verify it.
>
Bart,
On Wed, 8 Mar 2017, Bart Van Assche wrote:
> Sorry but the cpuhp_issue_call() still occurs with Linus' latest tree
> (commit ec3b93ae0bf4 / Merge branch 'x86-urgent-for-linus' of
> git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip).
>
> This morning I discovered that the hang only occu
Acked-by: Niklas Cassel
On 03/09/2017 07:39 AM, Kishon Vijay Abraham I wrote:
> Populate cpu_addr_fixup ops to extract the least 28 bits of the
> corresponding cpu address.
>
> Cc: Niklas Cassel
> Acked-by: Joao Pinto
> Signed-off-by: Kishon Vijay Abraham I
> ---
> drivers/pci/dwc/pcie-artpec
Check this thread:
https://groups.google.com/forum/#!msg/syzkaller/ty5IhaYWVp8/aTN_hZ8qBQAJ
On Thu, Mar 9, 2017 at 11:24 AM, Jeremy Huang wrote:
> Hello,
>
> Syzkaller fuzzer started crashing kernel with the following panics:
>
> R13: R14: 7ff12df759c0 R15: 7ff12df75700
>
Hello everyone,
Thanks to Chen-Yu's review [1], a first version of this patchset to
clean-up my sun8i A33 audio driver has been sent and merged.
One patch [2] needs a rework so this cover-letter is for its V2.
Changes with v1:
- Remove patches 01, 02 and 03 as they are merged in asoc/for-
On Thu, Mar 09, 2017 at 06:05:23PM +0800, Chen-Yu Tsai wrote:
> Hi Maxime,
>
> This is part 3 of my sun4i drm clean up series. In this part support
> for 2 display pipelines is added, after some more code cleanups and
> restructuring.
>
> While this series enables the second display pipeline, the
Hello,
Syzkaller fuzzer started crashing kernel with the following panics:
R13: R14: 7ff12df759c0 R15: 7ff12df75700
Kernel panic - not syncing: Couldn't open N_TTY ldisc for ptm0 --- error -12.
CPU: 1 PID: 32595 Comm: syz-executor0 Not tainted 4.11.0-rc1-next-20170308 #2
Am 08.03.2017 um 19:03 schrieb Paolo Bonzini:
> Large pages at the PDPE level can be emulated by the MMU, so the bit
> can be set unconditionally in the EPT capabilities MSR. The same is
> true of 2MB EPT pages, though all Intel processors with EPT in practice
> support those.
>
> Signed-off-by:
From: Borislav Petkov
We call it everywhere "struct mce *m". Adjust that here too to avoid
confusion.
No functionality change.
Signed-off-by: Borislav Petkov
---
arch/x86/kernel/cpu/mcheck/mce.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/x86/kernel/cpu/mc
> -Original Message-
> From: Baolin Wang [mailto:baolin.w...@linaro.org]
> Sent: Thursday, March 09, 2017 2:11 PM
> To: Jun Li
> Cc: NeilBrown ; Felipe Balbi ; Greg KH
> ; Sebastian Reichel ; Dmitry
> Eremin-Solenikov ; David Woodhouse
> ; r...@kernel.org; Marek Szyprowski
> ; Ruslan Bil
On Tue, Mar 7, 2017 at 6:34 AM, Icenowy Zheng wrote:
> Allwinner H3/V3s/A64 SoCs have a special USB PHY0 that can route to two
> controllers: one is MUSB and the other is a EHCI/OHCI pair.
>
> When it's routed to EHCI/OHCI pair, it will needs a "pmu0" regs to
> tweak, like other EHCI/OHCI pairs in
Signed-off-by: Neil Armstrong
---
arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
index 2d8dc6f..06d70bf 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
+++ b
Signed-off-by: Neil Armstrong
---
arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
index 06d70bf..a010ab9 100644
--- a/arch/arm64/bo
This patchset is a first round of update to the meson clock controllers
to bring audio support. The patchset is based on clk-next. It could be
rebased on amlogic tree later on, if you prefer the patches to go through
Kevin's tree.
First patch fix an issue found while writing patch 5 (Giving ternar
parameter val is not enclosed in parenthesis which is buggy when given an
expression instead of a simple value
Signed-off-by: Jerome Brunet
Reviewed-by: Kevin Hilman
---
drivers/clk/meson/clkc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/meson/clkc.h b/drive
Signed-off-by: Neil Armstrong
---
arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 24
arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 43 ++---
arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 8 ++
3 files changed, 40 insertions(+), 35 deletions(-)
diff --
[now with LKML on cc...]
Hi Thomas,
Here's a handful of updates for both irqchip and irqdomain. Nothing
really stands out, except for the Qualcomm erratum workaround.
Please pull.
Thanks,
M.
The following changes since commit c1ae3cfa0e89fa1a7ecc4c99031f5e9ae99d9201:
Linux 4.11-rc1
On 2017/3/8 6:13, Jaegeuk Kim wrote:
> This patch uses __set{__clear}_bit_le for highter speed.
>
> Signed-off-by: Jaegeuk Kim
Reviewed-by: Chao Yu
2017-03-09 11:17 GMT+01:00 Thomas Gleixner :
> On Wed, 8 Mar 2017, Bartosz Golaszewski wrote:
>
>> Some users of irq_alloc_generic_chip() are modules which can be
>> removed (e.g. gpio-ml-ioh) but have no means of freeing the allocated
>> generic chip. Provide a function for that.
>
> They have mea
Hi,
On 09-03-17 10:59, Jean Delvare wrote:
Hi Hans,
On ven., 2017-03-03 at 15:27 +0100, Hans de Goede wrote:
On 03-03-17 10:24, Jean Delvare wrote:
On Sat, 25 Feb 2017 18:23:55 +0100, Hans de Goede wrote:
1) Rather then add cmdline options for all things which can be DMI quirked
and thus may
Use read/write operations for the mpll clocks instead of the
read-only ones.
Signed-off-by: Jerome Brunet
---
drivers/clk/meson/gxbb.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c
index 79fb8989f8dd..5059c7bbdbb3 10
Am 08.03.2017 um 19:03 schrieb Paolo Bonzini:
> handle_ept_violation is checking for "guest-linear-address invalid" +
> "paging-structure walk", which is a sign of a bug in KVM. However,
> _all_ EPT violations without a valid guest linear address are paging
> structure walks, because those EPT vio
Am 09.03.2017 um 11:43 schrieb David Hildenbrand:
> Am 08.03.2017 um 19:03 schrieb Paolo Bonzini:
>> handle_ept_violation is checking for "guest-linear-address invalid" +
>> "paging-structure walk", which is a sign of a bug in KVM. However,
>> _all_ EPT violations without a valid guest linear addr
Reported-by: Stephen Boyd
Signed-off-by: Jerome Brunet
---
drivers/clk/meson/gxbb.c| 2 +-
drivers/clk/meson/meson8b.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c
index 1c1ec137a3cc..c063287bb0ed 100644
--- a/driv
On Wed, 2017-03-08 at 08:17 -0500, Brian Foster wrote:
> On Tue, Mar 07, 2017 at 10:01:04PM +0530, Abdul Haleem wrote:
> >
> > Hi,
> >
> > Today's mainline (4.11.0-rc1) booted with warnings on Power7 LPAR.
> >
> > Issue is not reproducible all the time.
> >
> > traces:
> >
> > Found de
Hi!
> > > - CONFIG_FUNCTION_GRAPH_TRACER sets it on x86-32 because of a gcc bug
> > > where the stack gets aligned before the mcount call. This issue
> > > should be mostly obsolete as most modern compilers now have -mfentry.
> > > We could make it dependent on CC_USING_FENTRY.
> >
> > Yea
Until now, there was only 1 divider and 1 mux declared for the meson8b
platform. With the ongoing work on various system, including audio, this
is about to change. Use the same approach as gates for dividers and muxes,
putting them in tables to fix the register address at runtime.
Signed-off-by: J
Signed-off-by: Jerome Brunet
---
drivers/clk/meson/meson8b.c | 103
drivers/clk/meson/meson8b.h | 20 -
2 files changed, 122 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c
index 2937443d450
Until now, there was only 2 dividers and 2 muxes declared for the gxbb
platform. With the ongoing work on various subsystem, including audio,
this is about to change. Use the same approach as gates for dividers and
muxes, putting them in tables to fix the register address at runtime.
Signed-off-by
Gxbb datasheet says N2 maximum value is 127 but the register field is
9 bits wide, the maximum value should 511.
Test shows value greater than 127, all the way to 511, works well
Signed-off-by: Jerome Brunet
---
drivers/clk/meson/clk-mpll.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Signed-off-by: Jerome Brunet
---
drivers/clk/meson/gxbb.h | 10 +-
include/dt-bindings/clock/gxbb-clkc.h | 5 +
2 files changed, 10 insertions(+), 5 deletions(-)
diff --git a/drivers/clk/meson/gxbb.h b/drivers/clk/meson/gxbb.h
index 8ee2022ce5d5..274f58764853 100644
---
On Thu, 2017-03-09 at 10:04 +0100, Jan Kara wrote:
> On Wed 08-03-17 21:57:25, Ted Tso wrote:
> > On Tue, Mar 07, 2017 at 11:26:22AM +0100, Jan Kara wrote:
> > > On a more general note (DAX is actually fine here), I find the current
> > > practice of clearing page dirty bits on error and reporting
Hi,
On Thu, Mar 09, 2017 at 06:05:32PM +0800, Chen-Yu Tsai wrote:
> Some Allwinner SoCs have two display pipelines (frontend -> backend ->
> tcon).
>
> Previously we only supported one pipeline. This patch extends the
> current driver to support two. It extends the tcon and backend pointers
> in
Since we know the GXBBB and GXL/GXM share more hardware, we can safely move
the remaining peripheral nodes present in the GXBB dtsi to the common GX dtsi.
The following patches are small cleanups and helps to uniform the GX common
dtsi compatible scheme.
Neil Armstrong (3):
ARM64: dts: meson-gx:
This patch adds new callbacks to the meson-mpll driver to control
and set the pll rate. For this, we also need to add the enable bit and
sdm enable bit. The corresponding parameters are added to mpll data
structure.
Signed-off-by: Jerome Brunet
---
drivers/clk/meson/clk-mpll.c | 152
From: Tony Luck
Move all code relating to /dev/mcelog to a separate source file.
/dev/mcelog driver can now operate from the machine check notifier with
lowest prio.
Boris:
* Move the mce_helper and trigger functionality behind
CONFIG_X86_MCELOG.
Signed-off-by: Tony Luck
Signed-off-by: Borisla
From: Borislav Petkov
It is confusing when staring at "struct mce_log mcelog" and then there's
also a function called mce_log(). So call the buffer what it is.
No functionality change.
Signed-off-by: Borislav Petkov
---
arch/x86/include/asm/mce.h | 2 +-
arch/x86/kernel/cpu/mcheck/mce.
From: Borislav Petkov
A simple data structure for collecting correctable errors along with
accessors. More detailed description in the code itself.
The error decoding is done with the decoding chain now and
mce_first_notifier() gets to see the error first and the CEC decides
whether to log it an
On Wed, Mar 08, 2017 at 11:51:39AM +0800, Chen-Yu Tsai wrote:
> On Tue, Mar 7, 2017 at 4:56 PM, Maxime Ripard
> wrote:
> > Even though that mux is undocumented, it seems like it needs to be set to 1
> > when using composite, and 0 when using HDMI.
> >
> > Signed-off-by: Maxime Ripard
> > ---
> >
Hi Songjun,
On 08/03/17 03:25, Wu, Songjun wrote:
> Hi Colin,
>
> Thank you for your comment.
> It is a bug, will be fixed in the next patch.
Do you mean that you will provide a new patch for this? Is there anything
wrong with this patch? It seems reasonable to me.
Regards,
Hans
>
>
On Wed, Mar 08, 2017 at 01:36:43AM +0800, Icenowy Zheng wrote:
>
>
> 08.03.2017, 01:07, "Maxime Ripard" :
> > Hi,
> >
> > On Tue, Mar 07, 2017 at 01:17:44AM +0800, Icenowy Zheng wrote:
> >> Allwinner H5 is a 64-bit SoC with a design like the 32-bit
> >> H3, and it's pin-to-pin compatible with H
On Thu 2017-03-09 10:38:46, Geert Uytterhoeven wrote:
> Hi Pavel,
>
> On Wed, Mar 8, 2017 at 10:22 PM, Pavel Machek wrote:
> > Well, I have fast CPUs, but most of the time they just compile
> > stuff. Especially bisect is compile-heavy. I suspect going back to
> > gcc-3.2 would bring me bigger ad
On 03/03/17 06:00, Leo Yan wrote:
> This is refactor to add function of_coresight_get_cpu(), so it's used to
> retrieve CPU id for coresight component. Finally can use it as a common
> function for multiple places.
>
> Suggested-by: Mathieu Poirier
> Signed-off-by: Leo Yan
> ---
> drivers/hwtrac
On Wed, 8 Mar 2017, David Carrillo-Cisneros wrote:
> On Wed, Mar 8, 2017 at 12:30 AM, Thomas Gleixner wrote:
> > Same applies for per CPU measurements.
>
> For CPU measurements. We need perf-like CPU filtering to support tools
> that perform low overhead monitoring by polling CPU events. These
>
On Thu 09-03-17 05:47:51, Jeff Layton wrote:
> On Thu, 2017-03-09 at 10:04 +0100, Jan Kara wrote:
> > On Wed 08-03-17 21:57:25, Ted Tso wrote:
> > > On Tue, Mar 07, 2017 at 11:26:22AM +0100, Jan Kara wrote:
> > > > On a more general note (DAX is actually fine here), I find the current
> > > > pract
From: Hua Jing
- Add a new compatible string for the Armada 3700 SoCs
- add sbuscfg support for orion usb controller driver. For the SoCs
without hlock, need to program BAWR/BARD/AHBBRST fields in the sbuscfg
register to guarantee the AHB master's burst would not overrun or
underrun the FI
Armada 37xx SoC embedded an EHCI controller. This patch adds the device
tree node enabling its support.
Signed-off-by: Gregory CLEMENT
---
arch/arm64/boot/dts/marvell/armada-3720-db.dts | 6 ++
arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 7 +++
2 files changed, 13 insertions(+)
dif
On Thu 09 Mar 10:07 CET 2017, Vivek Gautam wrote:
[..]
> + phy@34000 {
> + compatible = "qcom,msm8996-qmp-pcie-phy";
> + reg = <0x034000 0x488>;
Drop the leading 0 from the address.
> + #clock-cells = <1>;
> + #address-cells = <1>;
> +
1;4601;0c
On Wed, Mar 08, 2017 at 11:35:39AM +0800, Chen-Yu Tsai wrote:
> Hi,
>
> On Tue, Mar 7, 2017 at 4:56 PM, Maxime Ripard
> wrote:
> > The A10s has an HDMI controller connected to the second TCON channel. Add
> > it to our DT.
> >
> > Signed-off-by: Maxime Ripard
> > ---
> > arch/arm/boot
The mvebu ARM64 SoCs no longer select PLAT_ORION. However Armada 37xx use
the Orion EHCI controller. This patch allows the Orion EHCI driver to be
built when ARCH_MVEBU is selected.
Signed-off-by: Gregory CLEMENT
---
drivers/usb/host/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
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