Remove a CPU from the affinity mask when it goes offline and add it
back when it returns. In case the vetor was assigned only to the CPU
going offline it will be shutdown and re-started when the CPU
reappears.
Signed-off-by: Christoph Hellwig
---
arch/x86/kernel/irq.c | 3 +-
include/lin
Hi all,
this series changes our automatic MSI-X vector assignment so that it
takes all present CPUs into account instead of all online ones. This
allows to better deal with cpu hotplug events, which could happen
frequently due to power management for example.
Currently we only assign spread vectors to online CPUs, which ties the
IRQ mapping to the currently online devices and doesn't deal nicely with
the fact that CPUs could come and go rapidly due to e.g. power management.
Instead assign vectors to all present CPUs to avoid this churn.
Signed-off-by:
This will allow us to spread MSI/MSI-X affinity over all present CPUs and
thus better deal with systems where cpus are take on and offline all the
time.
Signed-off-by: Christoph Hellwig
---
kernel/irq/manage.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/kernel/irq
Currently we only create hctx for online CPUs, which can lead to a lot
of churn due to frequent soft offline / online operations. Instead
allocate one for each present CPU to avoid this and dramatically simplify
the code.
Signed-off-by: Christoph Hellwig
---
block/blk-mq-sysfs.c | 26 +++
Unlike most drіvers that simply pass the maximum possible vectors to
pci_alloc_irq_vectors NVMe needs to configure the device before allocting
the vectors, so it needs a manual update for the new scheme of using
all present CPUs.
Signed-off-by: Christoph Hellwig
---
drivers/nvme/host/pci.c | 2 +
This way we get a nice distribution independent of the current cpu
online / offline state.
Signed-off-by: Christoph Hellwig
---
block/blk-mq-cpumap.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/block/blk-mq-cpumap.c b/block/blk-mq-cpumap.c
index 8e61e8640e17..5eaecd4
The IRQFD framework calls the architecture dependent function
twice if the corresponding GSI type is edge triggered. For ARM,
the function kvm_set_msi() is getting called twice whenever the
IRQFD receives the event signal. The rest of the code path is
trying to inject the MSI without any validation
Hello,
On Wednesday 01 Feb 2017 16:19:27 Steve Longerbeam wrote:
> On 02/01/2017 01:30 AM, Philipp Zabel wrote:
> > On Tue, 2017-01-31 at 17:26 -0800, Steve Longerbeam wrote:
> > [...]
> >
> >>> # Set pad formats
> >>> media-ctl --set-v4l2 "'tc358743 1-000f':0[fmt:UYVY/1920x1080]"
> >>> media-ctl
On Fri 03-02-17 19:57:39, Tetsuo Handa wrote:
> Michal Hocko wrote:
> > On Mon 30-01-17 09:55:46, Michal Hocko wrote:
> > > On Sun 29-01-17 00:27:27, Tetsuo Handa wrote:
> > [...]
> > > > Regarding [1], it helped avoiding the too_many_isolated() issue. I can't
> > > > tell whether it has any negati
On 17/02/03 (金) 17:07, Fredrik Markstrom wrote:
On Tue, 31 Jan 2017 17:27:09 +0100 Eric Dumazet
wrote
> On Tue, 2017-01-31 at 14:32 +0100, Fredrik Markstrom wrote:
> > On Thu, 19 Jan 2017 19:53:47 +0100 Eric Dumazet
wrote
> > > On Thu, 2017-01-19 at 17:41 +0100, Fred
On Thu 02-02-17 18:28:02, Al Viro wrote:
> On Thu, Feb 02, 2017 at 03:48:17PM +0100, Jan Kara wrote:
>
> > > * ->page_mkwrite() instances sometimes return VM_FAULT_RETRY; AFAICS,
> > > it's only (ab)used there as 'not zero, but doesn't contain any error
> > > bits';
> > > VM_FAULT_RETRY from th
On Fri, Feb 3, 2017 at 10:40 PM, Steven Rostedt wrote:
> From: "Steven Rostedt (VMware)"
>
> fgd->hash is saved and then freed, but is never reset to either
> ftrace_graph_hash nor ftrace_graph_notrace_hash. But if multiple reads are
> performed, then the freed hash could be accessed again.
Argh
On 1/18/2017 7:54 AM, Hanjun Guo wrote:
> From: Hanjun Guo
>
> With platform msi support landed in the kernel, and the introduction
> of IORT for GICv3 ITS (PCI MSI) and SMMU, the framework for platform msi
> is ready, this patch set add few patches to enable the ACPI platform
> msi support.
>
>
[Let's CC more xfs people]
On Fri 03-02-17 19:57:39, Tetsuo Handa wrote:
[...]
> (1) I got an assertion failure.
I suspect this is a result of
http://lkml.kernel.org/r/20170201092706.9966-2-mho...@kernel.org
I have no idea what the assert means though.
>
> [ 969.626518] Killed process 6262 (oo
WARNING: Symbolic permissions 'S_IRUGO' are not preferred.
Consider using octal permissions '0444'.
This warning was detected by checkpatch.pl for hdm_i2c.c.
Signed-off-by: Zhengyi Shen
---
drivers/staging/most/hdm-i2c/hdm_i2c.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a
[CC Petr]
On Fri 03-02-17 19:57:39, Tetsuo Handa wrote:
[...]
> (2) I got a lockdep warning. (A new false positive?)
Yes, I suspect this is a false possitive. I do not see how we can
deadlock. __alloc_pages_direct_reclaim calls drain_all_pages(NULL) which
means that a potential recursion to the p
On Fri, 3 Feb 2017 23:49:38 +0900
Namhyung Kim wrote:
> On Fri, Feb 3, 2017 at 10:40 PM, Steven Rostedt wrote:
> > From: "Steven Rostedt (VMware)"
> >
> > fgd->hash is saved and then freed, but is never reset to either
> > ftrace_graph_hash nor ftrace_graph_notrace_hash. But if multiple reads a
On Fri, 3 Feb 2017 23:26:46 +0900
Namhyung Kim wrote:
> Hi Steve,
>
> On Fri, Feb 3, 2017 at 10:40 PM, Steven Rostedt wrote:
> > From: "Steven Rostedt (VMware)"
> >
> > This is a micro-optimization, but as it has to deal with a fast path of the
> > function tracer, these optimizations can be n
On Fri 03-02-17 10:56:42, vinayak menon wrote:
> On Thu, Feb 2, 2017 at 9:31 PM, Michal Hocko wrote:
> >
> > Why would you like to chose and kill a task when the slab reclaim can
> > still make sufficient progres? Are you sure that the slab contribution
> > to the stats makes all the above happeni
On Thu, 2017-02-02 at 15:12 +0100, Benjamin Tissoires wrote:
> + case POWER_SUPPLY_PROP_MANUFACTURER:
> + val->strval = "Logitech, Inc.";
I don't like this change. I'd prefer the concatenated manufacturer and
model strings leading to user-friendly strings, and "
On Fri, Feb 03, 2017 at 01:40:21PM +0200, Andy Shevchenko wrote:
> On Thu, 2017-02-02 at 17:41 -0800, Dmitry Torokhov wrote:
> > There is no reason why statically defined properties should be
> > modifiable,
> > so let's make device_add_properties() and the rest of pset_*()
> > functions to
> > tak
[+cc Mika, linux-kernel]
On Thu, Feb 02, 2017 at 08:11:48PM -0800, Yinghai Lu wrote:
> 4.9 is working,
> ...
> After reverting
>
> From 68db9bc814362e7f24371c27d12a4f34477d9356 Mon Sep 17 00:00:00 2001
> From: Lukas Wunner
> Date: Fri, 28 Oct 2016 10:52:06 +0200
> Subject: PCI: pciehp: Add run
On 03/02/17 14:50, Sinan Kaya wrote:
> On 1/18/2017 7:54 AM, Hanjun Guo wrote:
>> From: Hanjun Guo
>>
>> With platform msi support landed in the kernel, and the introduction
>> of IORT for GICv3 ITS (PCI MSI) and SMMU, the framework for platform msi
>> is ready, this patch set add few patches to e
On Fri, Feb 03, 2017 at 04:48:14PM +0530, Amit Shah wrote:
> I'm leaving my job at Red Hat, this email address will stop working next week.
> Update it to one that I will have access to later.
>
> Signed-off-by: Amit Shah
It's great that we'll still have you around! Do you want to send a pull
r
On Fri, Feb 03, 2017 at 01:43:03PM +0200, Andy Shevchenko wrote:
> On Thu, 2017-02-02 at 17:41 -0800, Dmitry Torokhov wrote:
> > Data that is fed into property arrays should not be modified, so let's
> > mark
> > relevant pointers as const. This will allow us making source arrays as
> > const/__ini
On 17.01.17 19:16:56, Will Deacon wrote:
> I can't really see the trend given that, for system time, your
> pfn_valid_within results have a variance of ~9 and the early_pfn_valid
> results have a variance of ~92. Given that the variance seems to come
> about due to the reboots, I think we need more
On Fri, Feb 3, 2017 at 10:40 PM, Steven Rostedt wrote:
> git://git.kernel.org/pub/scm/linux/kernel/git/rostedt/linux-trace.git
> for-next
>
> Head SHA1: 092adb1121aec9e0dfa2d07bc160ae60831f4798
>
>
> Steven Rostedt (VMware) (8):
> tracing: Add ftrace_hash_key() helper function
> ftra
On Fri 03-02-17 15:42:55, Hillf Danton wrote:
>
> On February 03, 2017 3:20 AM Johannes Weiner wrote:
> > @@ -1063,7 +1063,7 @@ static unsigned long shrink_page_list(struct
> > list_head *page_list,
> > PageReclaim(page) &&
> > test_bit(PGDAT_WRITE
From: Corentin Labbe
Date: Fri, 3 Feb 2017 14:41:45 +0100
> On Tue, Jan 31, 2017 at 11:12:25PM -0500, David Miller wrote:
>> From: Corentin Labbe
>> Date: Tue, 31 Jan 2017 10:11:48 +0100
>>
>> > The stmmac driver run TX completion under NAPI but without checking
>> > the work done by the TX com
On Fri, Feb 03, 2017 at 01:45:30PM +0200, Andy Shevchenko wrote:
> On Thu, 2017-02-02 at 17:41 -0800, Dmitry Torokhov wrote:
> > When augmenting ACPI-enumerated devices with additional property data
> > based
> > on DMI info, a module has often several potential property sets, with
> > only
> > one
Hi,
Laurent Vivier wrote,
> Le 03/02/2017 à 01:35, John Paul Adrian Glaubitz a écrit :
> > On 02/03/2017 01:10 AM, Greg Ungerer wrote:
> >> This is a limitation in the FEC support in QEMU.
> >> This works on real ColdFire hardware (which do support the
> >> FEC MIB stats registers from offset 0x20
From: Joerg Roedel
Also add the smmu devices to sysfs.
Signed-off-by: Joerg Roedel
---
drivers/iommu/arm-smmu-v3.c | 20 +++-
drivers/iommu/arm-smmu.c| 29 +
2 files changed, 48 insertions(+), 1 deletion(-)
diff --git a/drivers/iommu/arm-smmu-v3
From: Joerg Roedel
The struct is used to link devices to iommu-groups, so
'struct group_device' is a better name. Further this makes
the name iommu_device available for a struct representing
hardware iommus.
Signed-off-by: Joerg Roedel
---
drivers/iommu/iommu.c | 10 +-
1 file changed,
Em Fri, Feb 03, 2017 at 03:56:42PM +0530, Ravi Bangoria escreveu:
> After patch:
> $ perf record -a -e sdt_glib:idle__add
> event syntax error: 'sdt_glib:idle__add'
> \___ unknown tracepoint
>
> Error: File /sys/kernel/debug/tracing/events/sdt_glib/idle__add not
From: Joerg Roedel
Rename the function to iommu_ops_from_fwnode(), because that
is what the function actually does. The new name is much
more descriptive about what the function does.
Signed-off-by: Joerg Roedel
---
drivers/acpi/arm64/iort.c | 2 +-
drivers/iommu/iommu.c | 2 +-
include/li
Hi,
the IOMMU core code already has two ways of representing
individual hardware IOMMUs. One is the sysfs code and the
other is the newer iommu_register_instance interface. These
two interfaces are special purpose and can be unified.
This unification is attempted in this patch-set. It
introduces
From: Joerg Roedel
And also move its remaining functionality to
iommu_device_register() and 'struct iommu_device'.
Cc: Rob Herring
Cc: Frank Rowand
Cc: Matthias Brugger
Cc: Marek Szyprowski
Cc: devicet...@vger.kernel.org
Cc: linux-arm-ker...@lists.infradead.org
Signed-off-by: Joerg Roedel
-
From: Joerg Roedel
Register Exynos IOMMUs to the IOMMU core and make them
visible in sysfs. This patch does not add the links between
IOMMUs and translated devices yet.
Cc: Marek Szyprowski
Cc: linux-arm-ker...@lists.infradead.org
Cc: linux-samsung-...@vger.kernel.org
Signed-off-by: Joerg Roede
The ARM architecture defines the EL1 physical timer and the virtual timer,
and it is reasonable for an OS to expect to be able to access both.
However, the current KVM implementation does not provide the EL1 physical
timer to VMs but terminates VMs on access to the timer.
This patch series enables
From: Joerg Roedel
Register individual Mediatek IOMMUs to the iommu core and
add sysfs entries.
Cc: Matthias Brugger
Cc: linux-arm-ker...@lists.infradead.org
Cc: linux-media...@lists.infradead.org
Signed-off-by: Joerg Roedel
---
drivers/iommu/mtk_iommu.c | 26 ++
drive
Set a background timer for the EL1 physical timer emulation while VMs
are running, so that VMs get the physical timer interrupts in a timely
manner.
Schedule the background timer on entry to the VM and cancel it on exit.
This would not have any performance impact to the guest OSes that
currently u
Add the EL1 physical timer context.
Signed-off-by: Jintack Lim
Acked-by: Christoffer Dall
---
include/kvm/arm_arch_timer.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/kvm/arm_arch_timer.h b/include/kvm/arm_arch_timer.h
index f46fa3b..6445a3d 100644
--- a/include/kvm/arm_arch_t
KVM traps on the EL1 phys timer accesses from VMs, but it doesn't handle
those traps. This results in terminating VMs. Instead, set a handler for
the EL1 phys timer access, and inject an undefined exception as an
intermediate step.
Signed-off-by: Jintack Lim
Reviewed-by: Christoffer Dall
---
ar
When scheduling a background timer, consider both of the virtual and
physical timer and pick the earliest expiration time.
Signed-off-by: Jintack Lim
Reviewed-by: Christoffer Dall
---
arch/arm/kvm/arm.c| 3 ++-
virt/kvm/arm/arch_timer.c | 53 +++-
Abstract virtual timer context into a separate structure and change all
callers referring to timer registers, irq state and so on. No change in
functionality.
This is about to become very handy when adding the EL1 physical timer.
Signed-off-by: Jintack Lim
Acked-by: Christoffer Dall
Acked-by: M
Make cntvoff per each timer context. This is helpful to abstract kvm
timer functions to work with timer context without considering timer
types (e.g. physical timer or virtual timer).
This also would pave the way for ever doing adjustments of the cntvoff
on a per-CPU basis if that should ever make
Initialize the emulated EL1 physical timer with the default irq number.
Signed-off-by: Jintack Lim
Reviewed-by: Christoffer Dall
---
arch/arm/kvm/reset.c | 9 -
arch/arm64/kvm/reset.c | 9 -
include/kvm/arm_arch_timer.h | 3 ++-
virt/kvm/arm/arch_timer.c| 9 +++
Now that we have a separate structure for timer context, make functions
generic so that they can work with any timer context, not just the
virtual timer context. This does not change the virtual timer
functionality.
Signed-off-by: Jintack Lim
Acked-by: Marc Zyngier
Acked-by: Christoffer Dall
-
Le 03/02/2017 à 16:17, Waldemar Brodkorb a écrit :
> Hi,
> Laurent Vivier wrote,
>
>> Le 03/02/2017 à 01:35, John Paul Adrian Glaubitz a écrit :
>>> On 02/03/2017 01:10 AM, Greg Ungerer wrote:
This is a limitation in the FEC support in QEMU.
This works on real ColdFire hardware (which do
From: Joerg Roedel
There is currently support for iommu sysfs bindings, but
those need to be implemented in the IOMMU drivers. Add a
more generic version of this by adding a struct device to
struct iommu_device and use that for the sysfs bindings.
Also convert the AMD and Intel IOMMU driver to m
From: Joerg Roedel
This struct represents one hardware iommu in the iommu core
code. For now it only has the iommu-ops associated with it,
but that will be extended soon.
The register/unregister interface is also added, as well as
making use of it in the Intel and AMD IOMMU drivers.
Signed-off-
From: Joerg Roedel
Register the MSM IOMMUs to the iommu core and add sysfs
entries for that driver.
Signed-off-by: Joerg Roedel
---
drivers/iommu/msm_iommu.c | 73 +++
drivers/iommu/msm_iommu.h | 3 ++
2 files changed, 76 insertions(+)
diff --git a
The "opp_high" property brings support for 1.5 GHz CPU frequency for TI's
am57xx line of processors.
Signed-off-by: Lukasz Majewski
---
arch/arm/boot/dts/dra7.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index a860a56..5e
The "operating-points" property have been replaced with
"operating-points-v2". Only entries with the same frequencies have
been added, so no reqression should be introduced.
Signed-off-by: Lukasz Majewski
---
arch/arm/boot/dts/dra7.dtsi | 22 +-
1 file changed, 17 insertions(
On Tue 24-01-17 21:48:35, Fabian Frederick wrote:
> "out" label was only returning error code.
>
> Signed-off-by: Fabian Frederick
Thanks. I've taken this patch and squashed patch 3 into this one.
Honza
> ---
> fs/udf/file.c | 39
On Tue 24-01-17 21:48:34, Fabian Frederick wrote:
> Currently, lsattr for instance in udf directory gives
> "udf: Invalid argument While reading flags on ..."
>
> This patch returns -ENOIOCTLCMD
> when command is unknown to have more accurate message like this:
> "Inappropriate ioctl for device Wh
Emulate read and write operations to CNTP_TVAL, CNTP_CVAL and CNTP_CTL.
Now VMs are able to use the EL1 physical timer.
Signed-off-by: Jintack Lim
Reviewed-by: Christoffer Dall
---
arch/arm64/kvm/sys_regs.c| 37 ++---
include/kvm/arm_arch_timer.h | 2 ++
vir
Now that we maintain the EL1 physical timer register states of VMs,
update the physical timer interrupt level along with the virtual one.
Signed-off-by: Jintack Lim
Acked-by: Christoffer Dall
---
virt/kvm/arm/arch_timer.c | 4
1 file changed, 4 insertions(+)
diff --git a/virt/kvm/arm/arch
tree: https://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git
WIP.sched/core
head: 9a631ea4bdc4d7a7faabc4a98d632f39573a9a8d
commit: 9a631ea4bdc4d7a7faabc4a98d632f39573a9a8d [133/133] sched/headers: Split
out of
config: sh-titan_defconfig (attached as .config)
compiler: sh4-linux-gnu-gcc
On 2/3/2017 10:11 AM, Marc Zyngier wrote:
> On 03/02/17 14:50, Sinan Kaya wrote:
>> On 1/18/2017 7:54 AM, Hanjun Guo wrote:
>>> From: Hanjun Guo
>>>
>>> With platform msi support landed in the kernel, and the introduction
>>> of IORT for GICv3 ITS (PCI MSI) and SMMU, the framework for platform msi
From: Joerg Roedel
This makes the interface more consistent with
iommu_device_sysfs_add/remove.
Signed-off-by: Joerg Roedel
---
drivers/iommu/amd_iommu.c | 4 ++--
drivers/iommu/intel-iommu.c | 4 ++--
drivers/iommu/iommu-sysfs.c | 16
include/linux/iommu.h | 4 ++--
Using virtually mapped stack, kernel stacks are allocated via vmalloc.
In the current implementation, two stacks per cpu can be cached when
tasks are freed and the cached stacks are used again in task duplications.
but the array for the cached stacks is statically allocated by per-cpu api.
In thi
when a cpu is up, predefined number of stacks are allocated and cached
immediately.
Signed-off-by: Hoeun Ryu
---
kernel/fork.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/kernel/fork.c b/kernel/fork.c
index 50de6cf..ee4067d 100644
--- a/kernel/fork.c
+++ b/kernel/fork.c
On Sat 04-02-17 00:30:05, Hoeun Ryu wrote:
> Using virtually mapped stack, kernel stacks are allocated via vmalloc.
> In the current implementation, two stacks per cpu can be cached when
> tasks are freed and the cached stacks are used again in task duplications.
> but the array for the cached sta
Introducing NR_VMAP_STACK_CACHE, the number of cached stacks for virtually
mapped kernel stack can be configurable using Kbuild system.
default value is 2.
Signed-off-by: Hoeun Ryu
---
arch/Kconfig | 8
kernel/fork.c | 2 +-
2 files changed, 9 insertions(+), 1 deletion(-)
diff --git a
On (Fri) 03 Feb 2017 [17:11:49], Michael S. Tsirkin wrote:
> On Fri, Feb 03, 2017 at 04:48:14PM +0530, Amit Shah wrote:
> > I'm leaving my job at Red Hat, this email address will stop working next
> > week.
> > Update it to one that I will have access to later.
> >
> > Signed-off-by: Amit Shah
>
On Mon 30-01-17 09:12:10, Michal Hocko wrote:
> On Fri 27-01-17 11:40:42, Theodore Ts'o wrote:
> > On Fri, Jan 27, 2017 at 10:37:35AM +0100, Michal Hocko wrote:
> > > If this ever turn out to be a problem and with the vmapped stacks we
> > > have good chances to get a proper stack traces on a poten
On Fri, Feb 03, 2017 at 02:37:48PM +0100, Peter Zijlstra wrote:
> On Fri, Feb 03, 2017 at 01:59:34PM +0100, Mike Galbraith wrote:
> > On Fri, 2017-02-03 at 09:53 +0100, Peter Zijlstra wrote:
> > > On Fri, Feb 03, 2017 at 10:03:14AM +0530, Sachin Sant wrote:
> >
> > > > I ran few cycles of cpu hot(
Hi All,
Changes from v1
o added change set from Valentin catching CONFIG issues
o added missing test_and_change_bit atomic bitops patch
This is mostly a resend since I didnt really get many comments on the
original patch series. This is in linux-next and the build infra has
pointed out some is
From: Stefan Kristiansson
Motivation for this is to be able to print the way information
properly in print_cpuinfo(), instead of hardcoding it to one.
Signed-off-by: Stefan Kristiansson
Signed-off-by: Jonas Bonn
[sho...@gmail.com fixed conflict with show_cpuinfo change]
Signed-off-by: Stafford
The generic memcpy routine provided in kernel does only byte copies.
Using word copies we can lower boot time and cycles spend in memcpy
quite significantly.
Booting on my de0 nano I see boot times go from 7.2 to 5.6 seconds.
The avg cycles in memcpy during boot go from 6467 to 1887.
I tested sev
From: Valentin Rothberg
The Kconfig option for OR12000 is OR1K_1200.
Signed-off-by: Valentin Rothberg
Signed-off-by: Stafford Horne
---
arch/openrisc/lib/memcpy.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/openrisc/lib/memcpy.c b/arch/openrisc/lib/memcpy.c
index
From: Stefan Kristiansson
Optimized version that make use of the l.lwa and l.swa atomic instruction
pair.
Most openrisc cores provide these instructions now, if not available
emulation is provided.
Signed-off-by: Stefan Kristiansson
[sho...@gmail.com: remove OPENRISC_HAVE_INST_LWA_SWA config su
On Fri, Feb 03, 2017 at 04:42:27PM +0800, zhouxianr...@huawei.com wrote:
> +static inline void zram_fill_page_partial(char *ptr, unsigned int size,
> + unsigned long value)
> +{
> + int i;
> + unsigned long *page;
> +
> + if (likely(value == 0)) {
> + memset(ptr,
From: Olof Kindgren
This adds a hand-optimized assembler version of memset and sets
__HAVE_ARCH_MEMSET to use this version instead of the generic C
routine
Signed-off-by: Olof Kindgren
Signed-off-by: Stafford Horne
---
arch/openrisc/include/asm/string.h | 7 +++
arch/openrisc/kernel/or32_ksy
From: Namhyung Kim
Commit 21e6d8428664 ("perf diff: Use perf_hpp__register_sort_field
interface") changed list_add() to perf_hpp__register_sort_field().
This resulted in a behavior change since the field was added to the tail
instead of the head. So the -o option is mostly ignored due to its
or
From: Krister Johansen
If dso__load_kcore frees all of the existing maps, but one has already
been attached to a callchain cursor node, then we can get a SIGSEGV in
any function that happens to try to use this invalid cursor. Use the
existing map refcount mechanism to forestall cleanup of a map
Cleanups to whitespace and add some comments. Reading through the delay
slot logic I noticed some things:
- Delay slot instructions were not indented
- Some comments are not lined up
- Use tabs and spaces consistent with other code
No functional change
Signed-off-by: Stafford Horne
---
arch/
The strings used during the head/init phase of openrisc bootup were
stored in the executable section of the binary.
This causes compilation to fail when using CONFIG_DEBUG_INFO with
error:
Error: unaligned opcodes detected in executable segment
Also, this patch removes unused strings.
Signed-of
Use execption SR stored in pt_regs for detection, the current SR is not
correct as the handler is running after return from exception.
Also, The code that checks for a delay slot uses a flag bitmask and then
wants to check if the result is not zero. The test it implemented was
wrong.
Correct it
The openrisc official repository and patch work happens currently on
github. Add the repo for reference.
Signed-off-by: Stafford Horne
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index c36976d..92000bf 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@
Openrisc stack pointer is managed by decrementing r1. Add regexes to
recognize this.
Signed-off-by: Stafford Horne
---
scripts/checkstack.pl | 3 +++
1 file changed, 3 insertions(+)
diff --git a/scripts/checkstack.pl b/scripts/checkstack.pl
index dd83978..eea5b78 100755
--- a/scripts/checkstack
From: Sebastian Macke
This patch adds basic support for the idle state of the cpu.
The patch overrides the regular idle function, enables the interupts,
checks for the power management unit and enables the cpu doze mode
if available.
Signed-off-by: Sebastian Macke
[sho...@gmail.com: Fixed check
From: Stefan Kristiansson
Heavily based on the ARM implementation, this adds
ticket spinlock support for OpenRISC.
Signed-off-by: Stefan Kristiansson
[sho...@gmail.com: fix tabs vs space checkpatch warning]
Signed-off-by: Stafford Horne
---
arch/openrisc/include/asm/spinlock.h | 232 +++
From: Sebastian Macke
The bits were swapped, as per spec and processor implementation the
power management present bit is 9 and PIC bit is 8. This patch brings
the definitions into spec.
Signed-off-by: Sebastian Macke
[sho...@gmail.com: Added commit body]
Signed-off-by: Stafford Horne
---
arc
From: Stefan Kristiansson
This causes the build to fail when building with the or1k-musl-linux-
toolchain and it is not needed.
Signed-off-by: Stafford Horne
---
arch/openrisc/kernel/ptrace.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/openrisc/kernel/ptrace.c b/arch/openrisc/kerne
This helps to suppress the vmlinux.lds file.
Signed-off-by: Stafford Horne
---
arch/openrisc/kernel/.gitignore | 1 +
1 file changed, 1 insertion(+)
create mode 100644 arch/openrisc/kernel/.gitignore
diff --git a/arch/openrisc/kernel/.gitignore b/arch/openrisc/kernel/.gitignore
new file mode 1
On 02/03/2017 02:02 AM, Stuart Yoder wrote:
>
>> -Original Message-
>> From: upstream-release-boun...@linux.freescale.net [mailto:upstream-release-
>> boun...@linux.freescale.net] On Behalf Of laurentiu.tu...@nxp.com
>> Sent: Wednesday, February 01, 2017 5:43 AM
>> To: gre...@linuxfoundat
From: Stefan Kristiansson
Using the l.lwa and l.swa atomic instruction pair.
Most openrisc processor cores provide these instructions now. If the
instructions are not available emulation is provided.
Signed-off-by: Stefan Kristiansson
[sho...@gmail.com: remove OPENRISC_HAVE_INST_LWA_SWA config
Hi Linus,
The following changes since commit 566cf877a1fcb6d6dc0126b076aad062054c2637:
Linux 4.10-rc6 (2017-01-29 14:25:17 -0800)
are available in the git repository at:
git://github.com/awilliam/linux-vfio.git tags/vfio-v4.10-rc7
for you to fetch changes up to 2da64d20a0b20046d688e44f4033
From: Stefan Kristiansson
Support for the futex_atomic_* operations by using the
load-link/store-conditional l.lwa/l.swa instructions.
Most openrisc cores provide these instructions now if not available,
emulation is provided.
Signed-off-by: Stefan Kristiansson
[sho...@gmail.com: remove OPENRIS
From: Stefan Kristiansson
This adds an emulation layer for implementations
that lack the l.lwa and l.swa instructions.
It handles these instructions both in kernel space and
user space.
Signed-off-by: Stefan Kristiansson
[sho...@gmail.com: Added delay slot pc adjust logic]
Signed-off-by: Staffo
On 2017-01-30 09:35:34 [-0800], Andy Ritger wrote:
> The problem is that various static inline functions such as
> reservation_object_fini() indirectly call mutex_destroy. On DEBUG_MUTEX
> kernels, mutex_destroy is EXPORT_SYMBOL_GPL.
So your problem is simply that your non-GPL module can't link a
From: Namhyung Kim
The -o/--order option is to select column number to sort a diff result.
It does the job by adding a hpp field at the beginning of the sort list.
But it should not be added to the output field list as it has no
callbacks required by a output field.
During the setup_sorting(),
On Fri, Feb 03, 2017 at 07:44:57AM -0800, Paul E. McKenney wrote:
> On Fri, Feb 03, 2017 at 02:37:48PM +0100, Peter Zijlstra wrote:
> > On Fri, Feb 03, 2017 at 01:59:34PM +0100, Mike Galbraith wrote:
> > > On Fri, 2017-02-03 at 09:53 +0100, Peter Zijlstra wrote:
> > > > On Fri, Feb 03, 2017 at 10:0
From: Stefan Kristiansson
This utilize the load-link/store-conditional l.lwa and l.swa
instructions to implement the atomic bitops.
When those instructions are not available emulation is provided.
Signed-off-by: Stefan Kristiansson
[sho...@gmail.com: remove OPENRISC_HAVE_INST_LWA_SWA config sug
From: Stefan Kristiansson
This brings it inline with the other setup oprations done like the cache
enables _ic_enable and _dc_enable. Also, this is going to make it
easier to initialize additional cpu's when smp is introduced.
Signed-off-by: Stefan Kristiansson
[sho...@gmail.com: Added commit
repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux.git
tags/perf-urgent-for-mingo-4.10-20170203
for you to fetch changes up to aa33b9b9a2ebb00d33c83a5312d4fbf2d5aeba36:
perf callchain: Reference count maps (2017-02-02 11:39:09 -0300
Hi Linus,
On 02/03/2017 08:51 AM, Linus Walleij wrote:
> Your child nodes I guess will be instatiated as devices as well.
>
> These devices will have the NBUS driver as .parent in their
> struct device I guess. Else the design of this bus is tilted.
>
> If the NBUS driver use dev_set_drvdata(dev
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