Signed-off-by: Srinivas Kandagatla
Acked-by: Bjorn Andersson
---
arch/arm/boot/dts/qcom-apq8064.dtsi | 27 +++
1 file changed, 27 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi
b/arch/arm/boot/dts/qcom-apq8064.dtsi
index 268bd47..f725e31 100644
--- a/arc
This patch adds support to PM8821 PMIC and interrupt support.
PM8821 is companion device that supplements primary PMIC PM8921 IC.
Signed-off-by: Srinivas Kandagatla
Acked-by: Rob Herring
---
Changes since v2:
- removed few empty lines spotted by Bjorn
- rephrased some debug print
On Fri, Nov 11, 2016 at 08:09:04PM +, Kammela, Gayatri wrote:
> Since this is not bug or bug fix ,I am not sure under which product
> section in https://bugzilla.kernel.org/ should I upload the document
> for these two new features.
Just do what Kan has done here:
https://bugzilla.kernel.org/
Hi
Two fixes for the simplefb setup code in arch/x86/. One to support Matt's 64bit
EFI fb-base-address, and one to fix a longer standing verification bug.
Neither fix is critical. Additionally, most people still use efifb/vesafb
instead of simplefb, so probably does not affect any normal distribu
The screen_info object was extended to support 64bit lfb_base addresses
in:
commit ae2ee627dc87a70910de91b791b3cd0e9c6facdd
Author: Matt Fleming
Date: Tue Aug 25 16:32:55 2015 +0100
efifb: Add support for 64-bit frame buffer addresses
However, the x86 simple-framebuffer se
The screen_info.lfb_size field is shifted by 16 bits *only* in case of
VBE. This has historical reasons since VBE advertised it similarly.
However, in case of EFI framebuffers, the size is no longer shifted. Fix
the x86 simple-framebuffer setup code to use the correct size in the
non-VBE case.
Whi
Hi,
On 15-11-16 12:48, Pavel Machek wrote:
Hi!
The LED you are talking about _has_ a trigger, implemented in
hardware. That trigger can change LED brightness behind kernel's (and
userspace's) back. Don't pretend the trigger does not exist, it does.
And when you do that, you'll have nice place
From: Sunil Goutham
This patchset includes fixes for incorrect LMAC credits,
unreliable driver statistics, memory leak upon interface
down e.t.c
Changes from v1:
- As suggested replaced bit shifting with BIT() macro
in the patch 'Fix configuration of L3/L4 length checking'.
Radha Mohan Chinta
HSV formats were missing the color encoding, which leads to an invalid
ycbcr_enc value during get_fmt and try_fmt.
Signed-off-by: Ricardo Ribalda Delgado
---
drivers/media/platform/vivid/vivid-vid-common.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/media/platform/vivid/vivid-v
Zero is not a valid value for hsv_enc. Set the field to a valid
initial value.
This is not a problem for vivid, because it sets the field to 180 via
tpg_s_hsv_enc() on the control initialization, but it might be a source
of errors for other drivers that use this code.
Signed-off-by: Ricardo Ribal
From: Radha Mohan Chintakuntla
This patch fixes the 'bgx_id' determination on 83xx where there are
4 BGX blocks instead of 2 on other platforms.
Signed-off-by: Radha Mohan Chintakuntla
Signed-off-by: Sunil Goutham
---
drivers/net/ethernet/cavium/thunder/thunder_bgx.c | 4 ++--
drivers/net/eth
From: Sunil Goutham
This patch fixes enabling of HW verification of L3/L4 length and
TCP/UDP checksum which is currently being cleared. Also fixed VLAN
stripping config which is being cleared when multiqset is enabled.
Signed-off-by: Sunil Goutham
---
drivers/net/ethernet/cavium/thunder/nicvf_
On Tue 2016-11-15 13:06:14, Hans de Goede wrote:
> Hi,
>
> On 15-11-16 12:48, Pavel Machek wrote:
> >Hi!
> >
> >The LED you are talking about _has_ a trigger, implemented in
> >hardware. That trigger can change LED brightness behind kernel's (and
> >userspace's) back. Don't pretend the
On Wed, Nov 09, 2016 at 06:35:13PM -0600, Tom Lendacky wrote:
> +/*
> + * AMD Secure Memory Encryption (SME) can reduce the size of the physical
> + * address space if it is enabled, even if memory encryption is not active.
> + * Adjust x86_phys_bits if SME is enabled.
> + */
> +static void phys_bi
From: Sunil Goutham
Programming LMAC credits taking 9K frame size by default is incorrect
as for an interface which is one of the many on the same BGX/QLM
no of credits available will be less as Tx FIFO will be divided
across all interfaces. So let's say a BGX with 40G interface and another
BGX w
On Tue, Nov 15, 2016 at 1:01 PM, David Herrmann wrote:
> The screen_info object was extended to support 64bit lfb_base addresses
> in:
>
> commit ae2ee627dc87a70910de91b791b3cd0e9c6facdd
> Author: Matt Fleming
> Date: Tue Aug 25 16:32:55 2015 +0100
>
> efifb: Add support for
Hi!
> Add support for OV5647 sensor.
>
> +static int ov5647_write(struct v4l2_subdev *sd, u16 reg, u8 val)
> +{
> + int ret;
> + unsigned char data[3] = { reg >> 8, reg & 0xff, val};
> + struct i2c_client *client = v4l2_get_subdevdata(sd);
> +
> + ret = i2c_master_send(client, da
From: Sunil Goutham
This patch fixes the following
1. When interface is being teardown and queues are being cleaned up,
free pending SKBs that are in SQ which are either not transmitted
or freed as NAPI is disabled by that time.
2. While interface initialization, delay CFG_DONE notification
From: Sunil Goutham
This patch fixes multiple issues
1. Convert all driver statistics to percpu counters for accuracy.
2. To avoid multiple CQEs posted by a TSO packet appended to HW,
TSO pkt's SQE has 'post_cqe' not set but a dummy SQE is added
for getting HW transmit completion notificati
On Tuesday 15 November 2016 02:27 AM, Eric W. Biederman wrote:
Peter Zijlstra writes:
On Mon, Nov 14, 2016 at 04:02:30PM +0530, Hari Bathini wrote:
PERF_RECORD_SWITCH_CPU_WIDE = 15,
+ /*
+* struct {
+* struct perf_event_headerheader;
+
On Tue, Nov 15, 2016 at 1:01 PM, David Herrmann wrote:
> The screen_info.lfb_size field is shifted by 16 bits *only* in case of
> VBE. This has historical reasons since VBE advertised it similarly.
> However, in case of EFI framebuffers, the size is no longer shifted. Fix
> the x86 simple-framebuf
On Tue, Nov 15, 2016 at 01:10:35PM +0100, Joerg Roedel wrote:
> Maybe add a comment here why you can't use cpu_has (yet).
So that could be alleviated by moving this function *after*
init_scattered_cpuid_features(). Then you can simply do *cpu_has().
Also, I'm not sure why we're checking CPUID for
From: Colin Ian King
Comparing unsigned int ret to less than zero for an error status
check is never true. Fix this by making ret a signed int. Reduce
scope of ret too.
Found with static analysis by CoverityScan, CID 1377750
Signed-off-by: Colin Ian King
---
drivers/net/ethernet/amd/xgbe/xgb
On 14/11/16 11:48, Catalin Marinas wrote:
Hi Suzuki,
+static inline bool system_supports_fpsimd(void)
+{
+ return !cpus_have_const_cap(ARM64_HAS_NO_FPSIMD);
+}
Any particular reason why using negation instead of a ARM64_HAS_FPSIMD?
A potential problem would be the default cpus_have_co
On Friday 11 November 2016 01:18 AM, Eric W. Biederman wrote:
Hari Bathini writes:
Currently, there is no trivial mechanism to analyze events based on
containers. perf -G can be used, but it will not filter events for the
containers created after perf is invoked, making it difficult to asses
On Thu, Nov 10, 2016 at 07:16:39PM +0100, Sergio Paracuellos wrote:
> +#define HFA384x_CMD_AINFO ((u16)GENMASK(14, 8))
The casts to u16 are pointless because of type promotion and half of
these defines aren't used anyway (both that I looked at).
regards,
dan carpenter
On 14.11.2016 13:13, Zubair Lutfullah Kakakhel wrote:
> The Xilinx AXI Interrupt Controller IP block is used by the MIPS
> based xilfpga platform and a few PowerPC based platforms.
>
> Move the interrupt controller code out of arch/microblaze so that
> it can be used by everyone
>
> Signed-off-by
On Sat, 2016-11-12 at 20:05 +0800, Leo Yan wrote:
> Hi Rui, Eduardo,
>
> On Wed, Aug 31, 2016 at 04:50:16PM +0800, Leo Yan wrote:
> >
> > The thermal driver is standalone driver which is used to enable
> > thermal sensors, so it can be used with any cooling device and
> > should not bind with CPU
From: Noam Camus
Till now we used clockevent from generic ARC driver.
This was enough as long as we worked with simple multicore SoC.
When we are working with multithread SoC each HW thread can be
scheduled to receive timer interrupt using timer mask register.
This patch will provide a way to con
On Thu, Nov 10, 2016 at 07:16:40PM +0100, Sergio Paracuellos wrote:
> -#define WLAN_GET_FC_FTYPE(n) u16)(n)) & (BIT(2) | BIT(3))) >> 2)
> -#define WLAN_GET_FC_FSTYPE(n)u16)(n)) & \
> - (BIT(4) | BIT(5) | BIT(6) | BIT(7))) >> 4)
> +#define WLAN_GET_FC_FTYP
On Tue, Oct 25, 2016 at 11:03:11AM +0200, Christian Borntraeger wrote:
> For spinning loops people do often use barrier() or cpu_relax().
> For most architectures cpu_relax and barrier are the same, but on
> some architectures cpu_relax can add some latency.
> For example on power,sparc64 and arc,
On Tue, 2016-11-15 at 12:08 +0100, Jiri Kosina wrote:
> On Tue, 8 Nov 2016, Bastien Nocera wrote:
>
> > In that particular case, I'd rather it got renamed to "hid-udraw-
> ps3"
> > in this case. The XBox 360 and Wii versions use completely
> different
> > protocols:
> > http://brandonw.net/udraw/
Hi Peter,
On Mon, Nov 14, 2016 at 06:39:53PM +0100, Peter Zijlstra wrote:
[...]
> +/*
> + * Similar to atomic_dec_and_test(), it will BUG on underflow and fail to
> + * decrement when saturated at UINT_MAX.
> + *
> + * Provides release memory ordering, such that prior loads and stores are
> done
On Thu, Nov 10, 2016 at 07:16:42PM +0100, Sergio Paracuellos wrote:
> This patch replace actual mask stuff using BIT macros with
> or operators to make use of GENMASK macro which simplifies
> code clearity and readibility.
>
> It applies for two bitwise operations included in prism2sta.c source
On 14.11.2016 13:13, Zubair Lutfullah Kakakhel wrote:
> Remove __func__ and prefix irq-xilinx in various debug prints
>
> Signed-off-by: Zubair Lutfullah Kakakhel
>
> ---
> V6 -> V7
> New patch
> This diff was squashed into another patch. Split it up for cleanliness
> ---
> drivers/irqchip/irq-
>From: Scott Wood
>On 11/13/2016 11:27 PM, Sriram Dash wrote:
>> diff --git a/Documentation/devicetree/bindings/phy/phy-qoriq-usb3.txt
>> b/Documentation/devicetree/bindings/phy/phy-qoriq-usb3.txt
>> new file mode 100644
>> index 000..d934c80
>> --- /dev/null
>> +++ b/Documentation/devicetree/b
From: yuanjian
Add PWM driver for the PWM controller found on HiSilicon BVT SOCs, like
Hi3519V100, Hi3516CV300, etc.
The PWM controller is primarily in charge of controlling P-Iris lens.
Reviewed-by: Jiancheng Xue
Signed-off-by: Jian Yuan
---
Change Log:
v4:
Add #pwm-cells in the bindings doc
On 14.11.2016 13:13, Zubair Lutfullah Kakakhel wrote:
> Add a global structure to house various variables.
> And cleanup read/write handling by using jump label api.
>
> Signed-off-by: Zubair Lutfullah Kakakhel
>
> ---
> V6 -> V7
> Restructure and use jump label api
> Better commit log
>
> V5 -
The patch
"clocksource/drivers/microblaze: Convert init function to return error"
(sha1: 0586421746ef2bc33898d2d7f3dbb0eec6b234c3)
introduced return value and this one was forgetten to convert.
This patch also remove compilation warning:
arch/microblaze/kernel/timer.c: In function 'xilinx_timer_in
The patch adds new syscalls copy_file_range,
preadv2, pwritev2, pkey_mprotect, pkey_alloc,
pkey_free
Signed-off-by: Michal Simek
---
arch/microblaze/include/asm/unistd.h | 2 +-
arch/microblaze/include/uapi/asm/unistd.h | 6 ++
arch/microblaze/kernel/syscall_table.S| 6 ++
3 fi
Add new fpga families where Microblaze can run on.
Signed-off-by: Michal Simek
---
arch/microblaze/kernel/cpu/cpuinfo.c | 4
1 file changed, 4 insertions(+)
diff --git a/arch/microblaze/kernel/cpu/cpuinfo.c
b/arch/microblaze/kernel/cpu/cpuinfo.c
index 48a7d81487f3..96b3f26d16be 100644
--
Add missing release version code for v9.6 and v10.0.
Signed-off-by: Michal Simek
---
arch/microblaze/kernel/cpu/cpuinfo.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/microblaze/kernel/cpu/cpuinfo.c
b/arch/microblaze/kernel/cpu/cpuinfo.c
index b70bb538f001..48a7d81487f3 100644
--
From: Colin Ian King
table_info is being dereferenced before a null check, which implies
a potential null pointer deference error. Fix this by moving the null
check of table_info to the start of smu7_get_evv_voltages to avoid
potential null pointer deferencing.
Found with static analysis by Cov
Replace uint8_t, uint16_t and uint32_t with preferred kernel types
u8, u16 and u32 respectively suggested by checkpatch.pl
Signed-off-by: Punit Vara
---
drivers/staging/ks7010/ks_wlan.h | 138 +--
drivers/staging/ks7010/michael_mic.c | 10 +--
drivers/staging
On Mon, Nov 14, 2016 at 11:16:51AM -0500, Don Dutile wrote:
> On 11/14/2016 06:56 AM, Johannes Thumshirn wrote:
> > On Wed, Nov 09, 2016 at 11:11:40AM -0600, Bjorn Helgaas wrote:
> > > Hi Johannes,
> > >
> > > On Wed, Nov 02, 2016 at 04:35:52PM -0600, Johannes Thumshirn wrote:
> > > > The Read Com
Use module_platform_driver() helper to simplify the code.
Signed-off-by: Geliang Tang
---
drivers/media/platform/soc_camera/sh_mobile_ceu_camera.c | 13 +
1 file changed, 1 insertion(+), 12 deletions(-)
diff --git a/drivers/media/platform/soc_camera/sh_mobile_ceu_camera.c
b/drivers
On Tue, Nov 15, 2016 at 5:09 AM, Viresh Kumar wrote:
> On 14-11-16, 22:51, Rafael J. Wysocki wrote:
>> From: Rafael J. Wysocki
>>
>> The cpumask_test_cpu() check in cpufreq_cpu_get_raw() is sort of
>> pointless, because it may be racy with respect to CPU online/offline
>> which sets/clears the po
On 14.11.2016 13:13, Zubair Lutfullah Kakakhel wrote:
> The Xilinx interrupt controller driver is now available in drivers/irqchip.
> Switch to using that driver.
>
> Signed-off-by: Zubair Lutfullah Kakakhel
> Acked-by: Michael Ellerman (powerpc)
>
> ---
> V6 - V7
> Rebase to v4.9-rc5
>
> V5 -
On Tuesday 15 November 2016 09:24 AM, William Wu wrote:
> This series try to correct the 480MHz output clock of USB2 PHY
> clk_ops callback and fix the delay time. It aims to make the
> 480MHz clock gate more sensible and stable.
>
> Tested on rk3366/rk3399 EVB board.
merged to phy -next.
Than
On Tue, Nov 15, 2016 at 08:33:37PM +0800, Boqun Feng wrote:
> Hi Peter,
>
> On Mon, Nov 14, 2016 at 06:39:53PM +0100, Peter Zijlstra wrote:
> [...]
> > +/*
> > + * Similar to atomic_dec_and_test(), it will BUG on underflow and fail to
> > + * decrement when saturated at UINT_MAX.
> > + *
> > + * P
On Tue, Nov 15, 2016 at 11:39:09AM +0100, Daniel Bristot de Oliveira wrote:
> Disable RT_RUNTIME_SHARE by default and document it.
>
> Cc: Ingo Molnar
> Cc: Peter Zijlstra
> Cc: Steven Rostedt
> Cc: Clark Williams
> Cc: Luis Claudio R. Goncalves
> Cc: linux-kernel@vger.kernel.org
>
> Daniel
TPS65217 interrupt register includes read/writeable mask bits with
read-only status bits. (bit 4, 5, 6 are R/W, bit 0, 1, 2 are RO)
And reserved bit is not required.
Register update operation is preferred for disabling all interrupts during
the device initialisation.
Signed-off-by: Milo Kim
---
* Peter Zijlstra wrote:
> On Tue, Nov 15, 2016 at 11:03:59AM +0100, Ingo Molnar wrote:
> > > Should I also make a CONFIG knob that implements refcount_t with the
> > > 'normal' atomic_t primitives?
> >
> > I'd suggest doing the saturation/safe-wrap semantics only for now (i.e. the
> > current
TPS65217 INT pin is used for the system wakeup from suspend mode.
This patch enables push button or charger input event as a wakeup source.
Signed-off-by: Milo Kim
---
drivers/mfd/tps65217.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/mfd/tps65217.c b/drivers/mfd/tps65217.c
ind
TPS65217 MFD is an interrupt controller and MFD slave devices like
tps65217-charger and tps65217-pwrbutton request an interrupt to handle
each HW event.
Currently, TPS65217 IRQ name is not defined, so the result is as below.
root@arm:~# cat /proc/interrupts
...
182: 0 INTC 7 Level
TPS65217 IRQ domain should be removed and initialised as NULL when the
module is unloaded for the next use. When tps65217.ko is loaded again,
it causes the page fault. This patch fixes the error below.
root@arm:~# lsmod | grep "tps"
tps65217_charger3538 0
tps65218_pwrbutton 2974 0
t
On Tue, Nov 15, 2016 at 11:12 AM, Lorenzo Pieralisi
wrote:
> Hi Rafael,
>
> On Thu, Nov 10, 2016 at 12:36:12AM +0100, Rafael J. Wysocki wrote:
>> Hi Lorenzo,
>>
>> On Wed, Nov 9, 2016 at 3:19 PM, Lorenzo Pieralisi
>> wrote:
>> > This patch series is v7 of a previous posting:
>> >
>> > https://lkm
Rework the IRQ handler by using HW IRQ number and status bit.
Each HW IRQ number is matched with TPS65217 register layout[*].
(USB IRQ number is 0, AC is 1, Push button is 2)
When an interrupt is enabled, mask bit should be cleared (unmasked).
If an interrupt is disabled, then mask bit should be
From: Gustavo Padovan
There is now a new property called IN_FENCE_FD attached to every plane
state that receives sync_file fds from userspace via the atomic commit
IOCTL.
The fd is then translated to a fence (that may be a fence_array
subclass or just a normal fence) and then used by DRM to fenc
From: Gustavo Padovan
Hi,
Yet another iteration, v12 now after working on the changes proposed by Chris
Wilson.
Robert Foss managed to port Android's drm_hwcomposer to the new HWC2 API and
added support to fences. Current patches can be seen here:
https://git.collabora.com/cgit/user/robertfoss
From: Gustavo Padovan
Create one timeline context for each CRTC to be able to handle out-fences
and signal them. It adds a few members to struct drm_crtc: fence_context,
where we store the context we get from fence_context_alloc(), the
fence seqno and the fence lock, that we pass in fence_init()
On Tue, Nov 15, 2016 at 11:38 AM, David Binderman wrote:
> Hello there,
>
> drivers/block/rbd.c:838:34: warning: logical ‘and’ of mutually exclusive
> tests is always false [-Wlogical-op]
>
> Source code is
>
>} else if (token > Opt_last_int && token < Opt_last_string) {
>
> but
>
> enum {
>
From: Gustavo Padovan
Support DRM out-fences by creating a sync_file with a fence for each CRTC
that sets the OUT_FENCE_PTR property.
We use the out_fence pointer received in the OUT_FENCE_PTR prop to send
the sync_file fd back to userspace.
The sync_file and fd are allocated/created before com
Hi,
On Wednesday 14 September 2016 06:57 PM, Peter Griffin wrote:
> This phy is only used on STiH415/6 based silicon, and support for
> these SoC's is being removed from the kernel.
>
> Signed-off-by: Peter Griffin
> Cc:
I've merged the 1st 2 patches of this series. Since Patrice has already
m
When attaching a group to the container, handle the group's
reserved regions and particularly the IOMMU_RESV_MSI region
which requires an IOVA allocator to be initialized through
the iommu_get_msi_cookie API. This will allow the MSI IOVAs
to be transparently allocated on MSI controller's compose().
A new iommu-group sysfs attribute file is introduced. It contains
the list of reserved regions for the iommu-group. Each reserved
region is described on a separate line:
- first field is the start IOVA address,
- second is the end IOVA address,
Signed-off-by: Eric Auger
---
The file layout is i
Following LPC discussions, we now report reserved regions through
iommu-group sysfs reserved_regions attribute file.
Reserved regions are populated through the IOMMU get_resv_region callback
(former get_dm_regions), now implemented by amd-iommu, intel-iommu and
arm-smmu.
The intel-iommu reports t
This patch registers the [FEE0_h - FEF0_000h] 1MB MSI range
as a reserved region. This will allow to report that range
in the iommu-group sysfs.
Signed-off-by: Eric Auger
---
RFCv2 -> RFCv3:
- use get/put_resv_region callbacks.
RFC v1 -> RFC v2:
- fix intel_iommu_add_reserved_regions name
IOMMU domain users such as VFIO face a similar problem to DMA API ops
with regard to mapping MSI messages in systems where the MSI write is
subject to IOMMU translation. With the relevant infrastructure now in
place for managed DMA domains, it's actually really simple for other
users to piggyback o
Introduce a new helper serving the purpose to allocate a reserved
region. This will be used in iommu driver implementing reserved
region callbacks.
Signed-off-by: Eric Auger
---
drivers/iommu/iommu.c | 16
include/linux/iommu.h | 8
2 files changed, 24 insertions(+)
We want to extend the callbacks used for dm regions and
use them for reserved regions. Reserved regions can be
- directly mapped regions
- regions that cannot be iommu mapped (PCI host bridge windows, ...)
- MSI regions (because they belong to another address space or because
they are not transla
Introduce iommu_get_group_resv_regions whose role consists in
enumerating all devices from the group and collecting their
reserved regions. It checks duplicates.
Signed-off-by: Eric Auger
---
- we do not move list elements from device to group list since
the iommu_put_resv_regions() could not
On Monday 07 November 2016 06:35 PM, Alexandre Bailon wrote:
> If we configure the da8xx OTG phy in OTG mode, neither device or host
> mode will work. That is because the PHY is not able to detect and notify
> the driver that value of ID pin changed.
> To work despite this hardware limitation, th
The get() populates the list with the PCI host bridge windows
and the MSI IOVA range.
At the moment an arbitray MSI IOVA window is set at 0x800
of size 1MB. This will allow to report those info in iommu-group
sysfs?
Signed-off-by: Eric Auger
---
RFC v2 -> v3:
- use existing get/put_resv_re
IOMMU_RESV_NOMAP is used to tag reserved IOVAs that are not
supposed to be IOMMU mapped. IOMMU_RESV_MSI tags IOVAs
corresponding to MSIs that need to be IOMMU mapped.
IOMMU_RESV_MASK allows to check if the IOVA is reserved.
Signed-off-by: Eric Auger
---
include/linux/iommu.h | 4
1 file ch
As we introduced IOMMU_RESV_NOMAP and IOMMU_RESV_MSI regions,
let's prevent those new regions from being mapped.
Signed-off-by: Eric Auger
---
drivers/iommu/iommu.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c
index 6ee529f..a4530ad 100644
From: Fu Wei
This patch defines pr_fmt(fmt) for all pr_* functions,
then the pr_* doesn't need to add "arch_timer:" everytime.
According to the suggestion from checkpatch.pl:
(1) delete some Blank Spaces in arch_timer_banner;
(2) delete a redundant Tab in a bland line of arch_timer_init(void)
N
From: Fu Wei
This patch add a new enum "arch_timer_spi_nr" and use it in the driver.
Just for code's readability, no functional change.
Signed-off-by: Fu Wei
Acked-by: Mark Rutland
---
drivers/clocksource/arm_arch_timer.c | 4 ++--
include/clocksource/arm_arch_timer.h | 6 ++
2 files chan
From: Fu Wei
The patch fix a potential bug about arch_timer_uses_ppi in
arch_timer_register.
On ARM64, we don't use ARCH_TIMER_PHYS_SECURE_PPI in Linux, so we will
just igorne it in init code. If arch_timer_uses_ppi is
ARCH_TIMER_PHYS_NONSECURE_PPI, the orignal code of
arch_timer_uses_ppi may go
From: Fu Wei
To support the arm_arch_timer via ACPI we need to share defines and enums
between the driver and the ACPI parser code.
Split out the relevant defines and enums into arm_arch_timer.h, and
change "enum ppi_nr" to "enum arch_timer_ppi_nr" to avoid the potential
name clashes.
No functio
From: Fu Wei
Rename some enums and defines, to unify the format of enums and defines
in arm_arch_timer.h, also update all the users of these enums and defines:
drivers/clocksource/arm_arch_timer.c
virt/kvm/arm/hyp/timer-sr.c
And do some cleanups, according to the suggestion from checkpatc
From: Fu Wei
This patchset:
(1)Preparation for adding GTDT support in arm_arch_timer:
1. Move some enums and marcos to header file;
2. Add a new enum for spi type;
3. Improve printk relevant code.
4. rename some enums and defines, and some cleanups.
5.
From: Fu Wei
The patch refactor original memory-mapped timer init code:
(1) Extract a subfunction for detecting a bast time frame:
is_best_frame.
(2) Refactor "arch_timer_mem_init", make it become a common code for
memory-mapped timer init.
(3) Add a new function "arch
From: Fu Wei
This patch adds support for parsing arch timer in GTDT,
provides some kernel APIs to parse all the PPIs and
always-on info in GTDT and export them.
By this driver, we can simplify arm_arch_timer drivers, and
separate the ACPI GTDT knowledge from it.
Signed-off-by: Fu Wei
Signed-of
From: Fu Wei
The patch introduce two new structs:
arch_timer_mem,
arch_timer_mem_frame.
And also introduce a new define: ARCH_TIMER_MEM_MAX_FRAMES
These will be used for refactoring the memory-mapped timer init code to
prepare for GTDT
Signed-off-by: Fu Wei
---
include/clockso
From: Fu Wei
The patch refactor original arch_timer_uses_ppi init code:
(1) Extract a subfunction: arch_timer_uses_ppi_init
(2) Use the new subfunction in arch_timer_of_init and
arch_timer_acpi_init
Signed-off-by: Fu Wei
---
drivers/clocksource/arm_arch_timer.c | 73 +--
allows better debugging as freeing audit buffers now always honors slub
debug hooks (e.g. object poisoning) and leak checker can detect the
free operation.
Removal also results in a small speedup (using
single rule 'iptables -A INPUT -i lo -j AUDIT --type drop'):
super_netperf 4 -H 127.0.0.1 -l 3
From: Fu Wei
The patch add memory-mapped timer register support by using the
information provided by the new GTDT driver of ACPI.
Signed-off-by: Fu Wei
---
drivers/clocksource/arm_arch_timer.c | 26 +-
1 file changed, 25 insertions(+), 1 deletion(-)
diff --git a/driver
On 15 November 2016 10:47:52 GMT+00:00, Fabrice Gasnier
wrote:
>On 11/14/2016 05:47 PM, Lee Jones wrote:
>> On Sat, 12 Nov 2016, Jonathan Cameron wrote:
>>
>>> On 10/11/16 16:18, Fabrice Gasnier wrote:
Add core driver for STMicroelectronics STM32 ADC (Analog to Digital
Converter). STM
From: Fu Wei
The patch update arm_arch_timer driver to use the function
provided by the new GTDT driver of ACPI.
By this way, arm_arch_timer.c can be simplified, and separate
all the ACPI GTDT knowledge from this timer driver.
Signed-off-by: Fu Wei
Signed-off-by: Hanjun Guo
---
drivers/clocks
TPS65217 can be built as a module, this patch-set includes the error fix
and rework the interrupt handler.
Additionally, TPS65217 INT pin is registered as a system wakeup source.
Milo Kim (5):
mfd: tps65217: Fix page fault on unloading modules
mfd: tps65217: Specify the IRQ name
mfd: tps652
From: Fu Wei
On platforms booting with ACPI, architected memory-mapped timers'
configuration data is provided by firmware through the ACPI GTDT
static table.
The clocksource architected timer kernel driver requires a firmware
interface to collect timer configuration and configure its driver.
thi
From: Fu Wei
This driver adds support for parsing SBSA Generic Watchdog timer
in GTDT, parse all info in SBSA Generic Watchdog Structure in GTDT,
and creating a platform device with that information.
This allows the operating system to obtain device data from the
resource of platform device. The
On Wed, 2016-11-02 at 10:04 +0100, Filip Matusiak wrote:
> This is a workaround for VHT-enabled STAs which break the spec
> and have the VHT-MCS Rx map filled in with value 3 for all eight
> spacial streams, an example is AR9462 in AP mode.
>
> As per spec, in section 22.1.1 Introduction to the VH
TPS65217 has two charger interrupts - AC or USB power status change.
Interrupt request:
If an interrupt number is not defined, then use legacy polling thread.
Otherwise, create IRQ threads to handle AC or USB charger event.
Interrupt handler:
Check not only AC but also USB charger status.
AC and USB charger are supported, so generic names are preferred.
ac in tps65217_charger -> psy
tps65217_ac_props -> tps65217_charger_props
tps65217_ac_get_property -> tps65217_charger_get_property
tps65217-ac -> tps65217-charger
Cc: Enric Balletbo i Serra
Signed-off-by: Milo Kim
---
d
TPS65217 device supports two charger inputs - AC and USB.
Currently, only AC charger is supported. This patch-set adds USB charger
feature. Tested on Beaglebone black.
Milo Kim (5):
power: supply: tps65217: Move IRQ related operation into single
function
power: supply: tps65217: Remove IR
Hi, Greg
2016-11-15 18:18 GMT+08:00 Greg KH :
> On Tue, Nov 15, 2016 at 05:55:39PM +0800, Ganesh Mahendran wrote:
>> VM_IOREMAP is used to access hardware through a mechanism called
>> I/O mapped memory. Android binder is a IPC machanism which will
>> not access I/O memory.
>>
>> Also VM_IOREMAP h
IRQ number is only used on requesting the interrupt, so no need to keep
it inside the driver data.
In case of polling, poll_task is valid only when polling thread is
activated.
Cc: Enric Balletbo i Serra
Signed-off-by: Milo Kim
---
drivers/power/supply/tps65217_charger.c | 18 +-
On 11/15/2016 01:30 PM, Russell King - ARM Linux wrote:
> On Tue, Oct 25, 2016 at 11:03:11AM +0200, Christian Borntraeger wrote:
>> For spinning loops people do often use barrier() or cpu_relax().
>> For most architectures cpu_relax and barrier are the same, but on
>> some architectures cpu_relax c
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